DETAILED ACTION
The present application, filed 03/19/2024, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Drawings
Figures 1-3 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Aizawa (US 2008/0106245).
Re claim 1, Aizawa teaches a regulator voltage detection circuit [Fig 7] that outputs a detection signal [output of 8] indicating a voltage change of a regulator voltage [Po] output from a regulator circuit based on a reference voltage [at + terminal of 8], the regulator voltage detection circuit comprising: a load element [R34] including a first terminal and a second terminal, a current being supplied from a constant current circuit [CS2] to the first terminal, the second terminal receiving the regulator voltage [Po]; and a comparator [8] including a first input terminal connected to the first terminal and a second input terminal receiving the reference voltage, the comparator outputting the detection signal [as shown in Fig 7].
Re claim 2, Aizawa teaches wherein the load element is a single resistor [paragraph 90].
Re claim 3, Aizawa teaches a semiconductor device [Fig 7] including a regulator voltage detection circuit that outputs a detection signal [output of 8] indicating a voltage change of a regulator voltage [Po] output from a regulator circuit based on a reference voltage [at + terminal of 8], the semiconductor device comprising: a load element [R34] including a first terminal and a second terminal, a current being supplied from a constant current circuit [CS2] to the first terminal, the second terminal receiving the regulator voltage [Po]; and a comparator [8] including a first input terminal connected to the first terminal and a second input terminal receiving the reference voltage, the comparator outputting the detection signal [as shown in Fig 7].
Conclusion
Examiner's Note:
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAKAISHA JACKSON whose telephone number is (571)270-3111. The examiner can normally be reached on M-F 8:00-5:00.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MONICA LEWIS can be reached on 571-272-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LaKaisha Jackson/
Examiner, Art Unit 2838