Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 2-21 are pending.
This is in response to communications filed on 2/5/26.
The terminal disclaimer filed on 2/5/26 is approved.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 2-4, 8, 19-21 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Sharon et al (US Patent 11416263; cited in IDS).
For claim 2, Sharon et al teach the following limitations: A memory system (data storage device 106 in Fig 1), comprising: one or more memory devices (110, 112 and 116 and other memories shown in Fig 1); and processing circuitry coupled with the one or more memory devices (controller 108 in Fig 1; Fig 2 shows the controller with processing circuitry) and configured to cause the memory system to: receive, by the memory system, one or more access commands as part of a boot-up procedure (Fig 3 shows a boot operation; step 306 mentions that fetched data is collected; the boot operation includes command lines 20-37 of col 5 lines 1-10 of col 8), each command of the one or more access commands associated with a respective logical address of a plurality of logical addresses associated with the memory system (line 45, col 7 through line 55, col 8 mentions the reading for boot operation - “pre-fetch next LBA from the NVM”; “boot data may be retrieved from relevant location in an NVM” lines 40-43 of col 7; thus, each access command is associated with the respective LBA of the plural LBAs); determine, by the memory system, whether a logical address of the plurality of logical addresses is accessed as part of the boot-up procedure based at least in part on the one or more access commands (lines 15-50 of col 8; “boot data may be retrieved from relevant location in an NVM” lines 40-43 of col 7; step 306 – step 312 in Fig 3; LBA from NVM is read/fetched lines 1-51 of col 8; comparing requested LBA to predicted LBA – determining whether logical address is accessed line 42 col 8); decrement, by the memory system, a value of a counter associated with the logical address by a first quantity based at least in part on determining that the logical address is not accessed as part of the boot-up procedure (lines 35-55 of col 8 – comparing requested LBA to predicted LBA to determine a match, for mismatch decrement hit rate and prediction accuracy; thus the accuracy counter and hit rate counter is decreased when mismatch occurs for an LBA; Fig 3 step 310 step 312), wherein the first quantity is based at least in part on a quantity of previous boot-up procedures performed by the memory system (prediction accuracy and hit rate both are based on past boot history as mentioned in lines 1-55 of col 8; these two counters are decreased when mismatch occurs); and store, at the memory system, an address mapping comprising the plurality of logical addresses based at least in part on decrementing the counter (database update (i.e., address mapping update) is shown as steps 306 -step 308, which is based on step 310 and step 312 (i.e., counter decrement) as shown in Fig 3; the address mapping includes the database 214 of Fig 2, prediction accuracy metrics and hit rate; the update of the database including the LBAs, prediction accuracy and hit rate is mentioned in lines 1-55 of col 8).
For claim 3, Sharon et al teach wherein the processing circuitry is further configured to cause the memory system to: receive one or more second access commands as part of a second boot-up procedure (Fig 3 shows a loop; thus there is multiple boot procedure; the second boot accesses second access commands step 306), each second access command of the one or more second access commands associated with a respective logical address (line 35, col 7 through line 67, col 8); increment, for each second access command of the one or more second access commands that is associated with the logical address, the value of the counter by a second quantity (lines 35-55 of col 8 – comparing requested LBA to predicted LBA to determine a match, for match increment hit rate and prediction accuracy; thus the accuracy counter and hit rate counter is increased/incremented when match occurs for an LBA; Fig 3 step 310 step 312), wherein the first quantity is greater the second quantity (Fig 3 shows plural boot up procedure and multiple update in one boot procedure; thus, when more matches occur in one boot procedure than mismatch in another boot procedure, the first quantity is greater than second quantity); and update the address mapping based at least in part on incrementing the counter (database update (i.e., address mapping update) is shown as steps 306 -step 308, which is based on step 310 and step 312 (i.e., counter decrement/increment) as shown in Fig 3; the address mapping includes the database 214 of Fig 2, prediction accuracy metrics and hit rate; the update of the database including the LBAs, prediction accuracy and hit rate is mentioned in lines 1-55 of col 8).
For claim 4, Sharon et al teach the following limitations, wherein the first quantity is greater than one based at least in part on the quantity of previous boot-up procedures performed by the memory system (Fig 3 shows that previous boot history defines the prediction and hit rate; lines 1-55 of col 8).
For claim 8, Sharon teaches wherein, to update the address mapping, the processing circuitry is further configured to cause the memory system to: update, in response to decrementing the value of the counter, an order of the plurality of logical addresses of the address mapping (step 316 rearrange in the memory), wherein the order is based at least in part on a respective counter value associated with each logical address of the plurality of logical addresses (step 316 is based on step 312; lines 50-67 of col 8 – the rearrangement stores data sequentially; the counter value indicates prediction accuracy and considered in the rearrangement).
For claim 19, Sharon et al teach the following limitations A non-transitory computer-readable medium storing code comprising instructions (lines 55, col 9 through line 2, col 10) which, when executed by one or more processors (controller 108 in Fig 1; Fig 2 shows the controller with processing circuitry) of memory system (110, 112 and 116 and other memories shown in Fig 1), cause the memory system to: receive, by the memory system, one or more access commands as part of a boot-up procedure (Fig 3 shows a boot operation; step 306 mentions that fetched data is collected; the boot operation includes command lines 20-37 of col 5 lines 1-10 of col 8), each command of the one or more access commands associated with a respective logical address of a plurality of logical addresses associated with the memory system (line 45, col 7 through line 55, col 8 mentions the reading for boot operation - “pre-fetch next LBA from the NVM”; “boot data may be retrieved from relevant location in an NVM” lines 40-43 of col 7; thus, each access command is associated with the respective LBA of the plural LBAs); determine, by the memory system, whether a logical address of the plurality of logical addresses is accessed as part of the boot-up procedure based at least in part on the one or more access commands (lines 15-50 of col 8; “boot data may be retrieved from relevant location in an NVM” lines 40-43 of col 7; step 306 – step 312 in Fig 3; LBA from NVM is read/fetched lines 1-51 of col 8; comparing requested LBA to predicted LBA – determining whether logical address is accessed line 42 col 8); decrement, by the memory system, a value of a counter associated with the logical address by a first quantity based at least in part on determining that the logical address is not accessed as part of the boot-up procedure (lines 35-55 of col 8 – comparing requested LBA to predicted LBA to determine a match, for mismatch decrement hit rate and prediction accuracy; thus the accuracy counter and hit rate counter is decreased when mismatch occurs for an LBA; Fig 3 step 310 step 312), wherein the first quantity is based at least in part on a quantity of previous boot-up procedures performed by the memory system (prediction accuracy and hit rate both are based on past boot history as mentioned in lines 1-55 of col 8; these two counters are decreased when mismatch occurs); and store, at the memory system, an address mapping comprising the plurality of logical addresses based at least in part on decrementing the counter (database update (i.e., address mapping update) is shown as steps 306 -step 308, which is based on step 310 and step 312 (i.e., counter decrement) as shown in Fig 3; the address mapping includes the database 214 of Fig 2, prediction accuracy metrics and hit rate; the update of the database including the LBAs, prediction accuracy and hit rate is mentioned in lines 1-55 of col 8).
For claim 20, Sharon et al teach wherein the processing circuitry is further configured to cause the memory system to: receive one or more second access commands as part of a second boot-up procedure (Fig 3 shows a loop; thus there is multiple boot procedure; the second boot accesses second access commands step 306), each second access command of the one or more second access commands associated with a respective logical address (line 35, col 7 through line 67, col 8); increment, for each second access command of the one or more second access commands that is associated with the logical address, the value of the counter by a second quantity (lines 35-55 of col 8 – comparing requested LBA to predicted LBA to determine a match, for match increment hit rate and prediction accuracy; thus the accuracy counter and hit rate counter is increased/incremented when match occurs for an LBA; Fig 3 step 310 step 312), wherein the first quantity is greater the second quantity (Fig 3 shows plural boot up procedure and multiple update in one boot procedure; thus, when more matches occur in one boot procedure than mismatch in another boot procedure, the first quantity is greater than second quantity); and update the address mapping based at least in part on incrementing the counter (database update (i.e., address mapping update) is shown as steps 306 -step 308, which is based on step 310 and step 312 (i.e., counter decrement/increment) as shown in Fig 3; the address mapping includes the database 214 of Fig 2, prediction accuracy metrics and hit rate; the update of the database including the LBAs, prediction accuracy and hit rate is mentioned in lines 1-55 of col 8).
For claim 21, Sharon et al teach the following limitations, wherein the first quantity is greater than one based at least in part on the quantity of previous boot-up procedures performed by the memory system (Fig 3 shows that previous boot history defines the prediction and hit rate; lines 1-55 of col 8).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sharon et al (US Patent 11416263).
For claim 6, Sharon teaches wherein, to update the address mapping, the processing circuitry is further configured to cause the memory system to: compare the value of the counter to at least one second value associated with one or more second counters based at least in part on decrementing the value of the counter (lines 11-50 of col 8 mention that prediction accuracy metric is compared with certain threshold value, which can be anywhere between 50-100%, thus the threshold value is associated with another counter set by the user; Fig 3 shows decrement and loop of the operations – any operation is based on the previous operation).
For the limitations “remove the logical address from the address mapping based at least in part on comparing the value to the at least one second value”, Sharon does not explicitly mention about removing the LBA from the database 214. However, Sharon mentions detecting prediction accuracy, hit rate and database update (lines 1-55 of col 8). Delete/remove of entries from database is known in the art. It would have been obvious for one ordinary skill in the art before the effective filing date of the invention to remove an entry from the database to make room for the database for further entries. Sharon determines the hit rate/prediction accuracies of the LBAs. For least used LBAs/least accurate LBAs, the entries can be removed from the database.
For claim 7, for the limitations “remove the logical address from the address mapping based at least in part on the value of the counter satisfying a threshold value after decrementing the value”, Sharon does not explicitly mention about removing the LBA from the database 214. However, Sharon mentions detecting prediction accuracy, hit rate and database update (lines 1-55 of col 8). Delete/remove of entries from database is known in the art. It would have been obvious for one ordinary skill in the art before the effective filing date of the invention to remove an entry from the database to make room for the database for further entries. Sharon determines the hit rate/prediction accuracies of the LBAs. For least used LBAs/least accurate LBAs, the entries can be removed from the database.
Allowable Subject Matter
Claims 5, 9-18 are allowed.
Response to Arguments
Applicant's arguments regarding claims 2 and 19 have been fully considered but they are not persuasive.
Applicant argues that Sharon does not disclose at least "decrement a value of a counter associated with the logical address by a first quantity based at least in part on determining that the logical address is not accessed as part of the boot-up procedure," as recited in amended independent claim 2. According to applicant, Sharon’s LBA is always being accessed and updating the hit rate is not in relation to whether requested or predicted LBA was or was not accessed. Applicant further argues that Sharon requires an actual access command to be performed for a given LBA, which does not teach the claim limitations.
Examiner disagrees. Applicant did not mention the supporting paragraphs for the newly added limitations. It appears that Applicant’s specification para [0049] and [0061] provide the necessary support for the limitations for claim 2 and 19. According to Applicant’s disclosure para [0049], counter is decremented when commands do not have LBA that was accessed during previous boot procedure. According to Sharon, the predicted LBA is not part of the command when there is mismatch (i.e., requested LBA is different from predicted LBA). In other words, predicted LBA is not accessed as part of the boot procedure because it is not same as requested LBA and it is not part of the access commands. Claim requires whether a logical address is accessed as part of the boot up procedure is based on the access commands. Therefore, according to claim, the access command determines whether a logical address is accessed as part of the boot procedure. The “mismatch condition” sufficiently teaches “logical address is not accessed as part of boot-up procedure” because the command does not include the predicted LBA. Further, Sharon does not always pre-fetch data for predicted LBA. The predicted LBA has associated prediction accuracy metric. For low prediction accuracy metric, next LBA is predicted but not retrieved. The prediction accuracy metric is decremented when predicted LBA differs from requested LBA. According to Sharon lines 10-55 of col 8,
For prediction of the next LBA, a hash is computed on the sequence of previously read “n” LBAs. The hash result is used for accessing the database and predicting the next LBA. The prediction may include a prediction accuracy metric. Then, the manager 218 may decide to pre-fetch the next LBA from the NVM 224, before the next LBA is requested by the host 202. The pre-fetching may be a function of the prediction accuracy metric being sufficiently high. For example, if the prediction accuracy metric is above some certain value, such as about 75% then the next LBA is retrieved. However, for low prediction accuracy metrics, the next LBA may be predicted, but not retrieved. It is to be understood that previously listed value is not intended to be limiting, but to provide an example of a possible embodiment. For example, the prediction accuracy metric value threshold may be any number between about 50% to about 100%. Furthermore, the prediction accuracy metric may be updated for each boot operation or for each prediction performed.
At block 312, the manager 218 updates the hit rate of the data corresponding with the fetched data in the database 214. For example, a hit rate may be provided for each command/pattern of data separately, such that the most frequently utilized or fetched commands/patterns may be easily identified. For example, the hit rate may be updated each time a new read command is received from the host 202. The hit rate may be updated by comparing the requested LBA to the predicted LBA (e.g. as obtained from the database using the hash of previous read LBAs). Each time a match is found between requested LBA and predicted LBA then hit rate and/or prediction accuracy metric is increased and vice-versa.
Therefore, Sharon sufficiently teaches the claim limitations “decrement a value of a counter associated with the logical address by a first quantity based at least in part on determining that the logical address is not accessed as part of the boot-up procedure."
Conclusion
PTO-892 cites Yang et al that teaches tracking access frequency of chunks (Fig 8 and [0040]-[0043]); however, Yang does not mention chunks or LBAs are part of boot up procedure.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/FAHMIDA RAHMAN/Primary Examiner, Art Unit 2175
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