CTNF 18/610,227 CTNF 99838 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement The information disclosure statement (IDS) submitted on March 19, 2024 is in compliance with the provisions of 37 CFR 1.97 and 1.98. Accordingly, the IDS is being considered by the Examiner. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-20-02-aia AIA This application currently names joint inventors. In considering patentability of the claims the Examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. 07-21-aia AIA Claims 1-3, 5, 6, 8-10, an d 15-17 are rejected un der 35 U.S.C. 103 as being unpatentable over US 2022/033 6650 A1 (Chen) in view of US 2019/0280093 A1 (Curatola). Regarding c laim 1, Chen discloses, A method ([0001]) comprising: forming a channel layer (channel layer (108); FIG. 9; [0019]) on a semiconductor substrate (substrate (101); FIG. 9; [0019]) , the channel layer (108) including a gallium nitride (GaN) material ([0020]) ; PNG media_image1.png 488 791 media_image1.png Greyscale forming a barrier layer (barrier layer (110); FIG. 9; [0019]) on the channel layer (108) ; forming a first semiconductor device (first semiconductor device (Ra); FIG. 9; [0027]) on the semiconductor substrate (101) , the first semiconductor device (Ra) including a first terminal (first terminal (112a); FIG. 9; [0025]) over the barrier layer (110) ; and forming a second semiconductor device (second semiconductor device (Rb); FIG. 9; [0027]) on the semiconductor substrate (101) , the second semiconductor device (Rb) including a second terminal (second terminal (112b); FIG. 9; [0025]) over the barrier layer (110) . But, Applicant may argue that Chen does not explicitly disclose, the first semiconductor device (Ra) having a first threshold voltage; and the second semiconductor device (Rb) having a second threshold voltage different from the first threshold voltage, in which the first and second threshold voltages are both positive or negative voltages. However, in analogous art, Curatola discloses that it was well known to one of ordinary skill in the art before the effective filing date of the claimed invention that a threshold voltage (V TH ) of a gate structure (gate structure (122); FIG. 3; [0027]) can be predicably controlled by fabricating a thickness (thicknesses (136 and 138) FIG. 3; [0038]) of a barrier layer (barrier layer (108); FIG. 3; [0021]) to be relatively thicker or thinner ([0041]). PNG media_image2.png 742 978 media_image2.png Greyscale Therefore, it would have been obvious to one or ordinary skill in the art before the effective filing date of the claimed invention having the teachings of Chen and Curatola before him/her that the first semiconductor device (Ra) of Chen can be predicably fabricated to have a first threshold voltage and the second semiconductor device (Rb) of Chen can be predicably fabricated to have a second threshold voltage different from the first threshold volage by controlling the relative thicknesses of the barrier layer (110) of Chen, as taught by Curatola. But, Applicant may still argue that the Chen in view of Curatola does not appear to explicitly disclose that the first and second threshold voltages are both positive or negative voltages. However, there are a finite number of predicable solutions regarding the relative polarities of the first and second threshold voltages —i.e., the first and second threshold voltages can be: (i) different polarities or (ii) both positive or negative —and, absent unexpected results, it would have be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention having the teachings of Chen and Curatola before him/her to try each of these predicable solutions with a reasonable expectation of success one of which is that the first and second threshold voltages are both positive or negative voltages , as recited in claim 1. Please see, MPEP 2143(E)—“Obvious To Try”—Choosing From a Finite Number of Identified, Predicable Solutions, With a Reasonable Expectation of Success. Regarding claim 2, Chen in view of Curatola discloses, The method ([0001]) of claim 1, wherein forming the first semiconductor device (Ra) and forming the second semiconductor device (Rb) includes: forming a layer of a semiconductor material (112a and 112b are both semiconductor layers; [0025] of Chen) over the barrier layer (110) ; forming a layer of a metal (layer of a metal (166a and 166b); FIG. 9; [0037], all of Chen) ; patterning the layer of the semiconductor material (112a and 112b) to form the first terminal (first terminal (112a); FIG. 9; [0025], all of Chen) ; patterning the layer of the semiconductor material (112a and 112b) to form the second terminal (second terminal (112b); FIG. 9; [0025], all of Chen) ; patterning the layer of the metal (166a and 166b) to form a first metal contact (first metal contact (166a); FIG. 9; [0037], all of Chen) on the first terminal (112a) ; and patterning the layer of the metal (166a and 166b) to form a second metal contact (second metal contact (166b); FIG. 9; [0037], all of Chen) on the second terminal (112b) . Regarding claim 3, Chen in view of Curatola discloses, The method ([0001]) of claim 2, wherein the semiconductor material (112a and 112b) includes a p-type doped GaN material ([0022]) . Regarding claim 5, Chen in view of Curatola discloses, The method ([0001]) of claim 2, wherein the layer of the metal (166a and 166b) is formed on the first terminal (112a) and the second terminal (112b) . Regarding claim 6, Chen in view of Curatola discloses, The method ([0001]) of claim 2, wherein the first terminal (112a) has a first thickness (annotated FIG. 9, above) over a surface of the barrier layer (110) , and the second terminal (112b) has a second thickness (annotated FIG. 9, above) over the surface of the barrier layer (110). But, Applicant may argue that Chen in view of Curatola does not appear to explicitly disclose, the second thickness being different from the first thickness. However, there are a finite number of predicable solutions regarding a first thickness of the first terminal (112a) of Chen in view of Curatola over a surface of the barrier layer (110) thereof relative to a second thickness of the second terminal (112b) of Chen in view of Curatola over a surface of the barrier layer (110)—i.e., (i) the second thickness can be the same as the first thickness or (ii) the second thickness can be different from the first thickness —and, absent unexpected results, it would have be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention having the teachings of Chen and Curatola before him/her to try each of these predicable solutions with a reasonable expectation of success one of which is that the second thickness being different from the first thickness , as recited in claim 6. Please see, MPEP 2143(E), above. Regarding claim 8, Chen in view of Curatola discloses, The method ([0001]) of claim 2, wherein the first terminal (112a) is on the barrier layer (110) , and the second terminal (second terminal (132); FIG. 3; [0030], all of Curatola) extends into the barrier layer (110 and/or (barrier layer (108); FIG. 3; [0021], all of Curatola) . Regarding claim 9, Chen in view of Curatola discloses, The method ([0001]) of claim 8, wherein forming the first semiconductor device (Ra) and forming the second semiconductor device (Rb) includes: etching ([0047] of Curatola) the barrier layer (barrier layer (108); FIG. 3; [0021], all of Curatola) to form a recess (recess (136 and 142); FIG. 3; [0039], all of Curatola) ; and forming the semiconductor material (semiconductor material (124); FIG. 3; [0027], all of Curatola) on the barrier layer (108) , in which part of the layer of the semiconductor material (124) conforms (FIG. 3 of Curatola) with the recess (136 and 142) ; wherein patterning the layer of the semiconductor material (112a and 112b) to form the first terminal (112a) includes patterning the layer of the semiconductor material (112a and 112b) to form the first terminal (112a) on the barrier layer (110) ; and wherein patterning the layer of the semiconductor material (112a and 112b) to form the second terminal (112b) includes patterning the layer of the semiconductor material (112a and 112b) to form the second terminal (112b and/or 124) at least partially in the recess (136 and 142) . Regarding claim 10, Chen in view of Curatola discloses, The method ([0001]) of claim 2, further comprising: patterning the layer of the metal to form a third metal contact (third metal contact (118); FIG. 3; [0025], all of Curatola) on the barrier layer (108 of Curatola) , the third metal contact (118) electrically coupled ([0026] of Curatola) to the second metal contact (second metal contact (120); FIG. 3; []0025], all of Curatola) . Regarding claim 15, Chen in view of Curatola discloses, The method ([0001]) of claim 2, wherein the first terminal (112a) is a first gate ([0025] of Chen) having a first gate length (annotated FIG. 9, above) , and the second terminal is a second gate ([0025] of Chen) having a second gate length (annotated FIG. 9, above) ; wherein patterning the layer of the semiconductor material (112a and 112b) to form the first terminal (112a) includes patterning the layer of the semiconductor material (112a and 112b) to form the first gate ([0025] of Chen) having the first gate length (annotated FIG. 9, above) ; and wherein patterning the layer of the semiconductor material (112a and 112b) to form the second terminal (112b) includes patterning the layer of the semiconductor material (112a and 112b) to form the second gate ([0025] of Chen) having the second gate length (annotated FIG. 9, above) . But, Applicant may argue that Chen in view of Curatola does not appear to explicitly disclose, a second gate length different from the first gate length. However, there are a finite number of predicable solutions regarding a second gate length (annotated FIG. 9, above) of Chen in view of Curatola relative to a first gate length (annotated FIG. 9, above) thereof—i.e., the second gate length can be: (i) the same as the first gate length or (ii) different than the first gate length –and, absent unexpected results, it would have be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention having the teachings of Chen and Curatola before him/her to try each of these predicable solutions with a reasonable expectation of success one of which is that a second gate length (annotated FIG. 9, above) different from the first gate length (annotated FIG. 9, above), as recited in claim 15. Please see, MPEP 2143(E), above. Regarding claim 16, Chen in view of Curatola discloses, The method ([0001]) of claim 2, the second metal contact (166b) has a different lateral footprint (annotated FIG. 9, above) from the second terminal (112b) . But, Applicant may argue that Chen in view of Curatola does not appear to explicitly disclose, wherein the first metal contact has a same lateral footprint as the first terminal. However, there are a finite number of predicable solutions regarding a lateral footprint of the first metal contact (166a) of Chen in, view of Curatola relative to a lateral footprint of the first terminal (112a) thereof—i.e., a lateral footprint of the first metal contact (166a) can be: (i) different from a lateral footprint of the first terminal (112a) or (ii) the same as a lateral footprint of the first terminal (112a) –and, absent unexpected results, it would have be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention having the teachings of Chen and Curatola before him/her to try each of these predicable solutions with a reasonable expectation of success one of which is that wherein the first metal contact (166a) has a same lateral footprint as the first terminal (112a), as recited in claim 16. Please see, MPEP 2143(E), above. Regarding claim 17, Chen in view of Curatola discloses The method ([0001]) of claim 2, wherein the layer of the semiconductor material (112a and 112b) forming the first terminal (112a) and the layer of the semiconductor material (112a and 112b) forming the second terminal (112b) have dopant concentrations ([0032] of Curatola) . But, Applicant may argue that Chen in view of Curatola does not appear to explicitly disclose, different dopant concentrations . However, there are a finite number of predicable solutions regarding dopant concentrations of the layer of the semiconductor material (112a and 112b) forming the first terminal (112a) and the layer of the semiconductor material (112a and 112b) forming the second terminal (112b) of Chen in, view of Curatola—i.e., the dopant concentrations can be: (i) the same or (ii) different –and, absent unexpected results, it would have be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention having the teachings of Chen and Curatola before him/her to try each of these predicable solutions with a reasonable expectation of success one of which is that dopant concentrations of the layer of the semiconductor material (112a and 112b) forming the first terminal (112a) and the layer of the semiconductor material (112a and 112b) forming the second terminal (112b) are different , as recited in claim 17. Please see, MPEP 2143(E), above. Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable based on Chen in view of Curatola and further in view of US 2023/0044911 A1 (Li). Regarding claim 4, Applicant may argue that Chen in view of Curatola does not explicitly disclose, wherein forming the layer of the semiconductor material over the barrier layer includes forming the layer of the semiconductor material by an epitaxial growth process. However, in analogous art, Li discloses that it was well-known to one of ordinary skill in the art before the effective filing date of the claimed invention that epitaxy improves semiconductor crystal quality and electrical performance ([0150]). Therefore, it would have been obvious to one or ordinary skill in the art before the effective filing date of the claimed invention having the teachings of Chen, Curatola, and Li before him/her that forming the layer of the semiconductor material (112a and 112b) of Chen in view of Curatola over the barrier layer (110) thereof includes forming the layer of the semiconductor material (112a and 112b) by an epitaxial growth process , as taught by Li, to improve the crystal quality and/or electrical performance of semiconductor material (112a and 112b), as also taught by Li . Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable based on Chen in view of Curatola and further in view of US 2025/0294815 A1 (Xie). Regarding claim 7, Applicant may argue that Chen in view of Curatola does not explicitly disclose, wherein forming the first semiconductor device and forming the second semiconductor device includes etching at least one of the first or second terminals to set at least one of the first and second thicknesses. However, in analogous art, Xie discloses that it was well-known to one of ordinary skill in the art before the effective filing date of the claimed invention that etching may be predicably used to trim a semiconductor component to a desired thickness ([0055]). Therefore, it would have been obvious to one or ordinary skill in the art before the effective filing date of the claimed invention having the teachings of Chen, Curatola, and Xie before him/her that forming the first semiconductor device (Ra) and forming the second semiconductor device (Rb) may predicably include etching at least one of the first (112a) or second (112b) terminals to set at least one of the first and second thicknesses (annotated FIG. 9, above), as taught by Xie, with no change in the function of first (112a) or second (112b) terminals because they would still function as terminals. Please see, MPEP 2143(A)—Combining Prior Art Elements According To Known Methods To Yield Predicably Results . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 11-14, and 18-23 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to Applicant's disclosure. US 2019/0131442 A1 (Lin)—Discloses a method (FIG 2.) that includes forming a substrate (12), a second conductive layer (14), a first conductive layer (16), a first channel (17H) of a first semiconductor structure, a second channel (17L) of a second semiconductor structure, and a barrier structure (24). Also discloses a gate (GH) of the first semiconductor structure and a gate (GL) of the second semiconductor structure. US 2018/0197856 A1 (Chou)—Discloses a method (FIG. 1) that includes forming a substrate (102), channel layer (104) that includes GaN, a barrier layer (106), a dielectric layer (112), metal contacts (132, 134, 136, and 138). Any inquiry concerning this communication or earlier communications from the Examiner should be directed to Erik A. Anderson whose telephone number is (703) 756-1217. The Examiner can normally be reached Monday-Friday 8:30 a.m.-4:30 p.m. (Pacific Time Zone). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, Applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, William B. Partridge , can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is (571)273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at (866) 217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call (800) 786-9199 (IN USA OR CANADA) or (571) 272-1000. /ERIK A. ANDERSON/Examiner, Art Unit 2812 /William B Partridge/Supervisory Patent Examiner, Art Unit 2812 Application/Control Number: 18/610,227 Page 2 Art Unit: 2812 Application/Control Number: 18/610,227 Page 4 Art Unit: 2812 Application/Control Number: 18/610,227 Page 5 Art Unit: 2812 Application/Control Number: 18/610,227 Page 7 Art Unit: 2812 Application/Control Number: 18/610,227 Page 8 Art Unit: 2812 Application/Control Number: 18/610,227 Page 10 Art Unit: 2812 Application/Control Number: 18/610,227 Page 11 Art Unit: 2812 Application/Control Number: 18/610,227 Page 12 Art Unit: 2812
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