DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The objection to the drawings has been withdrawn in light of Applicant’s amendment to claim 6.
Specification
The new title presented is accepted by the examiner, and the objection to the title has been withdrawn.
Response to Arguments
Applicant’s arguments filed August 26, 2026 regarding claim 1, see pages 10-12 of Applicant’s arguments, have been fully considered. A new ground of rejection is presented below in light of Applicant’s amendments.
Regarding Applicant’s arguments with respect to claim 6, Applicant asserts that since the drawings might not be to scale, they do not show the claim limitations as they are amended. However, as is shown in the rejection below, there are teachings in Kadoguchi that suggest more of an overlap of the two semiconductor chips than with the second semiconductor chip and the diode. Specifically, the overlap stems from a shift in the first conductive plate to give more room for a connection to a lower chip, which is naturally going to be a small shift. This gives a motivation in the art to overlap with the second semiconductor chip with the diode to only a small degree, and thus the rejection of the newly amended claim does not only rely on the figures.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 and 3-19 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, the claim recites the limitation “an entirety of the third conductive plate is covered with the sealing resin.” As best understood by Applicant’s specification, this plate is a functional part of the device, and any conductive plate such as this would have some sort of electrical connection in order to function. However, if the entirety of the plate was covered with resin, it would be electrically isolated and thus rendered useless for its function. There is somewhat of an understanding as to the general intent of this limitation, particularly as pointed out in Applicant’s specification paragraph 0108 that the top of the conductive plate is covered with resin, and that the electrical connection with the chips need not be. However, it is unclear exactly what the scope of coverage of the resin needs to be to meet this limitation, as best understood in light of the specification. Thus, the claim is rendered indefinite. For examination, this was interpreted as requiring all surfaces not needed for electrical connection to be covered with the resin.
Claims 3-19 are rejected due to their dependence on claim 1.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
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Claims 1, 3, 9-10, 13-14, 16-17, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Kadoguchi et al. (US 20140197525 A1), hereinafter referred to as "Kadoguchi", in view of Yamamoto (US 20230091854 A1), hereinafter referred to as "Yamamoto".
In regards to claim 1, Kadoguchi discloses a semiconductor device comprising: a first semiconductor chip including a first obverse surface and a first reverse surface spaced apart from each other in a thickness direction (20 in Kadoguchi figure 1); a second semiconductor chip including a second obverse surface and a second reverse surface spaced apart from each other in the thickness direction (21 in figure 1), and electrically connected in series to the first semiconductor chip (paragraph 066; they are connected in series through first conductive plate 11); and a conductive member including a first conductive plate electrically connected to the first semiconductor chip and the second semiconductor chip (conductive member 10, 11, and 12 includes first conductive plate 11 in figure 1 which connects 20 and 21), a second conductive plate spaced apart from the first conductive plate (10, spaced apart from 11 in figure 1) and a third conductive plate spaced apart from the first conductive plate (12, spaced apart from 11 in figure 1); a sealing resin covering a portion of the conductive member, the first semiconductor chip, and the second semiconductor chip (90 in figure 1, end of paragraph 0045) wherein at least one of the first semiconductor chip and the second semiconductor chip is an IGBT (20 can be an IGBT, paragraph 0059) including a collector electrode, an emitter electrode, and a gate electrode (It has a gate and emitter on the top surface, see paragraphs 0060 and 0115; As the two devices 20 and 21 are connected in series through the conductor 11, there must naturally be a collector on the bottom), the second conductive plate and the third conductive plate are spaced apart from each other (see figure 1), the first semiconductor chip is provided between the first conductive plate and the second conductive plate in the thickness direction (20 is between 11 and 10), and the second semiconductor chip is provided between the first conductive plate and the third conductive plate in the thickness direction (21 is between 11 and 12) the first conductive plate is provided between the first semiconductor chip and the second semiconductor chip in the thickness direction (11 is between 20 and 21 in figure 1), and the second conductive plate includes a portion exposed from the sealing resin (lower surface of 10 in figure 1, see Kadoguchi paragraphs 0104 and 0120).
Kadoguchi discloses that the third conductive plate is covered with the sealing resin (see 11 in figure 1), but does not disclose that the entirety of the third conductive plate is covered with the sealing resin, as the top surface is not covered (Kadoguchi paragraph 0117).
Yamamoto teaches a stacked semiconductor device with a third conductive plate that has the top also covered in a sealing resin (sealing resin m in Yamamoto figure 3 also covers top surface of lead frame q2). It is known that sealing resins such as this can reduce moisture reaching the conductive elements.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the resin fully cover the top conductive plate like in Yamamoto in order to reduce moisture reaching the third conductive plate.
In regards to claim 3, Kadoguchi in view of Yamamoto discloses all of the limitations of claim 1. Kadoguchi further discloses that the first semiconductor chip and the second semiconductor chip overlap with each other as viewed in the thickness direction (21 and 20 overlap in figure 1).
In regards to claim 9, Kadoguchi in view of Yamamoto discloses all of the limitations of claim 1. Kadoguchi further discloses that the second semiconductor chip includes a second emitter electrode, a second collector electrode, and a second gate electrode (21 can be an IGBT see paragraph 0063. It has a gate and emitter on the top surface, see paragraphs 0060 and 0115 and an IGBT is known in the art to also have a collector electrode).
In regards to claim 10, Kadoguchi in view of Yamamoto discloses all of the limitations of claim 9. Kadoguchi further discloses that the second emitter electrode and the second gate electrode are provided on the second obverse surface of the second semiconductor chip (gate and emitter are on the top surface of 21, see paragraphs 0060 and 0115), and the second collector electrode is provided on the second reverse surface (As the two devices 20 and 21 are connected in series through the conductor 11, the collector naturally must be on the bottom), the second collector electrode is bonded to the first conductive plate (solder 30 below 21 in figure 1), and the second emitter electrode is bonded to the third conductive plate (solder 30 and spacer 40 above 21 in figure 1).
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In regards to claim 13, Kadoguchi in view of Yamamoto discloses all of the limitations of claim 1. Kadoguchi further discloses a plurality of power terminals each electrically connected to at least one of the first semiconductor chip and the second semiconductor chip (80, 81, and 82 in figure 1 and 2); and a signal terminal for inputting a gate signal to an IGBT that is one of the first semiconductor chip and the second semiconductor chip (60/61 in figure 1 and 2).
In regards to claim 14, Kadoguchi in view of Yamamoto discloses all of the limitations of claim 13. Kadoguchi further discloses the first semiconductor chip and the second semiconductor chip form a bridge in which the first semiconductor chip serving as an upper arm is connected to the second semiconductor chip serving as a lower arm (paragraph 0065), and the plurality of power terminals include a first input terminal electrically connected to an end of the bridge (82 in figure 2), a second input terminal electrically connected to another end of the bridge (80 in figure 2), and an output terminal electrically connected to a connecting point between the first semiconductor chip and the second semiconductor chip (81 in figure 1 and 2).
In regards to claim 16, Kadoguchi in view of Yamamoto discloses all of the limitations of claim 14. Kadoguchi further discloses that the signal terminal is arranged on a side opposite from the first input terminal and the second input terminal (61 is opposite 80/82 in figure 2) with the first semiconductor chip and the second semiconductor chip therebetween (20 and 21 are between 61 and 80/82).
In regards to claim 17, Kadoguchi in view of Yamamoto discloses all of the limitations of claim 13. Kadoguchi further discloses that the sealing resin covers a portion of each of the plurality of power terminals and a portion of the signal terminal, (90 in figure 1, end of paragraph 0045), the sealing resin includes a resin obverse surface and a resin reverse surface spaced apart from each other in the thickness direction (top and bottom of 90), and a plurality of resin side surfaces each connected to the resin obverse surface and the resin reverse surface (sides of 90), and the plurality of resin side surfaces include a first resin side surface from which the signal terminal is exposed (left side in figure 1).
In regards to claim 19, Kadoguchi in view of Yamamoto discloses all of the limitations of claim 17. Kadoguchi further discloses that at least one of the plurality of power terminals is exposed from a resin side surface which is one of the plurality of resin side surfaces different from the first resin side surface (power terminals 80/81/82 are exposed on right side of resin, while signal terminal is exposed on the left side, see figures 1 and 2).
Claims 4-8, 11, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Kadoguchi in view of Yamamoto, and further in view of Harada (JP 5966921 B2), hereinafter referred to as “Harada”.
In regards to claim 4, Kadoguchi in view of Yamamoto discloses all of the limitations of claim 1. Kadoguchi in view of Yamamoto does not disclose that the semiconductor chip is a reverse-conducting IGBT.
Harada teaches the first semiconductor chip is a reverse-conducting IGBT including an IGBT region and a diode region (2b in Harada figure 3 is an RC-IGBT, see machine translation page 3, paragraph 8), and includes a first collector electrode (4 in Harada figure 3), a first emitter electrode (3 in Harada figure 3), and a first gate electrode (5 in Harada figure 3). Harada teaches that both the IGBT and the reverse parallel diode are needed for the voltage converter circuit, and that the RC-IGBT integrates both of these into one chip.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the separate semiconductor and diode components from Kadoguchi in view of Yamamoto into one reverse-conducting IGBT of Harada in order to reduce the number of components and decrease the footprint of the device.
In regards to claim 5, Kadoguchi in view of Yamamoto discloses all of the limitations of claim 1. Kadoguchi further discloses a first diode chip connected to the first semiconductor chip (25 in Kadoguchi figure 1), wherein the first semiconductor chip includes a first collector electrode, a first emitter electrode, and a first gate electrode, (it has a gate and emitter on the top surface, see paragraphs 0060 and 0115; An IGBT is known in the art to also have a collector electrode, and as the device 20 is electrically connected to the conductor 10 through solder 30, and the emitter and gate are both on the top, the collector naturally must be on the bottom)
Kadoguchi does not explicitly disclose where the anode and cathode of the diode are connected, but Kadoguchi does say that “Conventionally, a power module to perform voltage conversion or power conversion of direct voltage is known” (paragraph 0002).
Harada teaches that the first diode chip includes an anode electrode connected to the first emitter electrode (Harada figure 4, anode of 92b is connected to emitter electrode 3), and a cathode electrode connected to the first collector electrode (Harada figure 4, cathode of 92b is connected to collector electrode 4). Harada also teaches that the voltage converter circuit has switching elements connected in reverse parallel to a diode that bypass a reverse current.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the anode and cathode of the diode be connected as in Harada in order to have a functioning power conversion circuit, as is known in the art.
Regarding claim 6, Kadoguchi in view of Yamamoto and Harada discloses all of the limitations of claim 5. Kadoguchi further discloses that the second semiconductor chip overlaps with the first semiconductor chip and the first diode chip as viewed in the thickness direction (see 21, 20, and 25 in Kadoguchi figure 1 and 2). The vast majority of the overlap is with the first semiconductor chip, rather than the first diode chip, which shows that an area in which the second semiconductor chip overlaps with the first diode chip is smaller than an area in which the second semiconductor chip overlaps with the first semiconductor chip as viewed in the thickness direction. Furthermore, the cause of this overlap is from the shifting of the first conductive plate (11 in figure 1) such that it does not overlap a part of the first semiconductor chip (see area A in Kadoguchi figure 3 and Kadoguchi paragraphs 0053 and 0069). Therefore, the teachings suggest that the offset would only be enough such that the first semiconductor chip can be readily accessed, which implies a relatively small shift, and thus a much smaller overlap with the diode, compared to the semiconductor chip.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the area of overlap with the diode would be smaller than the area of overlap with the semiconductor chip according to the teachings of Kadoguchi.
In regards to claim 7, Kadoguchi in view of Yamamoto and Harada discloses all of the limitations of claim 4. Kadoguchi further discloses the first emitter electrode and the first gate electrode are provided on the first obverse surface of the first semiconductor chip (paragraph 0065 and 115), and the first collector electrode is provided on the first reverse surface (As the device 20 is electrically connected to the conductor 10 through solder 30, and the emitter and gate are both on the top, the collector naturally must be on the bottom), the first collector electrode is bonded to the second conductive plate (using solder 30 below 20 in Kadoguchi figure 1), and the first emitter electrode is bonded to the first conductive plate (using solder 30 and spacer 40 above 20 in Kadoguchi figure 1).
In regards to claim 8, Kadoguchi in view of Yamamoto and Harada discloses all of the limitations of claim 7. Kadoguchi further discloses that the first conductive plate does not overlap with the first gate electrode as viewed in the thickness direction (Kadoguchi figure 1 and 3; paragraph 0069).
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In regards to claim 11, Kadoguchi in view of Yamamoto discloses all of the limitations of claim 10. Kadoguchi in view of Yamamoto does not disclose that the third conductive plate does not overlap with the second gate electrode as viewed in the thickness direction.
Harada teaches that the third conductive plate does not overlap with the second gate electrode as viewed in the thickness direction (conductive plate 13b does not overlap with either of the gate electrodes 5 in Harada figure 5). Harada also teaches that these don’t overlap so that it is easy to attach the bond wires to the gate electrode after the semiconductor chips and conductive plates are laminated and joined (Harada machine translation page 5, paragraph 3).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the third conductive plate not overlap the gate electrode as in Harada in order to more easily attach the bond wires after joining the semiconductor chips and conductive plates.
In regards to claim 15, Kadoguchi in view of Yamamoto discloses all of the limitations of claim 14. Kadoguchi in view of Yamamoto does not disclose that the first input terminal and the second input terminal are adjacent to each other in a first direction perpendicular to the thickness direction.
Harada teaches the first input terminal and the second input terminal are adjacent to each other in a first direction perpendicular to the thickness direction (Harada figure 5; input terminals 13b and 13c are adjacent to each other in a direction perpendicular to the top-down thickness direction).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to adjust the wiring to that of Harada’s adjacent terminals for any particular application, depending on where the signals might need to go or come from, in order to simplify connecting the module to the board.
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Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Kadoguchi in view of Yamamoto and further in view of Kawashima (US 20200365491 A1), hereinafter referred to as "Kawashima".
In regards to claim 12, Kadoguchi in view of Yamamoto discloses all of the limitations of claim 1. Kadoguchi in view of Yamamoto does not disclose a dimension of the second conductive plate in the thickness direction is larger than a dimension of each of the first conductive plate and the third conductive plate.
Kawashima teaches a dimension of the second conductive plate in the thickness direction is larger than a dimension of each of the first conductive plate and the third conductive plate (thickness T16 of the conductive plate 16 is greater than the thickness of the other two plates, T20 and T18 in Kawashima figure 15; see paragraphs 0088 and 0090). Kawashima also taches that this enhances the heat dissipation for the connected electrode due to the larger thermal capacity of the plate, thus improving the heat dissipating performance (paragraph 0090).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the larger dimension in the thickness direction of Kawashima in order to improve the heat dissipating performance.
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Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Kadoguchi in view of Yamamoto, and further in view of Iwabuchi et al. (US 20170110395 A1).
In regards to claim 18, Kadoguchi in view of Yamamoto discloses all of the limitations of claim 17. Kadoguchi in view of Yamamoto does not disclose power terminals exposed from the same side as the signal terminal.
Iwabuchi teaches the plurality of power terminals are exposed from the first resin side surface (power terminals 20 and 21 are exposed on the same first resin side as signal terminals 30/32/34 in Iwabuchi figure 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to adjust the wiring for any particular application, depending on where the signals might need to go or come from in order to simplify connecting the module to the board.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL K ELLIOTT whose telephone number is (571)357-4606. The examiner can normally be reached Mon-Fri 8:00 -5:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached at 408-918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANIEL KURT ELLIOTT/ Examiner, Art Unit 2899
/Brent A. Fairbanks/ Supervisory Patent Examiner, Art Unit 2899
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