DETAILED ACTION
This Office Action is in response to the application filed on 20 March 2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 7, 8, 10-17, 19, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takeda et al. (US 2009/0278200 A1; hereinafter Takeda), in view of Naito (US 2016/0197143 A1; hereinafter Naito).
In regards to claim 1, Takeda teaches, e.g. in fig. 5, a semiconductor device, comprising:
a vertical transistor (fig. 5; [0034]); and
a semiconductor layer (10/12/16/18/19/21) [0038-0042], forming a portion of the vertical transistor, wherein the semiconductor layer includes:
a first doped layer (12A) [0023];
a second doped layer (18) [0023], formed on the first doped layer; and
a third doped layer (19/21) [0038], formed on the second doped layer, wherein
an impurity concentration of the first conductivity type (fig. 5: n-type) of the second doped layer is less than the impurity concentration of the first conductivity type of the third doped layer (fig. 5: e.g. (18) has (N) doping whereas (12) has (N+) doping).
Takeda appears to be silent as to, but does not preclude, the limitations wherein an impurity concentration of a first conductivity type of the first doped layer is greater than an impurity concentration of the first conductivity type of the third doped layer ([0141]: (32) has a higher concentration of P, e.g. first conductivity type, than (4)). Naito teaches, e.g. in figs. 9-10, the limitations wherein an impurity concentration of a first conductivity type of the first doped layer is greater than an impurity concentration of the first conductivity type of the third doped layer ([0141]: (32) has a higher concentration of P, e.g. first conductivity type, than (4)). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Takeda with the aforementioned limitations taught by Naito to have a semiconductor design that reduces switching losses (Naito [0040]).
In regards to claim 2, the combination of Takeda and Naito teaches the limitations discussed above in addressing claim 1. Takeda further teaches, e.g. in fig. 5, the limitations further comprising:
a gate trench (24) [0036], formed in the semiconductor layer; and
a gate electrode (27) [0037], disposed in the gate trench, wherein
the gate trench extends through the third doped layer and reaches the second doped layer (fig. 5: (24) extends through (19/21) and reaches (18)).
In regards to claim 3, the combination of Takeda and Naito teaches the limitations discussed above in addressing claim 2. Takeda further teaches the limitations wherein the gate trench has a bottom wall, and at least a portion of the bottom wall is formed in the second doped layer (fig. 5: e.g. the bottom surface of (24) is formed in (18)).
In regards to claim 4, the combination of Takeda and Naito teaches the limitations discussed above in addressing claim 2. Takeda further teaches, e.g. in fig. 5, the limitations further comprising:
an insulating layer (25) [0036], formed on the semiconductor layer (12/16/18/19/21) [0038-0042]; and
a gate wiring (evidenced by (27)) formed on the insulating layer, wherein
the gate electrode is electrically connected to the gate wiring (fig. 5).
In regards to claim 7, the combination of Takeda and Naito teaches the limitations discussed above in addressing claim 2. Naito further teaches the limitations wherein the gate trench has a depth between about 2 μm and about 10 μm (figs. 9-10) [0145]. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Takeda with the aforementioned limitations taught by Naito to have a semiconductor design that reduces switching losses (Naito [0040]).
In regards to claim 8, the combination of Takeda and Naito teaches the limitations discussed above in addressing claim 2. Takeda further teaches the limitations wherein the gate trench (24) [0036] is one of a plurality of gate trenches arranged in stripes in a plan view (fig. 5: elements (24) are arranged in stripe patterns).
In regards to claim 10, the combination of Takeda and Naito teaches the limitations discussed above in addressing claim 1. Naito further teaches, e.g. in figs. 9-10, the limitations wherein the first doped layer is thinner than the third doped layer ([0117, ][0143-0145]), and the second doped layer is thicker than the third doped layer ([0117, ][0143-0145]). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Takeda with the aforementioned limitations taught by Naito to have a semiconductor design that reduces switching losses (Naito [0040]).
In regards to claim 11, the combination of Takeda and Naito teaches the limitations discussed above in addressing claim 1. The combination of Takeda and Naito appears to be silent as to the limitation wherein a resistivity of the first doped layer is less than a resistivity of the third doped layer, and a resistivity of the second doped layer is greater than the resistivity of the third doped layer; however, where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. See MPEP §2144.05 II A; see also In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). In the case at hand, Naito teaches the general conditions of claim 11. Specifically, Naito teaches the limitations of optimizing the resistance of different layers to have the desired effect of reducing switching losses ([0040], [0117-0119]). Therefore, one having ordinary skill in the at the time the application at hand would find it obvious to discover the optimum or workable ranges of a resistivity of the first doped layer is less than a resistivity of the third doped layer, and a resistivity of the second doped layer is greater than the resistivity of the third doped layer using only routine skill in the art.
In regards to claim 12, the combination of Takeda and Naito teaches the limitations discussed above in addressing claim 1. The combination of Takeda and Naito appears to be silent as to the limitation wherein the impurity concentration of the first conductivity type of the first doped layer is between about 1 × 1016 cm-3 and about 1 × 1019 cm-3, the impurity concentration of the first conductivity type of the second doped layer is between about 1 × 1013 cm-3 and about 1 × 1016 cm-3, and the impurity concentration of the first conductivity type of the third doped layer is between about 2 × 1015 cm-3 and about 1 × 1018 cm-3; however, where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. See MPEP §2144.05 II A; see also In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). In the case at hand, Naito teaches the general conditions of claim 11. Specifically, Naito teaches, e.g. in figs. 9-10, the limitations of optimizing the impurity concentration of different semiconductor layers to have the desired effect of a semiconductor device design that reduces switching losses ([0040], [0145]). Therefore, one having ordinary skill in the at the time the application at hand would find it obvious to discover the optimum or workable ranges wherein the impurity concentration of the first conductivity type of the first doped layer is between about 1 × 1016 cm-3 and about 1 × 1019 cm-3, the impurity concentration of the first conductivity type of the second doped layer is between about 1 × 1013 cm-3 and about 1 × 1016 cm-3, and the impurity concentration of the first conductivity type of the third doped layer is between about 2 × 1015 cm-3 and about 1 × 1018 cm-3 using only routine skill in the art.
In regards to claim 13, the combination of Takeda and Naito teaches the limitations discussed above in addressing claim 1. The combination of Takeda and Naito appears to be silent as to the limitation wherein a thickness of the first doped layer is between about 0.5 μm and about 10 μm, a thickness of the second doped layer is between about 1 μm and about 30 μm, and a thickness of the third doped layer is between about 1 μm and about 15 μm; however, where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. See MPEP §2144.05 II A; see also In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). In the case at hand, Naito teaches the general conditions of claim 11. Specifically, Naito teaches the limitations of optimizing the thickness of doped layers to achieve the desired effect of having a semiconductor device design that reduces switching losses (figs. 9-10) ([0040], [0145]). Therefore, one having ordinary skill in the at the time the application at hand would find it obvious to discover the optimum or workable ranges wherein a thickness of the first doped layer is between about 0.5 μm and about 10 μm, a thickness of the second doped layer is between about 1 μm and about 30 μm, and a thickness of the third doped layer is between about 1 μm and about 15 μm using only routine skill in the art.
In regards to claim 14, the combination of Takeda and Naito teaches the limitations discussed above in addressing claim 1. The combination of Takeda and Naito appears to be silent as to the limitation wherein a resistivity of the first doped layer is between about 0.01 Ω·cm and about 0.5 Ω·cm, a resistivity of the second doped layer is between about 0.1 Ω·cm and about 10 Ω·cm, a resistivity of the third doped layer is between about 0.05 Ω·cm and about 1 Ω·cm; however, where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. See MPEP §2144.05 II A; see also In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). In the case at hand, Naito teaches the general conditions of claim 11. Specifically, Naito teaches the limitations of optimizing the resistance of different layers to have the desired effect of reducing switching losses ([0040], [0117-0119]). Therefore, one having ordinary skill in the at the time the application at hand would find it obvious to discover the optimum or workable ranges wherein a resistivity of the first doped layer is between about 0.01 Ω·cm and about 0.5 Ω·cm, a resistivity of the second doped layer is between about 0.1 Ω·cm and about 10 Ω·cm, a resistivity of the third doped layer is between about 0.05 Ω·cm and about 1 Ω·cm using only routine skill in the art.
In regards to claim 15, the combination of Takeda and Naito teaches the limitations discussed above in addressing claim 1. Takeda further teaches, e.g. in fig. 5, the limitations wherein an ion implantation region (19) of a second conductivity type (P) is formed in the third doped layer (19/21) [0035].
In regards to claim 16, the combination of Takeda and Naito teaches the limitations discussed above in addressing claim 1. Takeda further teaches, e.g. in fig. 5, the limitations wherein a body region (19) of a second conductivity type (P) and a source region (21) of the first conductivity type (N) of the vertical transistor are formed in the third doped layer (19/21) [0035-0038].
In regards to claim 17, the combination of Takeda and Naito teaches the limitations discussed above in addressing claim 1. Takeda further teaches, e.g. in fig. 5, the limitations wherein the semiconductor layer (10/12/16/18/19/21) [0038-0042] further includes a semiconductor substrate (10), and the first doped layer (12A) [0023] is formed on the semiconductor substrate.
In regards to claim 19, the combination of Takeda and Naito teaches the limitations discussed above in addressing claim 1. Takeda further teaches the limitations wherein the vertical transistor is a trench-gate-type MOSFET [0034].
In regards to claim 20, the combination of Takeda and Naito teaches the limitations discussed above in addressing claim 1. Takeda further teaches the limitations wherein when the vertical transistor is turned on, a current flows through the first doped layer, the second doped layer and the third doped layer [0062].
Claim(s) 5, 6, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Takeda and Naito as applied to claim 2 above, and further in view of Zundel et al. (US 2015/0115353 A1; hereinafter Zundel).
In regards to claim 5, the combination of Takeda and Naito teaches the limitations discussed above in addressing claim 2. The combination of Takeda and Naito appears to be silent as to, but does not preclude, the limitations further comprising a field plate electrode disposed within the gate trench. Zundel teaches the limitations further comprising a field plate electrode (12a) [0058-0060] disposed within the gate trench (fig. 2). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by the combination of Takeda and Naito with the aforementioned limitations taught by Zundel to have a high power device (Zundel [0005]).
In regards to claim 6, the combination of Takeda, Naito, and Zundel teaches the limitations discussed above in addressing claim 5. Zundel further teaches, e.g. in fig. 2, the limitations further comprising:
an insulating layer (30) [0054], formed on the semiconductor layer (1) [0060]; and
a source wiring (10) [0050], formed on the insulating layer, wherein
the field plate electrode (12a) [0058-0060] is electrically connected to the source wiring (fig. 2: (12a/12b) is connected, similar to a gate, to source wiring (10) by source regions (2/3)).
It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by the combination of Takeda and Naito with the aforementioned limitations taught by Zundel to have a high power device (Zundel [0005]).
In regards to claim 18, the combination of Takeda and Naito teaches the limitations discussed above in addressing claim 2. The combination of Takeda and Naito appears to be silent as to, but does not preclude, the limitations wherein the semiconductor layer has a first surface and a second surface opposite to the first surface, the gate trench is formed on the first surface of the semiconductor layer, and the semiconductor device further includes a drain electrode formed on the second surface of the semiconductor layer. Zundel teaches, e.g. in fig. 2, the limitations wherein
the semiconductor layer (1/2/4/5) [0053] has a first surface (top) and a second surface (bottom) opposite to the first surface,
the gate trench (fig. 2: evidenced by (12)) is formed on the first surface of the semiconductor layer, and
the semiconductor device further includes a drain electrode (11) [0053] formed on the second surface of the semiconductor layer.
It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by the combination of Takeda and Naito with the aforementioned limitations taught by Zundel to have a high power device (Zundel [0005]).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Takeda and Naito as applied to claim 2 above, and further in view of Nagase et al. (US 2020/0321464 A1; hereinafter Nagase).
In regards to claim 9, the combination of Takeda and Naito teaches the limitations discussed above in addressing claim 2. The combination of Takeda and Naito appears to be silent as to, but does not preclude, the limitations wherein the gate trench is formed in a mesh shape in a plan view. Nagase teaches the limitations wherein the gate trench is formed in a mesh shape in a plan view [0097]. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by the combination of Takeda and Naito with the aforementioned limitations taught by Nagase to have a semiconductor device with high withstand voltage and low on-resistance (Nagase [0011]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CALVIN Y CHOI whose telephone number is (571)270-7882. The examiner can normally be reached M-F 8-4 (Pacific Time).
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CALVIN CHOI
Patent Examiner
Art Unit 2812
/CALVIN Y CHOI/Primary Patent Examiner, Art Unit 2812
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