Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 9, 10 and 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Berkhout (20190007011).
Regarding claims 1 and 10, Berkhout (Figs. 2 and 6A) discloses an audio amplifier comprising: a sigma delta modulator (208) operable as a digital processing circuit configured to generate an N-bit digital audio signal, see para. [0057], N being an integer larger than 1; a first modulation circuit (210) configured to truncate the digital audio signal and perform a first modulation processing based on pulse width modulation or pulse density modulation to generate a single-bit waveform modulated signal; and an amplifier circuit comprising: a single-bit digital-to-analog conversion circuit (212a) configured to receive and convert the single-bit waveform modulated signal to generate an input analog signal; block (214a) operable as a second modulation circuit configured to receive the input analog signal and an output modulated signal, perform subtraction thereon to generate a subtracted result and perform a second modulation processing on the subtracted result based on pulse width or pulse density modulation to generate a control signal; and a driving circuit (217a) configured to generate the output modulation signal according to the control signal and transmit the output modulation signal to the second modulation circuit through a closed-loop feedback path via feedback resistor (222a).
Regarding claims 9 and 18, wherein the driving circuit comprises: a P-type transistor electrically coupled between a supply power (Vp) and a connection terminal; and a N-type transistor electrically coupled between the connection terminal and a ground voltage; wherein the P-type transistor and the N-type transistor are controlled by the control signal to generate the output modulated signal at the connection terminal.
Allowable Subject Matter
Claims 2-8 and 11-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 2 and 11, prior art(s) does not disclose the single-bit DAC circuit is a switch circuit configured to switch to output one of a first reference voltage and a second reference voltage as the input analog signal according to the single-bit waveform modulated signal.
Regarding claims 3-8 and 12-17, prior art(s) does not disclose the second modulation circuit comprises: a front-end integral filter circuit configured to receive the input analog signal and the output modulated signal, perform subtraction thereon to generate the subtracted result and perform low-pass filtering and integration on the subtracted result to generate a filtered signal; and a back-end modulation circuit configured to modulate the filtered signal to generate the control signal.
Conclusion
The prior arts made of record and not relied upon is considered pertinent to applicant's disclosure.
Sahandiesfanjani et al., Caduff and Melanson disclose at least two modulation circuits. However, they lack a single bit digital-to-analog conversion circuit claimed.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Khanh V. Nguyen whose telephone number is (571) 272-1767. The examiner can normally be reached from 8:30 AM – 5:00 PM EST.
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/KHANH V NGUYEN/ Primary Examiner, Art Unit 2843
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