DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 2 and 11-16 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Invention or Species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 7/8/2026.
Applicant's election with traverse of Invention I, Species 2 in the reply filed on 7/8/2026 is acknowledged. The traversal is on the ground(s) that no undue burden is present. This is not found persuasive because serious burden was established in the Restriction Requirement mailed 5/13/2026. The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3, and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US patent publication US 20150021660 A1 (Chen et al hereinafter Chen).
Regarding claim 1, Chen discloses a power semiconductor device (the device of FIG. 3, which includes elements similar to the device of FIG. 1 with their values increased by 200 ¶ [0040]), comprising: a substrate (FIG. 3, substrate 302 ¶ [0022]); an epitaxial layer (FIG. 3, buffer layer 306 and first channel portion 308a are formed over substrate 302 by an epitaxial process ¶ [0028]) over the substrate and having a top surface (FIG. 3, top surface of first channel portion 308a), wherein the top surface is a rough interface (not a relevant condition in the present consideration of the claim) or a capture interface doped with ions (FIG. 3, first channel portion 308a, including its upper surface, may be doped with p-type ions such as iron or magnesium ¶ [0028-0029]), the rough interface is used to disrupt an atomic structure of the top surface, thereby breaking down a two-dimensional electron gas (not a relevant condition in the present consideration of the claim), and the ions doped in the capture interface are used to trap the two-dimensional electron gas (the ions may be employed for that intended use due to the interface of channel portion 308a with back barrier layer 110a, which comprises AlGaN ¶ [0028, 0033]); a barrier layer (FIG. 3, first back barrier layer 110a is in contact with the top surface of first channel portion 308a ¶ [0028, 0040]) in contact with the top surface of the epitaxial layer; a channel layer (FIG. 3, third channel portion 308c is disposed over barrier 110a ¶ [0040]) disposed on the barrier layer; a source pin and a drain pin (FIG. 3, electrodes 316 set on the left and right sides of channel portion 308c serve as source and drain pins ¶ [0037]) respectively disposed on two sides of the channel layer; and a gate pin (FIG. 3, gate 318 is set over channel portion 308c ¶ [0038]) disposed over the channel layer.
Regarding claim 3, Chen discloses the limitations of claim 1 as detailed above and further discloses that the ions comprise at least one of fluorine, oxygen, nitrogen, iron, boron, magnesium, and silicon (the p-type dopant ions may be iron or magnesium ¶ [0028]).
Regarding claim 10, Chen discloses the limitations of claim 1 as detailed above and further discloses a buffer layer disposed between the substrate and the epitaxial layer (FIG. 3, nucleation layer 304 functions as a buffer between substrate 302 and buffer layer 306 ¶ [0022]).
Claims 1 and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US patent publication US 20130221366 A1 (Curatola et al hereinafter Curatola).
Regarding claim 1, Curatola discloses a power semiconductor device (the device of FIG. 9B, which is similar to the device of FIGS. 8A-C aside from a few adjustments ¶ [0041], and is further related to the devices of FIGS. 1-3 and 6 in the sense that it illustrates how paths of charge-carrier gases are adjusted based on desired outcomes ¶ [0037]; the embodiment of FIG. 3 is notably relevant to the consideration of the implementation of the structure of FIG. 9B), comprising: a substrate (FIG. 9B, the portion of lower semiconductor compound 100 which is below the bottom surface of first doped region 130 functions in the capacity of a substrate ¶ [0026]); an epitaxial layer (FIG. 9B, the portion of lower semiconductor compound 100 which is above the bottom surface of first doped region 130 was formed as part of an epitaxial stack formation ¶ [0040]) over the substrate and having a top surface (a top surface of counter doped region 104 ¶ [0040]), wherein the top surface is a rough interface (not a relevant condition in the present consideration of the claim) or a capture interface doped with ions (FIG. 9B, counter doped region 104 has a counter dopant implantation ¶ [0040]), the rough interface is used to disrupt an atomic structure of the top surface, thereby breaking down a two-dimensional electron gas (not a relevant condition in the present consideration of the claim), and the ions doped in the capture interface are used to trap the two-dimensional electron gas (FIG. 9B, lower two-dimensional charge carrier gas 150, which when applied to the device of FIG. 3 is an electron gas, is trapped by the counter dopants in counter doped region 104 ¶ [0034, 0040]); a barrier layer (FIG. 9B, portion of intermediary compound semiconductor 110 below the upper two-dimensional charge carrier gas 160 functions in the capacity of a barrier layer and contacts the top surface of lower semiconductor compound 100 and counter doped region 104 ¶ [0027]) in contact with the top surface of the epitaxial layer; a channel layer (FIG. 9B, upper two-dimensional charge carrier gas 160 is a channel layer disposed on intermediary compound semiconductor 110 ¶ [0027]) disposed on the barrier layer; a source pin and a drain pin (FIG. 9B, first and second doped regions 130 and 140 form source and drain pins ¶ [0026]) respectively disposed on two sides of the channel layer (FIG. 9B, first and second doped regions 130 and 140 are on left and right sides of upper two-dimensional charge carrier gas 160); and a gate pin (FIG. 9B, gate 170 ¶ [0028]) disposed over the channel layer.
Regarding claim 9, Curatola discloses the limitations of claim 1 as detailed above and further discloses that the channel layer is a P-typed channel layer (FIGS. 3 and 9B, upper two-dimensional hole gas 160 is a P-typed channel ¶ [0034]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over US patent publication US 20150021660 A1 (Chen et al hereinafter Chen) as applied to claim 1 above, and further in view of US 20150021661 A1 (Chen et al hereinafter Chen 2).
Chen discloses the limitations of claim 1 as detailed above but does not further disclose that a doping concentration of the capture interface is greater than 1×10^18 cm^-3.
However, Chen 2 discloses a semiconductor device (the device of FIG. 1) wherein an interface between an AlGaN layer (Chen 2 FIG. 1, SLS 108 may be AlGaN ¶ [0029]) and a GaN layer (Chen 2 FIG. 1, buffer layer 110 may be GaN ¶ [0030]) may have a doping concentration greater than 1×10^18 cm^-3 (both SLS layer 108 and buffer layer 110 may have doping concentrations greater than 1×10^18 cm^-3, and their interface correspondingly has a comparable doping concentration ¶ [0029-0030]). A person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to optimize the dopant concentration of the capture interface because dopant concentrations affect the electrical properties, as Chen discusses in ¶ [0028], where the dopants can diffuse into adjoining layers in high quantities, or fail to prevent electron injection from the substrate in low quantities, the dopant concentration therefore being a result-effective variable. Therefore, it would be obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to vary the dopant concentration of the capture interface through routine optimization, and the person would have a reasonable expectation of success when a doping concentration of the capture interface is greater than 1×10^18 cm^-3, as Chen 2 has demonstrated that doping concentrations of that level when applied to interfaces of similar materials in an analogous device are known configurations to persons of ordinary skill in the art, which may may favorably adjust the electrical properties of the device.
Claims 5-8 are rejected under 35 U.S.C. 103 as being unpatentable over Chen as applied to claim 1 above, and further in view of obvious modifications to the disclosure of Chen.
Regarding claim 5, Chen discloses the limitations of claim 1 and further discloses a layer (FIG. 3, second channel portion 308b is between back barrier 110a and third channel portion 308c ¶ [0040]) disposed between the barrier layer and the channel layer.
Chen did not explicitly state that the layer was unintentionally doped; regarding a dopant concentration, Chen suggests that a second channel portion may have a same or a different dopant concentration as a first channel portion (¶ [0034]). Chen further teaches that a first channel portion may be either doped to a specific concentration or be left undoped or unintentionally doped (¶ [0029]). A person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to optimize the dopant concentration of the layer because dopant concentrations affect the electrical properties, as Chen discusses in ¶ [0028], where the dopants can diffuse into adjoining layers in high quantities, or fail to prevent electron injection from the substrate in low quantities, the dopant concentration therefore being a result-effective variable. Therefore, it would be obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to vary the dopant concentration of the layer through routine optimization, and the person would have a reasonable expectation of success when having the layer set at an unintentionally doped level, both because Chen contemplates such levels of dopant concentration for channel portions (¶ [0029]) and because doing so may favorably adjust the electrical properties of the device.
Regarding claim 6, Chen discloses the limitations of claim 5 as detailed above and further discloses that a top surface (FIG. 3, a top surface of first back barrier layer 110a) of the barrier layer is a rough interface (not a relevant condition in the present consideration of the claim) or a capture interface doped with ions (at least due to the dopants included in first channel portion 308a, it naturally follows that the top surface of first back barrier layer 110a will include dopants, even if only at an unintentional level ¶ [0029]), the rough interface is used to disrupt an atomic structure of the top surface of the barrier layer, thereby breaking down the two-dimensional electron gas (not a relevant condition in the present consideration of the claim), and the ions doped in the capture interface are used to trap the two-dimensional electron gas (the ions may contribute to a result in line with that intended use due to the interface of back barrier layer 110a, which comprises AlGaN, and second channel portion 308b ¶ [0028, 0033]).
Regarding claim 7, Chen discloses the limitations of claim 1 and further discloses that the epitaxial layer comprises gallium nitride or gallium oxide (FIG. 3, epitaxial buffer layer 306 may include gallium nitride).
Chen did not explicitly state that the channel layer also comprises gallium nitride or gallium oxide, but Chen does describe a process for forming a channel structure (FIG. 4, method 400, ¶ [0046-0050]) where a first portion and a second portion of a channel are both formed from gallium nitride (FIG. 4, operations 408 and 412 ¶ [0046, 0050]); Chen also teaches that the operation can be performed multiple times to form multiple back barrier layers (¶ [0050]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to form the device of Chen FIG. 3 in view of the disclosed method 400 by having the channel layer also comprise gallium nitride, as Chen contemplates such a configuration when discussing the method, in order to form the channel of a suitable material to achieve desirable electrical properties.
Regarding claim 8, Chen discloses the limitations of claim 7 as detailed above and further discloses that the barrier layer comprises aluminum gallium nitride, indium gallium nitride, or aluminum gallium oxide (FIG. 3, back barrier layer 110a includes aluminum gallium nitride AlGaN ¶ [0033]).
Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US patent publications US 20250176231 A1, US 20250098195 A1, US 20230411507 A1, US 20230070031 A1, US 20210050216 A1, US 20170263700 A1, and US 20160126312 A1.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWARD RHETT CHEEK whose telephone number is (571)272-3461. The examiner can normally be reached Monday - Thursday 7:30am - 5pm, Every other Friday 8:30am - 5pm.
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/E.R.C./Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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