Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are presented for examination.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. The limitation “means for dynamically allocating…” is interpreted in light of applicant’s specification as a data storage device/system and/or component(s) [paragraph 40].
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-5, 7-9 and 20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US PG Pub. 2024/0069721 to Sankaranarayanan et al., (hereafter Sankaranarayanan).
As to claim 20, Sankaranarayanan teaches the invention as claimed including a data storage device comprising:
a plurality of memory dies [memory dies 820, 920, Figs. 3-9 and corresponding text];
a plurality of backend modules, wherein there are fewer backend modules than memory dies [front-end and back-end channels that can be ONFI channels/interfaces, paragraph 25; less front-end and back-end channel in combination mapping to number of memory dies, Figs. 3 and 5-9 and corresponding text]; and
means for dynamically allocating the plurality of backend modules to the plurality of memory dies to balance load among the plurality of backend modules [selectively coupling of front-end to back-end channels in communicating with memory dies by controller and/or switch matrix, paragraphs 14 and 26-27; Figs. 3 and 5-9 and corresponding text; such selective coupling distribute load among available channel resources that would otherwise be idle or unable to access, paragraph 13, lines 1-16].
As to claim 1, Sankaranarayanan teaches the invention as claimed including in a data storage device comprising a plurality of memory dies and a plurality of backend modules, wherein there are more memory dies than backend modules [memory dies 820, 920, Figs. 3 and 5-9 and corresponding text; front-end and back-end channels that can be ONFI channels/interfaces, paragraph 25; less front-end and back-end channel in combination mapping to number of memory dies, Figs. 3 and 5-9 and corresponding text], a method comprising:
creating a dynamic allocation between at least some of the plurality of backend modules and at least some of the plurality of memory dies based on a workload of memory operations; and
providing the workload of memory operations to the plurality of backend modules per the dynamic allocation;
wherein the dynamic allocation more-evenly distributes the workload of memory operations among the plurality of backend modules than when a fixed allocation is used that fixedly allocates a backend module to more than one memory die [selectively coupling of front-end to back-end channels in communicating with memory dies by controller and/or switch matrix, paragraphs 14 and 26-27; transmit and receive communications/commands, paragraph 9, lines 10-14; paragraph 11, lines 1-4; paragraph 23; such selective coupling distribute load among available channel resources that would otherwise be idle or unable to access, paragraph 13, lines 1-16].
As to claim 2, Sankaranarayanan teaches the invention as claimed including wherein the dynamic allocation is created between all of the plurality of backend modules and all of the plurality of memory dies [selectively coupling of front-end to back-end channels in communicating with memory dies by controller and/or switch matrix, paragraphs 14 and 26-27; Figs. 3 and 5-9 and corresponding text; transmit and receive communications/commands, paragraph 9, lines 10-14; paragraph 11, lines 1-4; paragraph 23].
As to claim 3, Sankaranarayanan teaches the invention as claimed including wherein at least one memory die of the plurality of memory dies is fixedly allocated to a respective at least one backend module of the plurality of backend modules [Fig. 1 and corresponding text], and wherein the dynamic allocation is for the memory dies that are not fixedly allocated [Figs. 2-3 and 5-9 and corresponding text].
As to claim 4, Sankaranarayanan teaches the invention as claimed including wherein the dynamic allocation is created using a dynamic map [selectively coupling of front-end to back-end channels in communicating with memory dies by controller and/or switch matrix, paragraphs 14 and 26-27; Figs. 3 and 5-9 and corresponding text].
As to claim 5, Sankaranarayanan teaches the invention as claimed including wherein the dynamic allocation is created using a fixed map [selectively coupling of front-end to back-end channels in communicating with memory dies by controller and/or switch matrix, paragraphs 14 and 26-27; each memory die having a respective, hence fixed, back-end channel, Fig. 4 and corresponding text].
As to claim 7, Sankaranarayanan teaches the invention as claimed including wherein the providing is performed by at least one selector in the data storage device [selectively coupling of front-end to back-end channels in communicating with memory dies by controller and/or switch matrix, paragraphs 14 and 26-27; Figs. 2-9 and corresponding text].
As to claim 8, Sankaranarayanan teaches the invention as claimed including wherein the plurality of memory dies comprise a plurality of flash memory dies, and wherein the plurality of backend modules comprise a plurality of flash interface modules (FIMs) [flash/NAND memory and memory dies, paragraph 19-20; ONFI communication interfaces, paragraph 25].
As to claim 9, Sankaranarayanan teaches the invention as claimed including wherein at least one of the plurality of memory dies comprises a three-dimensional memory die [paragraph 20, lines 1-14].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sankaranarayanan as applied to claim 1 above, and further in view of US Patent 11,199,996 to Seo.
Seo was cited in applicant’s IDS filed on 3/20/24.
As to claim 6, Sankaranarayanan does not specifically teach the dynamic allocation is created by at least one scheduler in the data storage device. However, Sankaranarayanan disclosed the selectively coupling of front-end to back-end channels in communicating with memory dies by a memory controller and/or switch matrix [paragraphs 14 and 26-27] transmit and receive communications/commands via the memory controller to the memory devices/dies [paragraph 9, lines 10-14; paragraph 11, lines 1-4; paragraph 23]. Furthermore, Seo teaches schedulers of a NAND controller having decision logic block for scheduling transmission of commands over a respective shared channel interface to banks of die in respective NAND device group [Fig. 1 and corresponding text; col. 5, line 49-col. 6, line 16]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have implement Seo’s memory controller implemented scheduler in Sankaranarayanan to more efficiently transmit and execute command issued to NAND devices as being considered by Seo [col. 1, line 21-col. 2, line 23].
Allowable Subject Matter
Claims 10-19 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
A plurality of memory dies and a plurality of flash interface modules (FIMs), wherein a number of FIMs in the plurality of FIMs is fewer than a number of memory dies in the plurality of memory dies [memory dies 820, 920, Figs. 3 and 5-9 and corresponding text; front-end and back-end channels that can be ONFI channels/interfaces, paragraph 25; less front-end and back-end channel in combination mapping to number of memory dies, Figs. 3 and 5-9 and corresponding text] was disclosed in US PG Pub. 2024/0069721. Schedulers having decision logic block for scheduling transmission of commands over a respective shared channel interface to banks of die in a respective NAND device group [Fig. 1 and corresponding text; col. 5, line 49-col. 6, line 16] was disclosed in US Patent 11,199,996. US Patent 11,199,996 was cited in applicant’s IDS filed on 3/20/24. The prior arts of record when taken individually or in combination do not expressly teach or render obvious the plurality of schedulers, wherein each scheduler is associated with a respective subset of FIMs and is configured to schedule a memory operation for a selected FIM in its respective subset of FIMs; and a plurality of selectors, wherein each selector is associated with a respective memory die of the plurality of memory dies, is further associated with respective a subset of FIMs, and is configured to select a FIM in the subset of FIMs for connection with the respective memory die as a whole as recited in independent claim 10.
Neither a reference uncovered that would have provided a basis of evidence for asserting a motivation, nor one of ordinary skilled in the art before the effective filing date of the claimed invention, knowing the teaching of the prior arts of record would have combined them to arrive at the present invention as recited in independent claim 10 as a whole.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to QING YUAN WU whose telephone number is (571)272-3776. The examiner can normally be reached M-F 9AM-6PM EST.
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/QING YUAN WU/Primary Examiner, Art Unit 2199
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