Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgment is made of the information disclosure statements filed on 02/24/2025 and 03/20/2024. U.S. patents and Foreign Patents have been considered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 12, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over US20080301609A1 (Perez) in view of US20100325592A1 (Ji).
In regards to claim 1 (Perez) shows:
A system for auto-generating arrangement applied to electronic equipment, the electronic equipment using the system for auto-generating arrangement to generate a virtual integrated circuit (IC) layout, and the system for auto-generating arrangement comprising; Perez [0034] teaches a system comprising a computer readable media and a computer for generating and placing test structures in test chips, and Perez [0044] teaches creating a control data set for one or more device types, generating a test structure layout in response to the control data set, and placing the test structure layout within a pad array layout to form the test chip.
a grouping module configured to receive an electronic file that comprises device structures of testing devices and divide the testing devices into different testing device groups according to classification conditions; Perez [0026] teaches a tool set that receives a text control file as an input, the control file containing predefined keywords, user specified geometries, and references to predefined parameterized cells that represent the device structures, and Perez [0027] teaches determining a classification of the test structures based on the predefined keywords, thereby dividing them into groups according to classification conditions.
Perez differs from the claimed invention in that it does not explicitly disclose an arranging module connected to the grouping module and configured to arrange the different testing device groups in a virtual area based on an arrangement rule to form the virtual IC layout.
Ji teaches an arranging module connected to the grouping module and configured to arrange the different testing device groups in a virtual area based on an arrangement rule to form the virtual IC layout; Ji [0037] teaches arranging the patterns in a portion of the semiconductor layout that is defined as a virtual pattern arrangement area, and Ji [0036] teaches providing a restriction condition that governs the arrangement of the patterns within that area, thereby arranging the groups in a virtual area based on an arrangement rule.
It would have been obvious to one of ordinary skill in the art to combine Perez and Ji to arrange the generated testing device groups within a defined virtual area of the layout, with a reasonable expectation of success as both references address automated arrangement of structures within a semiconductor layout.
In regards to claim 2 (Perez) shows the system of claim 1:
wherein the virtual area comprises test lines and the arranging module is configured to arrange the testing devices that are grouped in each of the test lines; Perez [0037] teaches placing test structure layouts along the left-hand and right-hand rows of the pad array layout, each row serving as a test line, and Perez [0041] teaches arranging a total number of the grouped test structure devices within each array.
In regards to claim 12 (Perez) shows the system of claim 1:
further comprising: a storage module comprising a design orthogonal table and a device parameter table; Perez [0040] teaches a control data set file having columns of sub-type, device-type, cell name, length, width, and orientation, serving as a device parameter table, and Perez [0045] teaches comparing the input file against a stored predefined set of keywords and parameter geometries of previously established parameterized cells, thereby providing the stored tables.
a generating module connected to the storage module and the grouping module and configured to generate a plurality of sets of parameter names based on the design orthogonal table and the device parameter table; Perez [0026] teaches producing an ordered data set of hierarchical names, keywords, layout orientation, and parameterized layout geometries based on the input, thereby generating the plurality of sets of parameter names from the tables.
draw device structures of the testing devices according to the plurality of sets of parameter names; Perez [0029] teaches processing test structure geometry values to generate the parameterized cell layouts, thereby drawing the device structures according to the sets of parameter names.
convert the device structures of the testing devices into the electronic file, and output the electronic file; Perez [0027] teaches generating code representative of the generated test structure arrays, and Perez [0033] teaches outputting that code as instructions for the test structure arrays stored on a computer readable media for layout data processing, thereby converting the device structures into the electronic file and outputting it.
In regards to claim 13 (Perez) shows the system of claim 12:
wherein the plurality of sets of parameter names comprise one or a combination of a device shape, a device spacing, and a device width of the testing device; Perez [0040] teaches parameter columns providing the length and width dimensions of the device, and Perez [0048] teaches placing the test structure layout by a given spacing in the x-coordinate and y-coordinate directions, thereby providing device shape, device spacing, and device width parameter names.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over US20080301609A1 (Perez) in view of US20100325592A1 (Ji) and US20040000744A1 (Grigg).
In regards to claim 3 (Perez modified by Ji) does not show: wherein the arranging module is configured to mark test line information and device information of each of the testing devices on each of the test lines;
Grigg teaches wherein the arranging module is configured to mark test line information and device information of each of the testing devices on each of the test lines; Grigg [0049] teaches methods of labeling, or marking, semiconductor devices with marking structures, and Grigg [0074] teaches a computer programmed to recognize the location, orientation, and type of each semiconductor device at each location, thereby marking test line and device information on each device.
It would have been obvious to one of ordinary skill in the art to further combine Perez and Ji with Grigg to mark test line and device information on the arranged testing devices, with a reasonable expectation of success as the references address identification and labeling of semiconductor devices.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over US20080301609A1 (Perez) in view of US20100325592A1 (Ji) and US5140402A (Murakata).
In regards to claim 4 (Perez modified by Ji) does not show: wherein the grouping module is configured to select the testing devices that are grouped using random numbers and the arranging module is configured to arrange the testing devices that are grouped using random numbers in the virtual area to form the virtual IC layout;
Murakata teaches wherein the grouping module is configured to select the testing devices that are grouped using random numbers and the arranging module is configured to arrange the testing devices that are grouped using random numbers in the virtual area to form the virtual IC layout; Murakata [Column 6 Lines 25 - 35] teaches deciding a satisfaction level having a probabilistic perturbation value by using random numbers, and Murakata [Column 5 Lines 55 - 65] teaches selecting, when a placement improvement process is executed, one of the values generated by random numbers, thereby selecting and arranging the grouped devices using random numbers.
It would have been obvious to one of ordinary skill in the art to further combine Perez and Ji with Murakata to select and arrange the grouped testing devices using random numbers, with a reasonable expectation of success as the references address automated placement of devices within a semiconductor layout.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over US20080301609A1 (Perez) in view of US20100325592A1 (Ji) and US20200038917A1 (McBride).
In regards to claim 5 (Perez) shows the system of claim 1:
wherein the classification conditions comprise device type conditions; Perez [0040] teaches a device-type column that defines device type conditions for the test structures.
Perez differs from the claimed invention in that it does not explicitly disclose and device height conditions.
McBride teaches and device height conditions; McBride [0023] teaches sorting a set of items having different dimensions into groups of items having the same or similar dimensions, thereby providing a device height condition for grouping.
It would have been obvious to one of ordinary skill in the art to further combine Perez and Ji with McBride to group the testing devices by device height, with a reasonable expectation of success as both references address grouping of items by dimension for placement.
Claims 6, 8, 9, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over US20080301609A1 (Perez) in view of US20100325592A1 (Ji), US20200038917A1 (McBride), and US6766501B1 (Duggirala).
In regards to claim 6 (Perez) shows the system of claim 5:
wherein the grouping module is configured to divide the testing devices into type groups according to the device type conditions; Perez [0044] teaches creating a control data set for one or more device types and generating a test structure layout in response, thereby dividing the devices into type groups according to the device type conditions.
Perez differs from the claimed invention in that it does not explicitly disclose divide the testing devices of the type groups into type and height groups according to the device height conditions; and finally divide the testing devices that are not grouped into independent device groups, wherein the type and height groups and the independent device groups are the different testing device groups.
McBride teaches divide the testing devices of the type groups into type and height groups according to the device height conditions; McBride [0023] teaches sorting items into groups of the same or similar dimensions, thereby dividing the type groups into type and height groups according to the device height conditions.
McBride differs from the claimed invention in that it does not explicitly disclose and finally divide the testing devices that are not grouped into independent device groups, wherein the type and height groups and the independent device groups are the different testing device groups.
Duggirala teaches and finally divide the testing devices that are not grouped into independent device groups, wherein the type and height groups and the independent device groups are the different testing device groups; Duggirala [Column 6 Lines 55 - 65] teaches that every element not otherwise grouped is placed in a set of its own, thereby dividing the ungrouped devices into independent device groups.
It would have been obvious to one of ordinary skill in the art to combine Perez, Ji, and McBride to divide the type groups into type and height groups, with a reasonable expectation of success as the references address grouping of devices by dimension.
It would have been obvious to one of ordinary skill in the art to further combine Perez, Ji, and McBride with Duggirala to divide the ungrouped testing devices into independent device groups, with a reasonable expectation of success as the references address partitioning of devices into groups for layout.
In regards to claim 8 (Perez modified by Ji) does not show: wherein the arranging module is configured to compare an entire width of the type and height groups to an available space width within the virtual area, use the type and height groups that meet the available space width as a first arrangement group, use the type and height groups whose entire width greater than the available space width as a cutting remaining group, and determine whether the testing device is able to be arranged between a width of the cutting remaining group and the available space width; when the testing device is not able to be arranged between a width of the cutting remaining group and the available space width, the cutting remaining group is used as a second arrangement group and the arranging module sequentially arranges the first arrangement group and the second arrangement group in the virtual area;
McBride teaches wherein the arranging module is configured to compare an entire width of the type and height groups to an available space width within the virtual area; McBride [0028] teaches comparing a block width to the width of the target area.
McBride teaches use the type and height groups that meet the available space width as a first arrangement group; McBride [0034] teaches placing the block that fits within the target area as the first placed block.
McBride teaches use the type and height groups whose entire width greater than the available space width as a cutting remaining group, and determine whether the testing device is able to be arranged between a width of the cutting remaining group and the available space width; McBride [0028] teaches that a block whose width exceeds the target does not fit, and McBride [0049] teaches determining whether a further item can be placed in the remaining space.
McBride teaches when the testing device is not able to be arranged between a width of the cutting remaining group and the available space width, the cutting remaining group is used as a second arrangement group and the arranging module sequentially arranges the first arrangement group and the second arrangement group in the virtual area; McBride [0040] teaches cutting the remainder at the edges of the placed block to define the next rectangle, and McBride [0041] teaches placing the next block in that remaining rectangle, thereby arranging the first and second groups sequentially.
It would have been obvious to one of ordinary skill in the art to combine Perez, Ji, and McBride to compare the group width to the available space width and to use the fitting groups and the cutting remaining group as arrangement groups, with a reasonable expectation of success as the references address fitting grouped structures within a limited layout width.
In regards to claim 9 (Perez modified by Ji) does not show: wherein the arranging module is configured to determine whether the testing device is able to be arranged between a width of the cutting remaining group and the available space width, wherein when there is a space for arranging a testing device between a width of the cutting remaining group and the available space width, the grouping module conducts secondary grouping for the cutting remaining group and the independent device groups according to the classification conditions and divides the testing devices of the cutting remaining group and the independent device groups into different secondary classification groups, and the arranging module is configured to compare a width of the secondary classification group to the available space width, use the secondary classification group that meets the available space width as a third arrangement group, use the secondary classification group whose width less than the available space width as a final cutting remaining group, arrange the third arrangement group in the virtual area, and combine the final cutting remaining groups with each other and arrange them in the virtual area based on the available space width;
McBride teaches wherein the arranging module is configured to determine whether the testing device is able to be arranged between a width of the cutting remaining group and the available space width; McBride [0049] teaches determining whether a further item can be placed in the remaining space between placed blocks.
McBride teaches wherein when there is a space for arranging a testing device between a width of the cutting remaining group and the available space width, the grouping module conducts secondary grouping for the cutting remaining group and the independent device groups according to the classification conditions and divides the testing devices of the cutting remaining group and the independent device groups into different secondary classification groups; McBride [0023] teaches re-sorting items into groups of similar dimensions, and McBride [0041] teaches recursively forming new groupings for the remaining space, thereby conducting the secondary grouping.
McBride teaches and the arranging module is configured to compare a width of the secondary classification group to the available space width, use the secondary classification group that meets the available space width as a third arrangement group, use the secondary classification group whose width less than the available space width as a final cutting remaining group; McBride [0028] teaches comparing a block width to the available width, and McBride [0034] teaches placing the fitting block, thereby using the fitting secondary group as a third arrangement group and the smaller one as a final cutting remaining group.
McBride teaches arrange the third arrangement group in the virtual area, and combine the final cutting remaining groups with each other and arrange them in the virtual area based on the available space width; McBride [0041] teaches recursively defining new target rectangles from the remainders and filling them with further blocks until all are placed within the available space.
It would have been obvious to one of ordinary skill in the art to combine Perez, Ji, and McBride to conduct secondary grouping of the cutting remaining group and to recursively arrange the resulting groups within the available space, with a reasonable expectation of success as the references address recursive arrangement of grouped structures within a limited layout width.
In regards to claim 10 (Perez) shows the system of claim 9:
wherein the virtual area comprises test lines and the arranging module is configured to arrange the testing devices of the first arrangement group, the second arrangement group, the third arrangement group, and the final cutting remaining group in each of the test lines; Perez [0037] teaches placing the test structure layouts along the left-hand and right-hand rows of the pad array layout, each row serving as a test line in which the arrangement groups are arranged.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over US20080301609A1 (Perez) in view of US20100325592A1 (Ji), US20200038917A1 (McBride), US6766501B1 (Duggirala), and US20140151699A1 (Wu).
In regards to claim 7 (Perez modified by Ji, McBride, and Duggirala) does not show: wherein the arrangement rule is defined to determine whether an entire width of the type and height groups meets an available space width within the virtual area: if yes, arranging in the virtual area the type and height groups that meet the available space width; and if no, cutting the type and height groups that do not meet the available space width or transmitting the type and height groups that do not meet the available space width to the grouping module for secondary grouping;
Wu teaches wherein the arrangement rule is defined to determine whether an entire width of the type and height groups meets an available space width within the virtual area; Wu [0031] teaches determining whether a test structure width is within the available space width, since a width greater than the available width cannot be accommodated.
Wu teaches if yes, arranging in the virtual area the type and height groups that meet the available space width; Wu [0031] teaches that a structure whose width is within the available space width is accommodated within that space.
Wu teaches and if no, cutting the type and height groups that do not meet the available space width or transmitting the type and height groups that do not meet the available space width to the grouping module for secondary grouping; Wu [0032] teaches dividing a structure that exceeds the available width into portions for placement, thereby cutting or re-grouping the groups that do not meet the available space width.
It would have been obvious to one of ordinary skill in the art to further combine Perez, Ji, McBride, and Duggirala with Wu to determine whether the group width meets the available space width and to cut or re-group the groups exceeding that width, with a reasonable expectation of success as the references address fitting test structures within a limited layout width.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over US20080301609A1 (Perez) in view of US20100325592A1 (Ji), US20200038917A1 (McBride), US6766501B1 (Duggirala), and US20040000744A1 (Grigg).
In regards to claim 11 (Perez modified by Ji, McBride, and Duggirala) does not show: wherein the arranging module is configured to mark test line information and device information of each of the testing devices on each of the test lines;
Grigg teaches wherein the arranging module is configured to mark test line information and device information of each of the testing devices on each of the test lines; Grigg [0049] teaches methods of labeling, or marking, semiconductor devices with marking structures, and Grigg [0074] teaches a computer programmed to recognize the location, orientation, and type of each semiconductor device at each location, thereby marking test line and device information on each device.
It would have been obvious to one of ordinary skill in the art to further combine Perez, Ji, McBride, and Duggirala with Grigg to mark test line and device information on the arranged testing devices, with a reasonable expectation of success as the references address identification and labeling of semiconductor devices.
Conclusion
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/ANWER AHMED ALAWDI/Examiner, Art Unit 2851 /JACK CHIANG/ Supervisory Patent Examiner, Art Unit 2851
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