Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4, 8, 11, 15 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Manula et al (US 2007/0112995) (hereinafter Manula) in view of Zhang et al (US 2020/0042425) (hereinafter Zhang).
Regarding claim 1, Manula discloses a computer-implemented method for simplifying PCIe Transaction Layer Packet (TLP) processing logic, the computer-implemented method comprising:
providing a buffer (see Manula, Fig. 9, e.g., RB 328) in a PCIe processing environment between a data link layer (e.g., Fig. 9, DL receive 336) and a transaction layer (e.g., Fig. 9, TL receive 330), wherein the buffer includes a maximum buffer size (see Manula, p. [0102], e.g., only a part of the total buffer space available is pre-allocated to respective transaction types, and the remainder of the total buffer space is kept in reserve for allocation according to needs) and a command interface (e.g., Fig. 9, The transaction/data link interface) to the data link layer (see Manula, p. [0055], e.g., The transaction/data link interface provides: byte or multi-byte data to be sent across the link);
storing PCIe data from the data link layer in the buffer and identifying at least one transaction layer packet in stored PCIe data (see Manula, p. [0075], e.g., After processing by the data link layer receive logic 336, the received information is passed to the receive buffers 328 in the transaction layer receive portion 322);
forwarding the transaction layer packet from the buffer (see Manula. P. [0075-0076], e.g., the received information is passed to the receive buffers 328 in the transaction layer receive portion 322, and is then processed by the transaction layer receive logic 330).
However, Manula does not expressly disclose the PCIe processing environment comprises a plurality of clock cycles; wherein the at least one transaction layer packet is forwarded to the transaction layer for each clock cycle in the plurality of clock cycles of the PCIe processing environment; and determining that an amount of the stored PCIe data is at least equal to the maximum buffer size and notifying the data link layer using the command interface of the buffer that the maximum buffer size has been reached.
Zhang discloses the above recited limitations. In particular, Zhang discloses the PCIe processing environment comprises a plurality of clock cycles (e.g., timer 401); wherein the at least one transaction layer packet is forwarded to the transaction layer for each clock cycle in the plurality of clock cycles of the PCIe processing environment (see Zhang, Fig. 2, p. [0044], e.g., a timer 401 is set for each packet stored in the cache unit, and is configured to record storage duration of the packet in the cache unit. After the packet is sent from a PCIe port, the timer terminates timing performed on the storage duration of the packet); and determining that an amount of the stored PCIe data is at least equal to the maximum buffer size and notifying the data link layer using the command interface of the buffer that the maximum buffer size has been reached (see Zhang, p. [0016], e.g., the device records a quantity of packets that have been stored in the buffer, and when the recorded quantity reaches a third threshold, resets the accumulated duration of packet storage in the buffer to 0, and p. [0051]).
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Zhang’s teachings into Manula. The suggestion/motivation would have been to use a setting timer to perform timing when a time recorded reaches a threshold as suggested by Zhang.
Regarding claim 4, the combined teaching of Manula and Zhang disclose the computer-implemented method of claim 1, wherein the storing the PCIe data from the data link layer in the buffer further comprises determining that the PCIe data from the data link layer is valid (see Zhang, p. [0061], e.g., the processor 14 resets the accumulated duration of packet storage in the buffer 13 to 0 in the preset condition is to record a quantity of packets that have been stored in the buffer 13, and when the recorded quantity reaches a third threshold, reset the accumulated duration of packet storage in the buffer 13 to 0).
Regarding claim 8, Manula discloses a computer system for simplifying PCIe Transaction Layer Packet (TLP) processing logic, the computer system comprising: one or more processors, one or more computer-readable memories, and one or more computer-readable storage media (e.g., Figs 9); program instructions, stored on at least one of the one or more computer-readable storage media for execution by at least one of the one or more processors via at least one of the one or more computer-readable memories, to provide a buffer (see Manula, Fig. 9, e.g., RB 328) in a PCIe processing environment between a data link layer (e.g., Fig. 9, DL receive 336) and a transaction layer (e.g., Fig. 9, TL receive 330), wherein the buffer includes a maximum buffer size (see Manula, p. [0102], e.g., only a part of the total buffer space available is pre-allocated to respective transaction types, and the remainder of the total buffer space is kept in reserve for allocation according to needs) and a command interface (e.g., Fig. 9, The transaction/data link interface) to the data link layer (see Manula, p. [0055], e.g., The transaction/data link interface provides: byte or multi-byte data to be sent across the link);
program instructions, stored on at least one of the one or more computer-readable storage media for execution by at least one of the one or more processors via at least one of the one or more computer-readable memories, to store PCIe data from the data link layer in the buffer and identify at least one transaction layer packet in stored PCIe data (see Manula, p. [0075], e.g., After processing by the data link layer receive logic 336, the received information is passed to the receive buffers 328 in the transaction layer receive portion 322);
program instructions, stored on at least one of the one or more computer-readable storage media for execution by at least one of the one or more processors via at least one of the one or more computer-readable memories, to forward the transaction layer packet from the buffer (see Manula. P. [0075-0076], e.g., the received information is passed to the receive buffers 328 in the transaction layer receive portion 322, and is then processed by the transaction layer receive logic 330).
However, Manula does not expressly disclose the PCIe processing environment comprises a plurality of clock cycles; and wherein the at least one transaction layer packet is forwarded to the transaction layer for each clock cycle in the plurality of clock cycles of the PCIe processing environment; and program instructions, stored on at least one of the one or more computer-readable storage media for execution by at least one of the one or more processors via at least one of the one or more computer-readable memories, to determine that an amount of the stored PCIe data is at least equal to the maximum buffer size and notify the data link layer using the command interface of the buffer that the maximum buffer size has been reached.
Zhang discloses the above recited limitations. In particular, Zhang discloses the PCIe processing environment comprises a plurality of clock cycles (e.g., timer 401); and wherein the at least one transaction layer packet is forwarded to the transaction layer for each clock cycle in the plurality of clock cycles of the PCIe processing environment (see Zhang, Fig. 2, p. [0044], e.g., a timer 401 is set for each packet stored in the cache unit, and is configured to record storage duration of the packet in the cache unit. After the packet is sent from a PCIe port, the timer terminates timing performed on the storage duration of the packet); and program instructions, stored on at least one of the one or more computer-readable storage media for execution by at least one of the one or more processors via at least one of the one or more computer-readable memories, to determine that an amount of the stored PCIe data is at least equal to the maximum buffer size and notify the data link layer using the command interface of the buffer that the maximum buffer size has been reached (see Zhang, p. [0016], e.g., the device records a quantity of packets that have been stored in the buffer, and when the recorded quantity reaches a third threshold, resets the accumulated duration of packet storage in the buffer to 0, and p. [0051]).
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Zhang’s teachings into Manula. The suggestion/motivation would have been to use a setting timer to perform timing when a time recorded reaches a threshold as suggested by Zhang.
Regarding claim 11, the combined teaching of Manula and Zhang disclose the computer system of claim 8, wherein the program instructions, stored on at least one of the one or more computer-readable storage media for execution by at least one of the one or more processors via at least one of the one or more computer-readable memories, to store the PCIe data from the data link layer in the buffer further comprise program instructions, stored on at least one of the one or more computer-readable storage media for execution by at least one of the one or more processors via at least one of the one or more computer-readable memories, to determine that the PCIe data from the data link layer is valid (see Zhang, p. [0061], e.g., the processor 14 resets the accumulated duration of packet storage in the buffer 13 to 0 in the preset condition is to record a quantity of packets that have been stored in the buffer 13, and when the recorded quantity reaches a third threshold, reset the accumulated duration of packet storage in the buffer 13 to 0).
Regarding claim 15, Manula discloses a computer program product for simplifying PCIe Transaction Layer Packet (TLP) processing logic, the computer program product comprising: one or more computer-readable storage media (e.g., Figs 9);
program instructions, stored on at least one of the one or more computer-readable storage media, to provide a buffer (see Manula, Fig. 9, e.g., RB 328) in a PCIe processing environment between a data link layer (e.g., Fig. 9, DL receive 336) and a transaction layer (e.g., Fig. 9, TL receive 330), wherein the buffer includes a maximum buffer size (see Manula, p. [0102], e.g., only a part of the total buffer space available is pre-allocated to respective transaction types, and the remainder of the total buffer space is kept in reserve for allocation according to needs) and a command interface (e.g., Fig. 9, The transaction/data link interface) to the data link layer (see Manula, p. [0055], e.g., The transaction/data link interface provides: byte or multi-byte data to be sent across the link);
program instructions, stored on at least one of the one or more computer-readable storage media, to store PCIe data from the data link layer in the buffer and identify at least one transaction layer packet in stored PCIe data (see Manula, p. [0075], e.g., After processing by the data link layer receive logic 336, the received information is passed to the receive buffers 328 in the transaction layer receive portion 322);
program instructions, stored on at least one of the one or more computer-readable storage media, to forward the transaction layer packet from the buffer (see Manula. P. [0075-0076], e.g., the received information is passed to the receive buffers 328 in the transaction layer receive portion 322, and is then processed by the transaction layer receive logic 330).
However, Manula does not expressly disclose the PCIe processing environment comprises a plurality of clock cycles; wherein the at least one transaction layer packet is forwarded to the transaction layer for each clock cycle in the plurality of clock cycles of the PCIe processing environment; and program instructions, stored on at least one of the one or more computer-readable storage media, to determine that an amount of the stored PCIe data is at least equal to the maximum buffer size and notify the data link layer using the command interface of the buffer that the maximum buffer size has been reached.
Zhang discloses the above recited limitations. In particular, Zhang discloses the PCIe processing environment comprises a plurality of clock cycles; wherein the at least one transaction layer packet is forwarded to the transaction layer for each clock cycle in the plurality of clock cycles of the PCIe processing environment (see Zhang, Fig. 2, p. [0044], e.g., a timer 401 is set for each packet stored in the cache unit, and is configured to record storage duration of the packet in the cache unit. After the packet is sent from a PCIe port, the timer terminates timing performed on the storage duration of the packet); and program instructions, stored on at least one of the one or more computer-readable storage media, to determine that an amount of the stored PCIe data is at least equal to the maximum buffer size and notify the data link layer using the command interface of the buffer that the maximum buffer size has been reached (see Zhang, p. [0016], e.g., the device records a quantity of packets that have been stored in the buffer, and when the recorded quantity reaches a third threshold, resets the accumulated duration of packet storage in the buffer to 0, and p. [0051]).
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Zhang’s teachings into Manula. The suggestion/motivation would have been to use a setting timer to perform timing when a time recorded reaches a threshold as suggested by Zhang.
Regarding claim 18, the combined teaching of Manula and Zhang disclose the computer program product of claim 15, wherein the program instructions, stored on at least one of the one or more computer-readable storage media, to store the PCIe data from the data link layer in the buffer further comprise program instructions, stored on at least one of the one or more computer-readable storage media, to determine that the PCIe data from the data link layer is valid (see Zhang, p. [0061], e.g., the processor 14 resets the accumulated duration of packet storage in the buffer 13 to 0 in the preset condition is to record a quantity of packets that have been stored in the buffer 13, and when the recorded quantity reaches a third threshold, reset the accumulated duration of packet storage in the buffer 13 to 0).
Claims 2-3, 9-10 and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over the combined teaching of Manula and Zhang as applied to claims 1, 4, 8, 11, 15 and 18 above, and further in view of Choudhary et al (US 2021/0013999) (hereinafter Choudhary).
Regarding claim 2, the combined teaching of Manula and Zhang do not expressly disclose the computer-implemented method of claim 1, further comprising requesting, by the data link layer, a replay in the PCIe processing environment in response to the notifying the data link layer using the command interface of the buffer, wherein the PCIe data from the data link layer is nullified starting at a replay position in the PCIe data from the data link layer.
Choudhary discloses the above recited limitations (see Choudhary, p. [0075], e.g., the packet turns out to be a bad TLP, it will simply nullify the packet on the egress port while it waits for the replay of the packet on its ingress port. Depending on the outcome of replay at the ingress port, the egress port may not replay the bad TLP that was nullified. A subsequent location in memory may already be poisoned or has an uncorrectable error while returning the completion data. In that case, the completer nullifies the packet. The completer then resends the TLP with the “EP” (poison) bit set in the TLP header).
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Choudhary’s teachings into the combined teaching of Manula and Zhang. The suggestion/motivation would have been to provide a completer or requester Port in order to wait for the entire TLP to pass its CRC before acting on it as suggested by Choudhary.
Regarding claim 3, the combined teaching of Manula, Zhang and Choudhary disclose the computer-implemented method of claim 2, further comprising storing the PCIe data from the PCIe data link layer in the buffer starting at the replay position in the PCIe data from the data link layer in response to detecting the replay in the PCIe processing environment and determining that the amount of the stored PCIe data is below the maximum buffer size (see Zhang, p. [0020], e.g., the second buffer stores a maximum of one packet at any moment, and claim 4, e.g., Zhang discloses the second buffer stores at least two packets of one packet at any moment, the first buffer is smaller in size than the second buffer).
Regarding claim 9, the combined teaching of Manula, Zhang and Choudhary disclose the computer system of claim 8, further comprising program instructions, stored on at least one of the one or more computer-readable storage media for execution by at least one of the one or more processors via at least one of the one or more computer-readable memories, to request, by the data link layer, a replay in the PCIe processing environment in response to the notifying the data link layer using the command interface of the buffer, wherein the PCIe data from the data link layer is nullified starting at a replay position in the PCIe data from the data link layer (see Choudhary, p. [0075], e.g., the packet turns out to be a bad TLP, it will simply nullify the packet on the egress port while it waits for the replay of the packet on its ingress port. Depending on the outcome of replay at the ingress port, the egress port may not replay the bad TLP that was nullified. A subsequent location in memory may already be poisoned or has an uncorrectable error while returning the completion data. In that case, the completer nullifies the packet. The completer then resends the TLP with the “EP” (poison) bit set in the TLP header).
Regarding claim 10, the combined teaching of Manula, Zhang and Choudhary disclose the computer system of claim 9, further comprising program instructions, stored on at least one of the one or more computer-readable storage media for execution by at least one of the one or more processors via at least one of the one or more computer-readable memories, to store the PCIe data from the PCIe data link layer in the buffer starting at the replay position in the PCIe data from the data link layer in response to detecting the replay in the PCIe processing environment and determining that the amount of the stored PCIe data is below the maximum buffer size (see Zhang, p. [0020], e.g., the second buffer stores a maximum of one packet at any moment, and claim 4, e.g., Zhang discloses the second buffer stores at least two packets of one packet at any moment, the first buffer is smaller in size than the second buffer).
Regarding claim 16, the combined teaching of Manula, Zhang and Choudhary disclose the computer program product of claim 15, further comprising program instructions, stored on at least one of the one or more computer-readable storage media, to request, by the data link layer, a replay in the PCIe processing environment in response to the notifying the data link layer using the command interface of the buffer, wherein the PCIe data from the data link layer is nullified starting at a replay position in the PCIe data from the data link layer (see Choudhary, p. [0075], e.g., the packet turns out to be a bad TLP, it will simply nullify the packet on the egress port while it waits for the replay of the packet on its ingress port. Depending on the outcome of replay at the ingress port, the egress port may not replay the bad TLP that was nullified. A subsequent location in memory may already be poisoned or has an uncorrectable error while returning the completion data. In that case, the completer nullifies the packet. The completer then resends the TLP with the “EP” (poison) bit set in the TLP header).
Regarding claim 17, the combined teaching of Manula, Zhang and Choudhary disclose the computer program product of claim 16, further comprising program instructions, stored on at least one of the one or more computer-readable storage media, to store the PCIe data from the PCIe data link layer in the buffer starting at the replay position in the PCIe data from the data link layer in response to detecting the replay in the PCIe processing environment and determining that the amount of the stored PCIe data is below the maximum buffer size (see Zhang, p. [0020], e.g., the second buffer stores a maximum of one packet at any moment, and claim 4, e.g., Zhang discloses the second buffer stores at least two packets of one packet at any moment, the first buffer is smaller in size than the second buffer).
Claims 5-7, 12-14 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over the combined teaching of Manula and Zhang as applied to claims 1, 4, 8, 11, 15 and 18 above, and further in view of Raisch et al (US 2019/0310947) (hereinafter Raisch).
Regarding claim 5, the combined teaching of Manula and Zhang do not expressly disclose the computer-implemented method of claim 1, wherein the buffer comprises a plurality of arrays, further comprising obtaining metadata from the at least one transaction layer packet and associating the metadata with each array in the plurality of arrays.
Raisch discloses the above recited limitations (see Raisch, Fig. 4, p. [0064], e.g., The memory 400 may comprise an array with a plurality of request metadata entries 402, and The I/O receiver may fetch the metadata array and then transfer data pointed to by metadata into an internal buffer).
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Raisch’s teachings into the combined teaching of Manula and Zhang. The suggestion/motivation would have been to provide information for identifying the data to be transferred between the memory and the input/output device as suggested by Raisch.
Regarding claim 6, the combined teaching of Manula, Zhang and Raisch disclose the computer-implemented method of claim 5, wherein the metadata is selected from a group consisting of: a transaction layer packet start indicator, a transaction layer packet end indicator and a transaction layer packet nullify indicator (see Raisch, p. [0031-0032], e.g., the metadata comprises one or more of the following: an identifier of the transfer operation to be executed, an identifier of the origin location of the data to be transferred, an identifier of the target location of the data to be transferred, and an identifier of the size of the data to be transferred. Embodiments may have the beneficial effect of providing all the information for executing the data transfer by the metadata).
Regarding claim 7, the combined teaching of Manula, Zhang and Raisch disclose the computer-implemented method of claim 5, wherein each array in the plurality of arrays is four bytes wide (see Raisch, Fig. 4, p. [0061], e.g., The size of array 402 may, e.g., be fixed per device type or communicated during a setup).
Regarding claim 12, the combined teaching of Manula, Zhang and Raisch disclose the computer system of claim 8, wherein the buffer comprises a plurality of arrays, further comprising program instructions, stored on at least one of the one or more computer-readable storage media for execution by at least one of the one or more processors via at least one of the one or more computer-readable memories, to obtain metadata from the at least one transaction layer packet and associate the metadata with each array in the plurality of arrays (see Raisch, Fig. 4, p. [0064], e.g., The memory 400 may comprise an array with a plurality of request metadata entries 402, and The I/O receiver may fetch the metadata array and then transfer data pointed to by metadata into an internal buffer).
Regarding claim 13, the combined teaching of Manula, Zhang and Raisch disclose the computer system of claim 12, wherein the metadata is selected from a group consisting of: a transaction layer packet start indicator, a transaction layer packet end indicator and a transaction layer packet nullify indicator (see Raisch, p. [0031-0032], e.g., the metadata comprises one or more of the following: an identifier of the transfer operation to be executed, an identifier of the origin location of the data to be transferred, an identifier of the target location of the data to be transferred, and an identifier of the size of the data to be transferred. Embodiments may have the beneficial effect of providing all the information for executing the data transfer by the metadata).
Regarding claim 14, the combined teaching of Manula, Zhang and Raisch disclose the computer system of claim 12, wherein each array in the plurality of arrays is four bytes wide (see Raisch, Fig. 4, p. [0061], e.g., The size of array 402 may, e.g., be fixed per device type or communicated during a setup).
Regarding claim 19, the combined teaching of Manula, Zhang and Raisch disclose the computer program product of claim 15, wherein the buffer comprises a plurality of arrays, further comprising program instructions, stored on at least one of the one or more computer-readable storage media, to obtain metadata from the at least one transaction layer packet and associate the metadata with each array in the plurality of arrays (see Raisch, Fig. 4, p. [0064], e.g., The memory 400 may comprise an array with a plurality of request metadata entries 402, and The I/O receiver may fetch the metadata array and then transfer data pointed to by metadata into an internal buffer).
Regarding claim 20, the combined teaching of Manula, Zhang and Raisch disclose the computer program product of claim 19, wherein the metadata is selected from a group consisting of: a transaction layer packet start indicator, a transaction layer packet end indicator and a transaction layer packet nullify indicator (see Raisch, p. [0031-0032], e.g., the metadata comprises one or more of the following: an identifier of the transfer operation to be executed, an identifier of the origin location of the data to be transferred, an identifier of the target location of the data to be transferred, and an identifier of the size of the data to be transferred. Embodiments may have the beneficial effect of providing all the information for executing the data transfer by the metadata).
Conclusion
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/MINH TRANG T NGUYEN/Primary Examiner, Art Unit 2477