DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1 , 2, 9, 11-14, 16 , 19, and 20 is/are rejected under 35 U.S.C. 102 a(1) as being anticipated by Hsieh (US 2006/0197591) . Referring to Claim 1, Hsieh teaches a programmable amplifier, comprising: an n-channel metal-oxide-semiconductor (NMOS) amplification path that includes a first NMOS transistor 314 (fig. 3) and a second NMOS transistor 324 (fig. 3) that are connected in parallel between an input and an output (see fig. 3 where transistors 314 and 324 are connected in parallel and between input V3,V4 and output To) ; a complementary metal-oxide-semiconductor (CMOS) amplification path that includes a p-channel metal-oxide-semiconductor (PMOS) transistor 312 (fig. 3) connected in parallel with the first NMOS transistor 314 (fig. 3) between the input and the output (see fig. 3 where transistors 312 and 314 are connected in parallel and between input V3,V4 and output To ) ; and a plurality of switches that are programmable to switch the PMOS transistor off in a first mode and to switch the second NMOS transistor off in a second mode (see fig. 3 which shows the PMOS transistor off when switches S1 and S4 are opened and S2 and S3 are closed as further described in paragraph 35 which shows only the NMOS transistors operating and the second NMOS transistor is off when S 1 and S 2 are opened and S 3 and S 4 are closed as further described in paragraph 36 ) . Referring to Claim 11, Hsieh teaches a method, comprising: configuring, at a first time, a plurality of switches to drive a load in a circuit using an n-channel metal-oxide-semiconductor (NMOS) amplification path that includes a first NMOS transistor and a second NMOS transistor that are connected in parallel between an input and an output of the circuit (see fig. 3 where first and second NMOS transistors 314 and 324 are connected in parallel and between input V3,V4 and output To and also showing the PMOS transistor off when switches S1 and S4 are opened and S2 and S3 are closed as further described in paragraph 35 which shows only the NMOS transistors operating ; and configuring, at a second time, the plurality of switches to drive the load in the circuit using a complementary metal-oxide-semiconductor (CMOS) amplification path that includes a p-channel metal-oxide-semiconductor (PMOS) transistor connected in parallel with the first NMOS transistor between the input and the output of the circuit (see fig. 3 where PMOS transistor 312 and NMOS transistor 314 are connected in parallel and between input V3,V4 and output To and also showing the second NMOS transistor is off when S1 and S2 are opened and S3 and S4 are closed as further described in paragraph 36 ). Referring to Claim 16, Hsieh teaches a circuit, comprising: a first n-channel metal-oxide-semiconductor (NMOS) transistor in a first amplification path (see fig. 3 which shows the first amplification path including NMOS transistor 324) ; a p-channel metal-oxide-semiconductor (PMOS) transistor in a second amplification path (see fig. 3 which shows the second amplification including PMOS transistor 312) ; a second NMOS transistor in the first amplification path and the second amplification path (see fig. 3 which shows NMOS transistor 314 in the amplification path of NMOS transistor 324 and PMOS transistor 312) ; and a plurality of switches that are programmable to switch the PMOS transistor off in an NMOS mode and to switch the first NMOS transistor off in a complementary metal-oxide-semiconductor (CMOS) mode ( see fig. 3 which shows the PMOS transistor off when switches S1 and S4 are opened and S2 and S3 are closed as further described in paragraph 35 which shows only the NMOS transistors operating and the second NMOS transistor is off when S1 and S2 are opened and S3 and S4 are closed as further described in paragraph 36 ). Referring to Claim 2, Hsieh also teaches the first mode a s a high linearity mode (see paragraph 35 which shows the switches in a formation which has the NMOS transistors amplifying in parallel with a reduced power offset which shows high linearity since the output signal will be undistorted) and the second mode a s a low current mod e (see paragraph 36 which shows the switches in a formation which forms low current). Referring to Claim 9, Hsieh also teaches the plurality of switches programmed to drive a load in a signal path of a wireless receiver according to one or more of a current requirement or a linearity requirement (see paragraph 34 which shows driving the load according to a current requirement). Referring to Claim 12, Hsieh also teaches the plurality of switches configured to drive the load using the NMOS amplification path at the first time based at least in part on a high linearity requirement at the first time ( see paragraph 35 which shows the switches in a formation which has the NMOS transistors amplifying in parallel with a reduced power offset which shows high linearity since the output signal will be undistorted ). Referring to Claim 13, Hsieh also teaches the plurality of switches configured to drive the load using the CMOS amplification path at the second time based at least in part on a low current requirement or a low power consumption requirement at the second time (see paragraph 36 which shows the switches in a formation which forms low current). Referring to Claim 14, Hsieh also teaches configuring, at a third time, the plurality of switches to drive the load in the circuit using the NMOS amplification path with the first NMOS transistor switched off (see paragraph 34 which shows driving the load and paragraph 36 which shows the NMOS transistor switched off ). Referring to Claim 19, Hsieh also teaches the plurality of switches are programmable to drive a load in a signal path of a wireless receiver in the NMOS mode, the CMOS mode, or the sliced NMOS mode according to one or more of a current requirement or a linearity requirement ( see paragraph 34 which shows driving the load according to a current requirement) . Referring to Claim 20, the plurality of switches programmable to drive a load in a signal path of a wireless transmitter in the NMOS mode, the CMOS mode, or the sliced NMOS mode according to one or more of a current requirement or a linearity requirement (see paragraph 34 which shows driving the load according to a current requirement) . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim (s) 3, 4 , and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsieh in view of Ngai (US 2010/0277230) . Referring to Claim 3, Hsieh does not teach the plurality of switches further programmable to switch the PMOS transistor and the first NMOS transistor off in a third mod e . Ngai teaches the plurality of switches further programmable to switch the PMOS transistor and the first NMOS transistor off in a third mod e (see paragraph 36 which shows both PMOS and NMOS transistors switched off). Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to provide the teachings of Ngai to the device of Hsieh in order to better reduce unwanted noise. Referring to Claim 4, Ngai also teaches the third mode is associated with one or more of a lower gain or a lower current than the first mode and a higher linearity than the second mod e (see paragraph 42 which shows the current near zero and paragraph 36 which shows improved linearity). Referring to Claim 18, Ngai also teaches the plurality of switches further programmable to switch the PMOS transistor and the second NMOS transistor off in a sliced NMOS mode (see paragraph 36 which shows both PMOS and NMOS transistors switched off). Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to provide the teachings of Ngai to the device of Hsieh in order to better reduce unwanted noise. Claim (s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsieh in view of Cabrera et al. (US 2014/0009233) . Referring to Claim 5, Hsieh does not teach an NMOS bias that includes a voltage supply and an inductor coupled to the first NMOS transistor and the second NMOS transistor in the first mode; and an output capacitor arranged to isolate the PMOS transistor and the first NMOS transistor from the voltage supply in the second mode. Cabrera teaches an NMOS bias that includes a voltage supply and an inductor coupled to the first NMOS transistor and the second NMOS transistor in the first mode (see inductor L8 in fig. 5 coupled to NMOS transistors Q5 and Q7 in fig. 5) ; and an output capacitor arranged to isolate the PMOS transistor and the first NMOS transistor from the voltage supply in the second mode (see capacitor C15 coupled to NMOS transistor Q7 and PMOS transistor Q6 in fig. 5) . Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to provide the teachings of Cabrera to the device of Hsieh in order to better maintain high signal efficiency in multiple modes. Claim (s) 6 , 7 , and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsieh and Cabrera and further in view of Alam et al. (US 2021/0376797) . Referring to Claim 6 , the combination of Hsieh and Cabrera does not teach the plurality of switches includ ing a switch, across the output capacitor, that is closed in the first mode and open in the second mode . Alam teaches the plurality of switches includ ing a switch, across the output capacitor, that is closed in the first mode and open in the second mode (see fig. 11 which shows switch 1122B which bypasses the output capacitor). Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to provide the teachings of Alam to the modified device of Hsieh and Cabrera in order to maintain high quality communication in high traffic. Referring to Claim 7, Alam also teaches a switch, coupled between a drain of the PMOS transistor and an output of the CMOS amplification path, that is open in the first mode to isolate a nonlinear parasitic capacitance from the PMOS transistor that is switched off in the first mode (see switch 1124B which is coupled between transistors 1104 and 1106). Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to provide the teachings of Alam to the modified device of Hsieh and Cabrera in order to maintain high quality communication in high traffic. Referring to Claim 15, Alam also teaches a switch, across an output capacitor, that is closed at the first time and open at the second time (see fig. 11 which shows switch 1122B which bypasses the output capacitor). Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to provide the teachings of Alam to the modified device of Hsieh and Cabrera in order to maintain high quality communication in high traffic. Claim (s) 8 , 10 , and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsieh in view of Agrawal et al. (US 2022/0200642) . Referring to Claim 8, Hsieh does not teach a neutralization circuit arranged to neutralize a nonlinear parasitic capacitance from the first NMOS transistor and the second NMOS transistor in the first mode . Agrawal teaches a neutralization circuit arranged to neutralize a nonlinear parasitic capacitance from the first NMOS transistor and the second NMOS transistor in the first mode (see paragraph 209 which shows neutralization capacitors in a circuit with NMOS transistors as shown in paragraph 174). Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to provide the teachings of Agrawal to the device of Hsieh in order to better operate in wider bandwidths and more modulation schemes. Referring to Claim 10, Agrawal also teaches the signal path included in or coupled to a millimeter wave integrated circuit (see paragraph 76 which shows a millimeter wave IC) . Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to provide the teachings of Agrawal to the device of Hsieh in order to better operate in wider bandwidths and more modulation schemes. Referring to Claim 17, Agrawal also teaches a neutralization circuit arranged to neutralize a nonlinear parasitic capacitance from the first NMOS transistor and the second NMOS transistor in the NMOS mode (see paragraph 209 which shows neutralization capacitors in a circuit with NMOS transistors as shown in paragraph 174). Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to provide the teachings of Agrawal to the device of Hsieh in order to better operate in wider bandwidths and more modulation schemes. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT EUGENE YUN whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)272-7860 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT 9am-5pm . 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Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /EUGENE YUN/ Primary Examiner, Art Unit 2648