Prosecution Insights
Last updated: April 19, 2026
Application No. 18/610,636

WIRING BOARD UNIT AND METHOD FOR DESIGNING THE SAME

Non-Final OA §103
Filed
Mar 20, 2024
Examiner
SAWYER, STEVEN T
Art Unit
2847
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Toppan Holdings Inc.
OA Round
1 (Non-Final)
72%
Grant Probability
Favorable
1-2
OA Rounds
2y 6m
To Grant
99%
With Interview

Examiner Intelligence

Grants 72% — above average
72%
Career Allow Rate
733 granted / 1017 resolved
+4.1% vs TC avg
Strong +31% interview lift
Without
With
+30.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
42 currently pending
Career history
1059
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
60.4%
+20.4% vs TC avg
§102
26.9%
-13.1% vs TC avg
§112
10.6%
-29.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1017 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Drawings The drawings are objected to under 37 CFR 1.84(h)(5) because Figures 6 and 13 show(s) modified forms of construction in the same view. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Objections Claims 1, 8, 9 and 16 are objected to because of the following informalities: These claims state, “(hereinafter referred to as a “first surface”)”. The Applicant is encouraged to positively claim this surface as initially being “the first surface” within the claim and not including the “()” to further explain its meaning. Appropriate correction is required. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shimizu et al. (US PG. Pub. 2018/0166372) in view of Nishimura et al. (US PG. Pub. 2020/0344870). Regarding claim 1 – Shimizu teaches a wiring board unit (fig. 3, 100), comprising: a first wiring board (11 [paragraph 0027] Shimizu states, “wiring structure 11”) and a second wiring board (12 [paragraph 0027] Shimizu states, “wiring structure 12”) bonded to the first wiring board (11), a semiconductor element (101 [paragraph 0080] Shimizu states, “semiconductor chip 101”) being resin-sealed (105 [paragraph 0080] Shimizu states, “underfill resin 105”) on a surface side (hereinafter referred to as a "first surface") (upper surface of second wiring board 12) of the second wiring board (12) opposite to a surface (bottom surface) for bonding with the first wiring board (11) and the second wiring board having an insulating resin material ([paragraph 0045] Shimizu states, “A photosensitive insulative resin, the main component of which is a phenol-based resin, a polyimide-based resin, or the like, for example, may be used as the material of the insulating layers 61, 63, 65”) Shimizu fails to teach wherein a tensile strength of an insulating resin material used for the second wiring board and a width of a Cu pattern formed on the first surface give a value less than 0.5 when substituted in Formula 1 below. [Formula 1] 1/(1+Exp(-A)) ... (1) A= -15.45 - 0.1654 x Tensile strength + 11.31 x log (Cu pattern width). Nishimura teaches wherein a tensile strength ([table 1 & 0150] Nishimura states, “the stress and elongation at break were measure as tensile strength…results are shown in Table 1…tensile strength (MPa) 100, 70, 75, 56, 78, 84, 95, 65, 70, 89, 44”) of an insulating resin material (figs. 1-2, 12 [paragraph 0043] Nishimura states, “resin layer 12”) used for a wiring board (100 [paragraph 0043] Nishimura states, “circuit board 100”) and a width of a Cu pattern ([paragraph 0155] Nishimura states, “and copper wiring patterns having a pitch of 150 μm and a line width of 40, 45, 50, 55 and 60 μm, and a pitch of 750 μm and a line width of 200, 220, 240, 260 and 280 μm”) formed on the first surface give a value less than 0.5 when substituted in Formula 1 below. [Formula 1] 1/(1+Exp(-A)) ... (1) A= -15.45 - 0.1654 x Tensile strength + 11.31 x log (Cu pattern width) (In the instant application Applicant specifies value ranges of tensile strength in paragraph 0081 from 90-170MPa and CU pattern width being 20-2000um, Nishimura teaches values within these ranges as quoted above and will therefore meet the less than .5 range of the formula above and would reasonably be considered to have the same properties, i.e. no cracking). It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the wiring board unit having a first and second wiring board bonded together with a semiconductor element on the upper surface of the second wiring board with an insulating resin material being used for the second wiring board as taught by Shimizu with the tensile strength of the insulating resin material and the width of a Cu pattern formed therein are selected so that the formula ([Formula 1] 1/(1+Exp(-A)) ... (1) A= -15.45 - 0.1654 x Tensile strength + 11.31 x log (Cu pattern width)) will be less than 0.5 as taught by Nishimura because Nishimura states, “The results shown in Table 1 indicates that the circuit boards obtained in Examples 1 to 7 reduced the transmission loss of electric signals in the high-frequency circuit, and had excellent smoothness.” [paragraph 0178]. Regarding claim 2 – Shimizu in view of Nishimura teach the wiring board unit of claim 1, wherein the tensile strength (Nishimura; [table 1 & 0150] Nishimura states, “the stress and elongation at break were measure as tensile strength…results are shown in Table 1…tensile strength (MPa) 100, 70, 75, 56, 78, 84, 95, 65, 70, 89, 44”) of the insulating resin material (figs. 1-2, 12 [paragraph 0043] Nishimura states, “resin layer 12”) used for the second wiring board and the width of the Cu pattern ([paragraph 0158] Nishimura states, “copper wiring pattern having a pitch of 100um and a line width of 50um”) formed on the first surface give a value of 0.1 or less when substituted in the Formula 1 (Applicant specifies value ranges of tensile strength in paragraph 0081 from 90-170MPa and CU pattern width 20-2000um, Nishimura teaches values within these ranges as quoted above and will therefore meet the 0.1 or less range of the formula above). Regarding claim 3 – Shimizu in view of Nishimura teach the wiring board unit of claim 1, where in the second wiring board (Shimizu; fig. 12) is a multilayer wiring board (figure 3 shows the second wiring board 12 being comprised of three insulating layers (61, 63 & 65) with intervening metal layers). Regarding claim 4 – Shimizu in view of Nishimura teach the wiring board unit of claim 3, but fail to teach wherein the multilayer wiring board is formed by SAP or a damascene process. In accordance to MPEP 2113, the method of forming the device is not germane to the issue of patentability of the device itself. Therefore, this limitation has not been given patentable weight. Please note that even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product, i.e. “the multilayer wiring board”, does not depend on its method of production, i.e. “formed by SAP or a damascene process”. In re Thorpe, 227 USPQ 964, 966 (Federal Circuit 1985). Regarding claim 5 – Shimizu in view of Nishimura teach the wiring board unit of claim 1, wherein the insulating resin material (Shimizu; fig. 3, 61, 63 & 65) of the second wiring board (12) is a photosensitive insulating resin ([paragraph 0045] Shimizu states, “A photosensitive insulative resin, the main component of which is a phenol-based resin, a polyimide-based resin, or the like, for example, may be used as the material of the insulating layers 61, 63, 65”). Regarding claim 6 – Shimizu in view of Nishimura teach the wiring board unit of claim 3, wherein the insulating resin material (Shimizu; fig. 3, 61, 63 & 65) of the second wiring board (12) is a photosensitive insulating resin ([paragraph 0045] Shimizu states, “A photosensitive insulative resin, the main component of which is a phenol-based resin, a polyimide-based resin, or the like, for example, may be used as the material of the insulating layers 61, 63, 65”). Regarding claim 7 – Shimizu in view of Nishimura teach the wiring board unit of claim 4, wherein the insulating resin material (Shimizu; fig. 3, 61, 63 & 65) of the second wiring board (12) is a photosensitive insulating resin ([paragraph 0045] Shimizu states, “A photosensitive insulative resin, the main component of which is a phenol-based resin, a polyimide-based resin, or the like, for example, may be used as the material of the insulating layers 61, 63, 65”). Regarding claim 8 – Shimizu teaches a method of designing a wiring board unit (fig. 3, 100) including a first wiring board (11 [paragraph 0027] Shimizu states, “wiring structure 11”) and a second wiring board (12 [paragraph 0027] Shimizu states, “wiring structure 12”) bonded to the first wiring board (11), a semiconductor element (101 [paragraph 0080] Shimizu states, “semiconductor chip 101”) being resin-sealed (105 [paragraph 0080] Shimizu states, “underfill resin 105”) on a surface side (hereinafter referred to as a "first surface") (upper surface of second wiring board 12) of the second wiring board (12) opposite to a surface (bottom surface) for bonding with the first wiring board (11) and the second wiring board having an insulating resin material ([paragraph 0045] Shimizu states, “A photosensitive insulative resin, the main component of which is a phenol-based resin, a polyimide-based resin, or the like, for example, may be used as the material of the insulating layers 61, 63, 65”) Shimizu fails to teach the method including setting a tensile strength of an insulating resin material used for the second wiring board and a width of a Cu pattern formed on the first surface give a value less than 0.5 when substituted in Formula 1 below. [Formula 1] 1/(1+Exp(-A)) ... (1) A= -15.45 - 0.1654 x Tensile strength + 11.31 x log (Cu pattern width). Nishimura teaches a method including setting a tensile strength ([table 1 & 0150] Nishimura states, “the stress and elongation at break were measure as tensile strength…results are shown in Table 1…tensile strength (MPa) 100, 70, 75, 56, 78, 84, 95, 65, 70, 89, 44”) of an insulating resin material (figs. 1-2, 12 [paragraph 0043] Nishimura states, “resin layer 12”) used for a wiring board (100 [paragraph 0043] Nishimura states, “circuit board 100”) and a width of a Cu pattern ([paragraph 0155] Nishimura states, “and copper wiring patterns having a pitch of 150 μm and a line width of 40, 45, 50, 55 and 60 μm, and a pitch of 750 μm and a line width of 200, 220, 240, 260 and 280 μm”) formed on the first surface give a value less than 0.5 when substituted in Formula 1 below. [Formula 1] 1/(1+Exp(-A)) ... (1) A= -15.45 - 0.1654 x Tensile strength + 11.31 x log (Cu pattern width) (In the instant application Applicant specifies value ranges of tensile strength in paragraph 0081 from 90-170MPa and CU pattern width being 20-2000um, Nishimura teaches values within these ranges as quoted above and will therefore meet the less than .5 range of the formula above and would reasonably be considered to have the same properties, i.e. no cracking). It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the method of designing a wiring board unit having a first and second wiring board bonded together with a semiconductor element on the upper surface of the second wiring board with an insulating resin material being used for the second wiring board as taught by Shimizu with the method including setting a tensile strength of the insulating resin material and the width of a Cu pattern formed therein are selected so that the formula ([Formula 1] 1/(1+Exp(-A)) ... (1) A= -15.45 - 0.1654 x Tensile strength + 11.31 x log (Cu pattern width)) will be less than 0.5 as taught by Nishimura because Nishimura states, “The results shown in Table 1 indicates that the circuit boards obtained in Examples 1 to 7 reduced the transmission loss of electric signals in the high-frequency circuit, and had excellent smoothness.” [paragraph 0178]. Regarding claim 9 – Shimizu teaches a wiring board unit (fig. 3, 100), comprising: a first wiring board (11 [paragraph 0027] Shimizu states, “wiring structure 11”) and a second wiring board (12 [paragraph 0027] Shimizu states, “wiring structure 12”) bonded to the first wiring board (11), a semiconductor element (101 [paragraph 0080] Shimizu states, “semiconductor chip 101”) being resin-sealed (105 [paragraph 0080] Shimizu states, “underfill resin 105”) on a surface side (hereinafter referred to as a "first surface") (upper surface of second wiring board 12) of the second wiring board (12) opposite to a surface (bottom surface) for bonding with the first wiring board (11) and the second wiring board having an insulating resin material ([paragraph 0045] Shimizu states, “A photosensitive insulative resin, the main component of which is a phenol-based resin, a polyimide-based resin, or the like, for example, may be used as the material of the insulating layers 61, 63, 65”) Shimizu fails to teach wherein a tensile strength of an insulating resin material used for the second wiring board and a width of a Cu pattern formed on the first surface give a value less than 0.5 when substituted in Formula 1 below. [Formula 2] 1/(1+Exp(-A)) ... (1) A= 0.227 - 0.1619 x Tensile strength + 6.648 x log (Cu pattern width). Nishimura teaches wherein a tensile strength ([table 1 & 0150] Nishimura states, “the stress and elongation at break were measure as tensile strength…results are shown in Table 1…tensile strength (MPa) 100, 70, 75, 56, 78, 84, 95, 65, 70, 89, 44”) of an insulating resin material (figs. 1-2, 12 [paragraph 0043] Nishimura states, “resin layer 12”) used for a wiring board (100 [paragraph 0043] Nishimura states, “circuit board 100”) and a width of a Cu pattern ([paragraph 0155] Nishimura states, “and copper wiring patterns having a pitch of 150 μm and a line width of 40, 45, 50, 55 and 60 μm, and a pitch of 750 μm and a line width of 200, 220, 240, 260 and 280 μm”) formed on the first surface give a value less than 0.5 when substituted in Formula 1 below. [Formula 2] 1/(1+Exp(-A)) ... (1) A= 0.227 - 0.1619 x Tensile strength + 6.648 x log (Cu pattern width) (In the instant application Applicant specifies value ranges of tensile strength in paragraph 0081 from 90-170MPa and CU pattern width being 20-2000um, Nishimura teaches values within these ranges as quoted above and will therefore meet the less than .5 range of the formula above and would reasonably be considered to have the same properties, i.e. no cracking). It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the wiring board unit having a first and second wiring board bonded together with a semiconductor element on the upper surface of the second wiring board with an insulating resin material being used for the second wiring board as taught by Shimizu with the tensile strength of the insulating resin material and the width of a Cu pattern formed therein are selected so that the formula ([Formula 1] 1/(1+Exp(-A)) ... (1) A= -15.45 - 0.1654 x Tensile strength + 11.31 x log (Cu pattern width)) will be less than 0.5 as taught by Nishimura because Nishimura states, “The results shown in Table 1 indicates that the circuit boards obtained in Examples 1 to 7 reduced the transmission loss of electric signals in the high-frequency circuit, and had excellent smoothness.” [paragraph 0178]. Regarding claim 10 – Shimizu in view of Nishimura teach the wiring board unit of claim 9, wherein the tensile strength (Nishimura; [table 1 & 0150] Nishimura states, “the stress and elongation at break were measure as tensile strength…results are shown in Table 1…tensile strength (MPa) 100, 70, 75, 56, 78, 84, 95, 65, 70, 89, 44”) of the insulating resin material (figs. 1-2, 12 [paragraph 0043] Nishimura states, “resin layer 12”) used for the second wiring board and the width of the Cu pattern ([paragraph 0158] Nishimura states, “copper wiring pattern having a pitch of 100um and a line width of 50um”) formed on the first surface give a value of 0.1 or less when substituted in the Formula 2 (Applicant specifies value ranges of tensile strength in paragraph 0081 from 90-170MPa and CU pattern width 20-2000um, Nishimura teaches values within these ranges as quoted above and will therefore meet the 0.1 or less range of the formula above). Regarding claim 11 – Shimizu in view of Nishimura teach the wiring board unit of claim 9, where in the second wiring board (Shimizu; fig. 12) is a multilayer wiring board (figure 3 shows the second wiring board 12 being comprised of three insulating layers (61, 63 & 65) with intervening metal layers). Regarding claim 12 – Shimizu in view of Nishimura teach the wiring board unit of claim 11, but fail to teach wherein the multilayer wiring board is formed by SAP or a damascene process. In accordance to MPEP 2113, the method of forming the device is not germane to the issue of patentability of the device itself. Therefore, this limitation has not been given patentable weight. Please note that even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product, i.e. “the multilayer wiring board”, does not depend on its method of production, i.e. “formed by SAP or a damascene process”. In re Thorpe, 227 USPQ 964, 966 (Federal Circuit 1985). Regarding claim 13 – Shimizu in view of Nishimura teach the wiring board unit of claim 9, where in the second wiring board (Shimizu; fig. 12) is a multilayer wiring board (figure 3 shows the second wiring board 12 being comprised of three insulating layers (61, 63 & 65) with intervening metal layers). Regarding claim 14 – Shimizu in view of Nishimura teach the wiring board unit of claim 11, where in the second wiring board (Shimizu; fig. 12) is a multilayer wiring board (figure 3 shows the second wiring board 12 being comprised of three insulating layers (61, 63 & 65) with intervening metal layers). Regarding claim 15 – Shimizu in view of Nishimura teach the wiring board unit of claim 12, where in the second wiring board (Shimizu; fig. 12) is a multilayer wiring board (figure 3 shows the second wiring board 12 being comprised of three insulating layers (61, 63 & 65) with intervening metal layers). Regarding claim 16 – Shimizu teaches a method of designing a wiring board unit (fig. 3, 100) including a first wiring board (11 [paragraph 0027] Shimizu states, “wiring structure 11”) and a second wiring board (12 [paragraph 0027] Shimizu states, “wiring structure 12”) bonded to the first wiring board (11), a semiconductor element (101 [paragraph 0080] Shimizu states, “semiconductor chip 101”) being resin-sealed (105 [paragraph 0080] Shimizu states, “underfill resin 105”) on a surface side (hereinafter referred to as a "first surface") (upper surface of second wiring board 12) of the second wiring board (12) opposite to a surface (bottom surface) for bonding with the first wiring board (11) and the second wiring board having an insulating resin material ([paragraph 0045] Shimizu states, “A photosensitive insulative resin, the main component of which is a phenol-based resin, a polyimide-based resin, or the like, for example, may be used as the material of the insulating layers 61, 63, 65”) Shimizu fails to teach the method including setting a tensile strength of an insulating resin material used for the second wiring board and a width of a Cu pattern formed on the first surface give a value less than 0.5 when substituted in Formula 2 below. [Formula 2] 1/(1+Exp(-A)) ... (1) A= 0.227 – 0.1619 x Tensile strength + 6.648 x log (Cu pattern width). Nishimura teaches a method including setting a tensile strength ([table 1 & 0150] Nishimura states, “the stress and elongation at break were measure as tensile strength…results are shown in Table 1…tensile strength (MPa) 100, 70, 75, 56, 78, 84, 95, 65, 70, 89, 44”) of an insulating resin material (figs. 1-2, 12 [paragraph 0043] Nishimura states, “resin layer 12”) used for a wiring board (100 [paragraph 0043] Nishimura states, “circuit board 100”) and a width of a Cu pattern ([paragraph 0155] Nishimura states, “and copper wiring patterns having a pitch of 150 μm and a line width of 40, 45, 50, 55 and 60 μm, and a pitch of 750 μm and a line width of 200, 220, 240, 260 and 280 μm”) formed on the first surface give a value less than 0.5 when substituted in Formula 1 below. [Formula 2] 1/(1+Exp(-A)) ... (1) A= 0.227 – 0.1619 x Tensile strength + 6.648 x log (Cu pattern width) (In the instant application Applicant specifies value ranges of tensile strength in paragraph 0081 from 90-170MPa and CU pattern width being 20-2000um, Nishimura teaches values within these ranges as quoted above and will therefore meet the less than .5 range of the formula above and would reasonably be considered to have the same properties, i.e. no cracking). It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the method of designing a wiring board unit having a first and second wiring board bonded together with a semiconductor element on the upper surface of the second wiring board with an insulating resin material being used for the second wiring board as taught by Shimizu with the method including setting a tensile strength of the insulating resin material and the width of a Cu pattern formed therein are selected so that the formula ([Formula 2] 1/(1+Exp(-A)) ... (1) A= 0.227 – 0.1619 x Tensile strength + 6.648 x log (Cu pattern width)) will be less than 0.5 as taught by Nishimura because Nishimura states, “The results shown in Table 1 indicates that the circuit boards obtained in Examples 1 to 7 reduced the transmission loss of electric signals in the high-frequency circuit, and had excellent smoothness.” [paragraph 0178]. Regarding claim 17 – Shimizu in view of Nishimura teach the wiring board unit of claim 2, where in the second wiring board (Shimizu; fig. 12) is a multilayer wiring board (figure 3 shows the second wiring board 12 being comprised of three insulating layers (61, 63 & 65) with intervening metal layers). Regarding claim 18 – Shimizu in view of Nishimura teach the wiring board unit of claim 10, where in the second wiring board (Shimizu; fig. 12) is a multilayer wiring board (figure 3 shows the second wiring board 12 being comprised of three insulating layers (61, 63 & 65) with intervening metal layers). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Akutagawa et al. (WO2018047861) disposes a wiring board unit having a first and second wiring board with a chip on the second wiring board. Fukao et al. (US PG. Pub. 2023/0167215) discloses a resin composition having a tensile strength. Takai et al. (US PG. Pub. 2005/0106370) discloses a formation method of metal layer on resin layer, printed circuit board. Imai et al. (US PG. Pub. 2024/0301115) discloses a negative-type photosensitive polymer. Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN T SAWYER whose telephone number is (571)270-5469. The examiner can normally be reached M-F 8:30 am - 5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at 5712722342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /STEVEN T SAWYER/Primary Examiner, Art Unit 2847
Read full office action

Prosecution Timeline

Mar 20, 2024
Application Filed
Nov 26, 2025
Non-Final Rejection — §103 (current)

Precedent Cases

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Expected OA Rounds
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Grant Probability
99%
With Interview (+30.9%)
2y 6m
Median Time to Grant
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