Prosecution Insights
Last updated: July 17, 2026
Application No. 18/610,636

WIRING BOARD UNIT AND METHOD FOR DESIGNING THE SAME

Final Rejection §102§103
Filed
Mar 20, 2024
Priority
Sep 22, 2021 — JP 2021-153745 +4 more
Examiner
SAWYER, STEVEN T
Art Unit
2847
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Toppan Holdings Inc.
OA Round
2 (Final)
72%
Grant Probability
Favorable
3-4
OA Rounds
1m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 72% — above average
72%
Career Allowance Rate
748 granted / 1035 resolved
+4.3% vs TC avg
Strong +31% interview lift
Without
With
+30.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
39 currently pending
Career history
1071
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
95.0%
+55.0% vs TC avg
§102
3.2%
-36.8% vs TC avg
§112
1.1%
-38.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1035 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-3, 8-11 and 16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liou et al. (US PG. Pub. 2016/0196986). Regarding claim 1 – Liou teaches a wiring board unit (fig. 2, 200), comprising: a first wiring board (202 [paragraph 0030] Liou states, “printed circuit board 202”) and a second wiring board (204 and also fig. 1, 100 [paragraph 0029] Liou states, “the package substrate 204 is the package substrate 100 illustrated in FIG. 1”) bonded (bonded through solder balls 220) to the first wiring board (202), a semiconductor element (206 [paragraph 0028] Liou states, “integrated circuit 206”) being resin-sealed (208 [paragraph 0028] Liou states, “encapsulation layer 208 includes an epoxy resin”) on a first surface (top surface) of the second wiring board (204) opposite to a surface (bottom surface) for bonding with the first wiring board (202), wherein a tensile strength ([paragraph 0019] Liou states, “the first additional layer 106 or the second additional layer 108 has a tensile strength within a range of 50 MPa to 150 MPa”) of an insulating resin material (fig. 1, 106 & fig. 2, 212) used for the second wiring board (fig. 1, 100 & fig. 2, 204) and a width ([paragraph 0022] Liou states, “line widths of circuit patterns formed on surfaces of the layers of the package substrate 100 are within a range of 6 microns to 25 microns”) of a Cu pattern (fig. 2, 216 [paragraph 0030 & 0033] Liou states, “circuit features 216…the circuit features are formed from copper”) formed on the first surface give a value less than 0.5 when substituted in Formula 1 below; [Formula 1] 1/(1+Exp(-A)) ... (1) A = -15.45 - 0.1654 x Tensile strength + 11.31 x log (Cu pattern width), wherein the tensile strength is from 135 MPa to 170 MPa (In the instant application Applicant specifies value ranges of tensile strength 135 MPa-170MPa (as claimed) and CU pattern width being 20-2000um (defined in specification), Liou teaches values within these ranges as quoted above and will therefore meet the less than .5 range of the formula above and would reasonably be considered to have the same properties, i.e. no cracking). Regarding claim 2 – Liou teaches the wiring board unit of claim 1, wherein the tensile strength ([paragraph 0019] Liou states, “the first additional layer 106 or the second additional layer 108 has a tensile strength within a range of 50 MPa to 150 MPa”) of the insulating resin material (fig. 1, 106) used for the second wiring board (100 & fig. 2, 204) and the width ([paragraph 0022] Liou states, “line widths of circuit patterns formed on surfaces of the layers of the package substrate 100 are within a range of 6 microns to 25 microns”) of the Cu pattern (fig. 2, 216 [paragraph 0030 & 0033] Liou states, “circuit features 216…the circuit features are formed from copper”) formed on the first surface (top surface of second wiring board 100 & fig. 2, 204) give a value of 0.1 or less when substituted in the Formula 1 (Applicant specifies value ranges of tensile strength of 135MPa-170MPa (as claimed) and CU pattern width 20-2000um (defined in specification), Liou teaches values within these ranges as quoted above and will therefore meet the 0.1 or less range of the formula above). Regarding claim 3 – Liou teaches the wiring board unit of claim 1, where in the second wiring board (figs. 1 & 2, 100 & 204) is a multilayer wiring board (figures 1 and 2 show a multilayer wiring board comprised of layers 106, 112 & 108 of figure 1 and 212, 210 & 214 of figure 2). Regarding claim 8 – Liou teaches a method of designing a wiring board unit (fig. 2, 200) including a first wiring board (202 [paragraph 0030] Liou states, “printed circuit board 202”) and a second wiring board (204 and also fig. 1, 100 [paragraph 0029] Liou states, “the package substrate 204 is the package substrate 100 illustrated in FIG. 1”) bonded (bonded through solder balls 220) to the first wiring board (202), a semiconductor element (206 [paragraph 0028] Liou states, “integrated circuit 206”) being resin-sealed (208 [paragraph 0028] Liou states, “encapsulation layer 208 includes an epoxy resin”) on a first surface (top surface) of the second wiring board (204) opposite to a surface (bottom surface) for bonding with the first wiring board (202), the method including setting a tensile strength ([paragraph 0019] Liou states, “the first additional layer 106 or the second additional layer 108 has a tensile strength within a range of 50 MPa to 150 MPa”) of an insulating resin material (fig. 1, 106 & fig. 2, 212) used for the second wiring board (fig. 1, 100 & fig. 2, 204) and a width ([paragraph 0022] Liou states, “line widths of circuit patterns formed on surfaces of the layers of the package substrate 100 are within a range of 6 microns to 25 microns”) of a Cu pattern (fig. 2, 216 [paragraph 0030 & 0033] Liou states, “circuit features 216…the circuit features are formed from copper”) formed on the first surface (top surface of second wiring board 204) so that a value less than 0.5 is obtained when substituted in Formula 1 below; [Formula 1] 1/(1+Exp(-A)) ... (1) A = -15.45 - 0.1654 x Tensile strength + 11.31 x log (Cu pattern width), wherein the tensile strength is from 135 MPa to 170 MPa (In the instant application Applicant specifies value ranges of tensile strength 135 MPa-170MPa (as claimed) and CU pattern width being 20-2000um (defined in specification), Liou teaches values within these ranges as quoted above and will therefore meet the less than .5 range of the formula above and would reasonably be considered to have the same properties, i.e. no cracking). Regarding claim 9 – Liou teaches a wiring board unit (fig. 2, 200), comprising: a first wiring board (202 [paragraph 0030] Liou states, “printed circuit board 202”) and a second wiring board (204 and also fig. 1, 100 [paragraph 0029] Liou states, “the package substrate 204 is the package substrate 100 illustrated in FIG. 1”) bonded (bonded through solder balls 220) to the first wiring board (202), a semiconductor element (206 [paragraph 0028] Liou states, “integrated circuit 206”) being resin-sealed (208 [paragraph 0028] Liou states, “encapsulation layer 208 includes an epoxy resin”) on a first surface (top surface) of the second wiring board (204) opposite to a surface (bottom surface) for bonding with the first wiring board (202), wherein a tensile strength ([paragraph 0019] Liou states, “the first additional layer 106 or the second additional layer 108 has a tensile strength within a range of 50 MPa to 150 MPa”) of an insulating resin material (fig. 1, 106 & fig. 2, 212) used for the second wiring board (fig. 1, 100 & fig. 2, 204) and a width ([paragraph 0022] Liou states, “line widths of circuit patterns formed on surfaces of the layers of the package substrate 100 are within a range of 6 microns to 25 microns”) of a Cu pattern (fig. 2, 216 [paragraph 0030 & 0033] Liou states, “circuit features 216…the circuit features are formed from copper”) formed on the first surface give a value less than 0.5 when substituted in Formula 2 below; [Formula 2] 1/(1+Exp(-A)) ... (2) A = 0.227 - 0.1619 x Tensile strength + 6.648 x log (Cu pattern width), wherein the tensile strength is from 135 MPa to 170 MPa (In the instant application Applicant specifies value ranges of tensile strength 135 MPa-170MPa (as claimed) and CU pattern width being 20-2000um (defined in specification), Liou teaches values within these ranges as quoted above and will therefore meet the less than .5 range of the formula above and would reasonably be considered to have the same properties, i.e. no cracking). Regarding claim 10 – Liou teaches the wiring board unit of claim 9, wherein the tensile strength ([paragraph 0019] Liou states, “the first additional layer 106 or the second additional layer 108 has a tensile strength within a range of 50 MPa to 150 MPa”) of the insulating resin material (fig. 1, 106) used for the second wiring board (100 & fig. 2, 204) and the width ([paragraph 0022] Liou states, “line widths of circuit patterns formed on surfaces of the layers of the package substrate 100 are within a range of 6 microns to 25 microns”) of the Cu pattern (fig. 2, 216 [paragraph 0030 & 0033] Liou states, “circuit features 216…the circuit features are formed from copper”) formed on the first surface (top surface of second wiring board 100 & fig. 2, 204) give a value of 0.1 or less when substituted in the Formula 2 (Applicant specifies value ranges of tensile strength of 135MPa-170MPa (as claimed) and CU pattern width 20-2000um (defined in specification), Liou teaches values within these ranges as quoted above and will therefore meet the 0.1 or less range of the formula above). Regarding claim 11 – Liou teaches the wiring board unit of claim 9, where in the second wiring board (figs. 1 & 2, 100 & 204) is a multilayer wiring board (figures 1 and 2 show a multilayer wiring board comprised of layers 106, 112 & 108 of figure 1 and 212, 210 & 214 of figure 2). Regarding claim 16 – Liou teaches a method of designing a wiring board unit (fig. 2, 200) including a first wiring board (202 [paragraph 0030] Liou states, “printed circuit board 202”) and a second wiring board (204 and also fig. 1, 100 [paragraph 0029] Liou states, “the package substrate 204 is the package substrate 100 illustrated in FIG. 1”) bonded (bonded through solder balls 220) to the first wiring board (202), a semiconductor element (206 [paragraph 0028] Liou states, “integrated circuit 206”) being resin-sealed (208 [paragraph 0028] Liou states, “encapsulation layer 208 includes an epoxy resin”) on a first surface (top surface) of the second wiring board (204) opposite to a surface (bottom surface) for bonding with the first wiring board (202), the method including setting a tensile strength ([paragraph 0019] Liou states, “the first additional layer 106 or the second additional layer 108 has a tensile strength within a range of 50 MPa to 150 MPa”) of an insulating resin material (fig. 1, 106 & fig. 2, 212) used for the second wiring board (fig. 1, 100 & fig. 2, 204) and a width ([paragraph 0022] Liou states, “line widths of circuit patterns formed on surfaces of the layers of the package substrate 100 are within a range of 6 microns to 25 microns”) of a Cu pattern (fig. 2, 216 [paragraph 0030 & 0033] Liou states, “circuit features 216…the circuit features are formed from copper”) formed on the first surface (top surface of second wiring board 204) so that a value less than 0.5 is obtained when substituted in Formula 2 below; [Formula 2] 1/(1+Exp(-A)) ... (2) A = 0.227 - 0.1619 x Tensile strength + 6.648 x log (Cu pattern width), wherein the tensile strength is from 135 MPa to 170 MPa (In the instant application Applicant specifies value ranges of tensile strength 135 MPa-170MPa (as claimed) and CU pattern width being 20-2000um (defined in specification), Liou teaches values within these ranges as quoted above and will therefore meet the less than .5 range of the formula above and would reasonably be considered to have the same properties, i.e. no cracking). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 4 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liou et al. Regarding claim 4 – Liou teaches the wiring board unit of claim 3, but fails to teach wherein the multilayer wiring board is formed by SAP or a damascene process. In accordance to MPEP 2113, the method of forming the device is not germane to the issue of patentability of the device itself. Therefore, this limitation has not been given patentable weight. Please note that even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product, i.e. “the multilayer wiring board”, does not depend on its method of production, i.e. “formed by SAP or a damascene process”. In re Thorpe, 227 USPQ 964, 966 (Federal Circuit 1985). Regarding claim 12 – Liou teaches the wiring board unit of claim 11, but fails to teach wherein the multilayer wiring board is formed by SAP or a damascene process. In accordance to MPEP 2113, the method of forming the device is not germane to the issue of patentability of the device itself. Therefore, this limitation has not been given patentable weight. Please note that even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product, i.e. “the multilayer wiring board”, does not depend on its method of production, i.e. “formed by SAP or a damascene process”. In re Thorpe, 227 USPQ 964, 966 (Federal Circuit 1985). Claim(s) 5-7, 13-15 & 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liou et al. as applied to claim 1, 2, 3, 4 and 10 above, and further in view of Shimizu et al. (US PG. Pub. 2018/0166372). Regarding claim 5 – Liou teaches the wiring board unit of claim 1, but fails to teach wherein the insulating resin material of the second wiring board is a photosensitive insulating resin. Shimizu teaches a wiring board unit (fig. 3, 100) wherein an insulating resin material (61, 63 & 65) of a second wiring board (12) is a photosensitive insulating resin ([paragraph 0045] Shimizu states, “A photosensitive insulative resin, the main component of which is a phenol-based resin, a polyimide-based resin, or the like, for example, may be used as the material of the insulating layers 61, 63, 65”). It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the wiring board unit having a second wiring board with an insulating resin material as taught by Liou with the insulating resin material of the second wiring board being a photosensitive insulating resin as taught by Shimizu because photolithography allows for direct and precision patterning as well as high-density interconnects for miniaturization. Regarding claim 6 – Liou teaches the wiring board unit of claim 3, but fails to teach wherein the insulating resin material of the second wiring board is a photosensitive insulating resin. Shimizu teaches a wiring board unit (fig. 3, 100) wherein an insulating resin material (61, 63 & 65) of a second wiring board (12) is a photosensitive insulating resin ([paragraph 0045] Shimizu states, “A photosensitive insulative resin, the main component of which is a phenol-based resin, a polyimide-based resin, or the like, for example, may be used as the material of the insulating layers 61, 63, 65”). It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the wiring board unit having a second wiring board with an insulating resin material as taught by Liou with the insulating resin material of the second wiring board being a photosensitive insulating resin as taught by Shimizu because photolithography allows for direct and precision patterning as well as high-density interconnects for miniaturization. Regarding claim 7 – Liou teaches the wiring board unit of claim 4, but fails to teach wherein the insulating resin material of the second wiring board is a photosensitive insulating resin. Shimizu teaches a wiring board unit (fig. 3, 100) wherein an insulating resin material (61, 63 & 65) of a second wiring board (12) is a photosensitive insulating resin ([paragraph 0045] Shimizu states, “A photosensitive insulative resin, the main component of which is a phenol-based resin, a polyimide-based resin, or the like, for example, may be used as the material of the insulating layers 61, 63, 65”). It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the wiring board unit having a second wiring board with an insulating resin material as taught by Liou with the insulating resin material of the second wiring board being a photosensitive insulating resin as taught by Shimizu because photolithography allows for direct and precision patterning as well as high-density interconnects for miniaturization. Regarding claim 13 – Liou teaches the wiring board unit of claim 9, but fails to teach wherein the insulating resin material of the second wiring board is a photosensitive insulating resin. Shimizu teaches a wiring board unit (fig. 3, 100) wherein an insulating resin material (61, 63 & 65) of a second wiring board (12) is a photosensitive insulating resin ([paragraph 0045] Shimizu states, “A photosensitive insulative resin, the main component of which is a phenol-based resin, a polyimide-based resin, or the like, for example, may be used as the material of the insulating layers 61, 63, 65”). It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the wiring board unit having a second wiring board with an insulating resin material as taught by Liou with the insulating resin material of the second wiring board being a photosensitive insulating resin as taught by Shimizu because photolithography allows for direct and precision patterning as well as high-density interconnects for miniaturization. Regarding claim 14 – Liou teaches the wiring board unit of claim 11, but fails to teach wherein the insulating resin material of the second wiring board is a photosensitive insulating resin. Shimizu teaches a wiring board unit (fig. 3, 100) wherein an insulating resin material (61, 63 & 65) of a second wiring board (12) is a photosensitive insulating resin ([paragraph 0045] Shimizu states, “A photosensitive insulative resin, the main component of which is a phenol-based resin, a polyimide-based resin, or the like, for example, may be used as the material of the insulating layers 61, 63, 65”). It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the wiring board unit having a second wiring board with an insulating resin material as taught by Liou with the insulating resin material of the second wiring board being a photosensitive insulating resin as taught by Shimizu because photolithography allows for direct and precision patterning as well as high-density interconnects for miniaturization. Regarding claim 15 – Liou teaches the wiring board unit of claim 12, but fails to teach wherein the insulating resin material of the second wiring board is a photosensitive insulating resin. Shimizu teaches a wiring board unit (fig. 3, 100) wherein an insulating resin material (61, 63 & 65) of a second wiring board (12) is a photosensitive insulating resin ([paragraph 0045] Shimizu states, “A photosensitive insulative resin, the main component of which is a phenol-based resin, a polyimide-based resin, or the like, for example, may be used as the material of the insulating layers 61, 63, 65”). It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the wiring board unit having a second wiring board with an insulating resin material as taught by Liou with the insulating resin material of the second wiring board being a photosensitive insulating resin as taught by Shimizu because photolithography allows for direct and precision patterning as well as high-density interconnects for miniaturization. Regarding claim 17 – Liou teaches the wiring board unit of claim 2, but fails to teach wherein the insulating resin material of the second wiring board is a photosensitive insulating resin. Shimizu teaches a wiring board unit (fig. 3, 100) wherein an insulating resin material (61, 63 & 65) of a second wiring board (12) is a photosensitive insulating resin ([paragraph 0045] Shimizu states, “A photosensitive insulative resin, the main component of which is a phenol-based resin, a polyimide-based resin, or the like, for example, may be used as the material of the insulating layers 61, 63, 65”). It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the wiring board unit having a second wiring board with an insulating resin material as taught by Liou with the insulating resin material of the second wiring board being a photosensitive insulating resin as taught by Shimizu because photolithography allows for direct and precision patterning as well as high-density interconnects for miniaturization. Regarding claim 18 – Liou teaches the wiring board unit of claim 10, but fails to teach wherein the insulating resin material of the second wiring board is a photosensitive insulating resin. Shimizu teaches a wiring board unit (fig. 3, 100) wherein an insulating resin material (61, 63 & 65) of a second wiring board (12) is a photosensitive insulating resin ([paragraph 0045] Shimizu states, “A photosensitive insulative resin, the main component of which is a phenol-based resin, a polyimide-based resin, or the like, for example, may be used as the material of the insulating layers 61, 63, 65”). It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the wiring board unit having a second wiring board with an insulating resin material as taught by Liou with the insulating resin material of the second wiring board being a photosensitive insulating resin as taught by Shimizu because photolithography allows for direct and precision patterning as well as high-density interconnects for miniaturization. Response to Arguments Applicant’s arguments with respect to claim(s) 1-18 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN T SAWYER whose telephone number is (571)270-5469. The examiner can normally be reached M-F 8:30 am - 5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at 5712722342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /STEVEN T SAWYER/Primary Examiner, Art Unit 2847
Read full office action

Prosecution Timeline

Mar 20, 2024
Application Filed
Dec 01, 2025
Non-Final Rejection mailed — §102, §103
Apr 30, 2026
Applicant Interview (Telephonic)
May 01, 2026
Examiner Interview Summary
May 11, 2026
Response Filed
Jun 03, 2026
Final Rejection mailed — §102, §103
Jul 13, 2026
Applicant Interview (Telephonic)
Jul 14, 2026
Examiner Interview Summary

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Prosecution Projections

3-4
Expected OA Rounds
72%
Grant Probability
99%
With Interview (+30.7%)
2y 5m (~1m remaining)
Median Time to Grant
Moderate
PTA Risk
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