DETAILED ACTION
This office action is in response to the application filed on 03/20/2024.
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03/20/2024 and 04/15/2024 has been considered by the examiner.
Election/Restrictions
Claims 17-19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected group, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 02/23/2026.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in claims 6 and 10. Therefore, the “a portion parallel to the top surface which connects to a region of one of the first bus bar and the second bus bar that is not the first planar region or the second planar region” and claim 10 limitations must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claims 7 and 10 are objected to because of the following informalities: Claim 7 lines 4 “and second planar” should be “and the second planar”. Claim 10 “a positive DC terminals of a power module or to a positive terminal of a capacitor module… connected to a negative DC terminals of a power module or to a negative terminal of a capacitor module” this should be “the positive DC terminals of the power modules or to a positive terminal of the capacitor modules… connected to the negative DC terminals of the power modules or to the negative terminal of the capacitor modules”. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1-4, 7, 11-13 and 16 is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Lei US 2017/0033704 in view of Ugare US 20250055385.
Regarding Claim 1, Lei teaches (Figures 1-10) a three-phase power electronics module, comprising: three power modules (122-126, Fig. 3) arranged in a row, each module having a positive DC terminal, a negative DC terminal (162 and 164, fig. 5), and an AC terminal (166) and configured to convert DC electrical power delivered via the two DC terminals into AC electrical power at the AC terminal; two capacitor modules (fig. 7, 200), each capacitor module having a positive terminal and a negative terminal (par. 46); a first bus bar (see fig. 8, connected to 162), having a first planar region (169), electrically connecting the positive DC terminals of the power modules and the positive terminals of the capacitor modules (par. 44-48); and a second bus bar (220), having a second planar region (with 222) overlapping and spaced apart from the first planar region, electrically connecting the negative DC terminals of the power modules and the negative terminals of the capacitor modules (see figs. 7-8, par. 44-48). (For example: Par. 35-48)
Lei does not teach two capacitor modules interspersed between the power modules.
Ugare teaches (Figure 6) two capacitor modules (603 and 606) interspersed between the power modules (at 630). (For Example: Par. 64-70)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Lei to include two capacitor modules interspersed between the power modules as taught by Chen to reduce space in the circuit.
Regarding Claim 2, Lei teaches (Figures 1-10) further comprising a third capacitor module (200 of 126) at one end of the three power modules (122-126), the third capacitor module having a positive terminal electrically connected to the first bus bar and a negative terminal electrically connected to the second bus bar (see fig. 5, 162-164). (For example: Par. 35-48)
Regarding Claim 3, Lei teaches (Figures 1-10) the module.
Lei does not teach further comprising an insulator between the first planar region and the second planar region.
Ugare teaches (Figure 6) an insulator (627) between the first planar region and the second planar region. (For Example: Par. 67)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Lei to include two capacitor modules interspersed between the power modules as taught by Chen to improve conduction is the system.
Regarding Claim 4, Lei teaches (Figures 1-10) wherein: the DC terminals of the power modules and the terminals of the capacitor modules (see fig. 7-8, 162-164) extend from a top surface of the power electronics module (with 224); and the first planar region and second planar surface are parallel to the top surface (see fig. 7, with 220). (For example: Par. 35-48)
Regarding Claim 7, Lei teaches (Figures 1-10) wherein: the DC terminals of the power modules (162-164) and the terminals of the capacitor modules (at 226 and 228) extend from a top surface of the power electronics module (Fig. 8-9); and the first planar surface and second planar surface are perpendicular to the top surface (see figs. 7-9 with 222 and 169). (For example: Par. 35-48)
Regarding Claim 11, Lei teaches (Figures 1-10) a three-phase power electronics module (at fig. 2), comprising: three power modules arranged in a row (122-126), each module having a positive DC terminal (162), a negative DC terminal (164), and an AC terminal (164) and configured to convert DC electrical power delivered via the two DC terminals into AC electrical power at the AC terminal; and two capacitor modules (200), each capacitor module having a positive terminal and a negative terminal (at 214 and 216), wherein the positive terminal of each capacitor module extends between and is electrically connected with the positive DC terminals of adjacent power modules (see fig. 7); and the negative terminal of each capacitor module extends between and is electrically connected with the negative DC terminals of adjacent power modules (see fig.7). (For example: Par. 35-48)
Lei does not teach two capacitor modules interspersed between the power modules.
Ugare teaches (Figure 6) two capacitor modules (603 and 606) interspersed between the power modules (at 630). (For Example: Par. 64-70)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Lei to include two capacitor modules interspersed between the power modules as taught by Chen to reduce space in the circuit.
Regarding Claim 12, Lei teaches (Figures 1-10) wherein: each power module (Fig. 5-7) includes a housing (132) defining two slots each providing access to one of the two DC terminals (at 162-163); and the AC terminal extends through the housing (166). (For example: Par. 35-48)
Regarding Claim 13, Lei teaches (Figures 1-10) wherein: each of the capacitor modules (Fig. 7, 200) includes a housing which abuts (with 228) the over-molded housing of an adjacent power modules (210); and the positive terminals and the negative terminals of each of the capacitor modules extend into the slots of the adjacent power modules (they are connected with 220). (For example: Par. 35-48)
Regarding Claim 16, Lei teaches (Figures 1-10) wherein each of the power modules further includes a set of signal terminals extending through the respective housing (Fig. 5, 168-170). (For example: Par. 35-48)
Claims 5-6 is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Lei US 2017/0033704 in view of Ugare US 20250055385 and further in view of Jakobi US 2024/0322697.
Regarding Claim 5, Lei teaches (Figures 1-10) module.
Lei does not teach wherein one of the first bus bar and the second bus bar has a stepped profile.
Jakobi teaches (Figure 1a) wherein one of the first bus bar and the second bus bar has a stepped profile (dc+). (For Example: Par. 24-33)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Lei to include wherein one of the first bus bar and the second bus bar has a stepped profile as taught by Jakobi to reduce the stray inductance of the power module.
Regarding Claim 6, Lei teaches (Figures 1-10) the modules.
Lei does not teach wherein one of the positive DC terminals and the negative DC terminals extends farther from the top surface than the other of the positive DC terminals and the negative DC terminals and includes a portion parallel to the top surface which connects to a region of one of the first bus bar and the second bus bar that is not the first planar region or the second planar region.
Jakobi teaches (Figures 1a and 1b) wherein one of the positive DC terminals and the negative DC terminals (DC+) extends farther from the top surface (100) than the other of the positive DC terminals and the negative DC terminals (dc-) and includes a portion parallel to the top surface (112) which connects to a region of one (114) of the first bus bar and the second bus bar that is not the first planar region or the second planar region (at 162). (For Example: Par. 24-33)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Lei to include wherein one of the positive DC terminals and the negative DC terminals extends farther from the top surface than the other of the positive DC terminals and the negative DC terminals and includes a portion parallel to the top surface which connects to a region of one of the first bus bar and the second bus bar that is not the first planar region or the second planar region, as taught by Jakobi to reduce the stray inductance of the power module.
Claim 8-10 is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Lei US 2017/0033704 in view of Ugare US 20250055385 and further in view of Esmaili US 2010/0089641.
Regarding Claim 8, Lei teaches (Figures 1-10) wherein: each of the positive terminal and the negative terminal of each of the capacitor modules (214 +/-) includes a tab (228) which extends parallel to the top surface (210). (For example: Par. 35-48)
Lei does not teach the first bus bar includes a plurality of tabs extending from the first planar region parallel to the top surface and electrically connected to the tabs of respective positive terminals; and the second bus bar includes a plurality of tabs extending from the second planar region parallel to the top surface and electrically connected to the tabs of respective negative terminals.
Esmaili teaches (Figures 2-4) the first bus bar (52) includes a plurality of tabs extending from the first planar region parallel to the top surface (at 50 see fig. 2, with 70-78) and electrically connected to the tabs of respective positive terminals (fig. 3, 162); and the second bus bar (53) includes a plurality of tabs extending from the second planar region parallel to the top surface (at 52, see fig. 2 with 70-78) and electrically connected to the tabs of respective negative terminals (164, Fig. 3). (For Example: Par. 19-23)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Lei to include the first bus bar includes a plurality of tabs extending from the first planar region parallel to the top surface and electrically connected to the tabs of respective positive terminals; and the second bus bar includes a plurality of tabs extending from the second planar region parallel to the top surface and electrically connected to the tabs of respective negative terminals, as taught by Esmaili to provide a low inductance busbar system to reduce voltage spikes.
Regarding Claim 9, Lei teaches (Figures 1-10) wherein: each of the positive DC terminal and the negative DC terminal (162-164) of each of the power modules includes a tab which extends parallel to the top surface (see fig. 5 and 8, with 165 and 163). (For example: Par. 35-48)
Lei does not teach the first bus bar includes a plurality of tabs extending from the first planar region parallel to the top surface and electrically connected to the tabs of respective positive DC terminals; and the second bus bar includes a plurality of tabs extending from the second planar region parallel to the top surface and electrically connected to the tabs of respective negative DC terminals.
Esmaili teaches (Figures 2-4) the first bus bar (52) includes a plurality of tabs extending from the first planar region parallel to the top surface (at 50 see fig. 2, with 70-78) and electrically connected to the tabs of respective positive terminals (fig. 3, 162); and the second bus bar (53) includes a plurality of tabs extending from the second planar region parallel to the top surface (at 52, see fig. 2 with 70-78) and electrically connected to the tabs of respective negative terminals (164, Fig. 3). (For Example: Par. 19-23)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Lei to include the first bus bar includes a plurality of tabs extending from the first planar region parallel to the top surface and electrically connected to the tabs of respective positive terminals; and the second bus bar includes a plurality of tabs extending from the second planar region parallel to the top surface and electrically connected to the tabs of respective negative terminals, as taught by Esmaili to provide a low inductance busbar system to reduce voltage spikes.
Regarding Claim 10, Lei teaches (Figures 1-10) the modules.
Lei does not teach wherein: the first bus bar includes a plurality of first tabs extending perpendicular to the top surface and perpendicular to the first planar region, each first tab electrically connected to a positive DC terminals of a power module or to a positive terminal of a capacitor module; and the second bus bar includes a plurality of second tabs extending perpendicular to the top surface and perpendicular to the second planar region, each second tab electrically connected to a negative DC terminals of a power module or to a negative terminal of a capacitor module.
Esmaili teaches (Figures 2-4) wherein: the first bus bar (52) includes a plurality of first tabs extending perpendicular to the top surface and perpendicular to the first planar region (see fig. 2, tabs 70-73), each first tab electrically connected to a positive DC terminals of a power module or to a positive terminal of a capacitor module (see fig. 3, 162 and 82); and the second bus bar (53) includes a plurality of second tabs extending perpendicular to the top surface (164) and perpendicular to the second planar region (see fig. 2, 74-78), each second tab electrically connected to a negative DC terminals of a power module or to a negative terminal of a capacitor module (see fig. 3, 164 and 78). (For Example: Par. 19-23)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Lei to include wherein: the first bus bar includes a plurality of first tabs extending perpendicular to the top surface and perpendicular to the first planar region, each first tab electrically connected to a positive DC terminals of a power module or to a positive terminal of a capacitor module; and the second bus bar includes a plurality of second tabs extending perpendicular to the top surface and perpendicular to the second planar region, each second tab electrically connected to a negative DC terminals of a power module or to a negative terminal of a capacitor module, as taught by Esmaili to provide a low inductance busbar system to reduce voltage spikes.
Allowable Subject Matter
Claim 14-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Reasons for Indicating Allowable Subject Matter
The following is an examiner’s statement of reasons for indicating Allowable Subject Matter:
Claim 14; prior art of record fails to disclose either by itself or in combination: “…further comprising a third capacitor module adjacent to an outside power module of the three power modules, wherein: the third capacitor module includes an over-molded housing which abuts the over-molded housing of outside power module; a positive terminal of the third capacitor module extends into one of the slots of the outside power module and is electrically connected with the positive DC terminal of the outside power module; and a negative terminal of the third capacitor module extends into the other slot of the outside power module and is electrically connected with the negative DC terminal of the outside power module”.
These features taken alone or in combination are neither disclosed nor suggested by the prior art of record.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUSTAVO A ROSARIO-BENITEZ whose telephone number is (571)270-7888. The examiner can normally be reached M-F 9AM-5PM.
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/GUSTAVO A ROSARIO-BENITEZ/ Primary Examiner, Art Unit 2838