Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 08/10/26 has been entered.
Response to Arguments
Applicant's arguments filed 08/10/26 directed towards claims 1-2 and 10-11 have been fully considered but are moot because they do not apply the rejection used below.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim (s) 1-2 and 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ryutaro (WO 2022018868 A1; published on 01/27/2022).
Regarding claim 1, Ryutaro discloses a semiconductor apparatus (Fig.9) comprising: an insulating substrate (2) including an insulating layer (2) including a first main surface (top of 2), and a circuit pattern (3) disposed directly on the first main surface and including a first portion (see recess part of 3) ; and an electrode (10) including a second portion (10a) bonded to the first portion, wherein bonding between the first portion and the second portion is ultrasonic bonding (10a is ultrasonic bonded to 3), one of the first portion and the second portion is fitted in a recess (see recess 5 in 3) of the other of the first portion and the second portion in a planar view of the first main surface (top of 2) , a step of the recess extends in a direction (see recess 5 extending in a thickness direction of 3) perpendicular to a direction of ultrasonic vibration applied for the ultrasonic bonding ( direction of vibration is left and right of Fig.9 which involves 10a rubbing 3) , and both ends of the recess in the direction of the ultrasonic vibration are open (see ends of 5 open on both sides of 10a).
Regarding claim 2, Ryutaro discloses wherein the first portion has the recess (see 3 having a recess 5), and the second portion is fitted in the recess (see 10a fitted into recess 5).
Regarding claim 11, Ryutaro discloses, in Fig.9, method of manufacturing a semiconductor apparatus, comprising: preparing an insulating substrate (2) and an electrode (10), the insulating substrate including an insulating layer (2) and a circuit pattern (3) disposed directly on a first main surface of the insulating layer and including a first portion(5), the electrode including a second portion (10a) ; fitting one of the first portion and the second portion (10a) into a recess (5) of the other of the first portion and the second portion; and ultrasonically bonding the first portion and the second portion (10a and 3 are ultrasonic bonded), wherein in a planar view of the first main surface, a step (thickness direction of 5) of the recess extends in a direction perpendicular to a direction of ultrasonic vibration (left right direction) applied for the ultrasonic bonding, and both ends of the recess in the direction of the ultrasonic vibration are open (see ends of 5 open on both ends outside of 10a).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 10 are rejected under 35 U.S.C. 103 as being unpatentable over Ryutaro (WO 2022018868 A1; published on 01/27/2022) as applied to claim 1 above, and further in view of Yutaka et al. (JP 2014056917 A1) hereinafter Yutaka
Regarding claim 10, Ryutaro discloses the insulating layer includes a second main surface opposite to the first main surface (see bottom side of 2).
Ryutaro is silent with respect to the insulating substrate includes a heat dissipation plate disposed on the second main surface.
Yutaka discloses the insulating substrate includes a heat dissipation plate disposed on the second main surface (see 6 disposed on bottom of surface of 51;Fig.5).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention to use the teachings of Yutaka to modify the device of Ryutaro in order to perform heat dissipation to prevent damage to the device.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETE LEE whose telephone number is (571) 270-5921. The examiner can normally be reached on Monday-Friday (2nd & 4th Friday Off). If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Timothy Dole can be reached at (571) 272-2229 The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/PETE T LEE/ Primary Examiner, Art Unit 2847
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