Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of claims 1-3 and 10-11 in the reply filed on 12/19/25 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim (s) 1-3 and 10-11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yutaka et al. (JP 2014056917A) hereinafter Yutaka.
Regarding claim 1, Yutaka discloses, in Fig.5, an insulating substrate (51) including an insulating layer including a first main surface (top surface of 5), and a circuit pattern (52a and 4 ) disposed on the first main surface and including a first portion (4); and an electrode (3) including a second portion (3p) bonded to the first portion, wherein bonding between the first portion and the second portion is ultrasonic bonding ( 3 and 4 are joined together by ultrasonic waves), and one of the first portion and the second portion is fitted in the other of the first portion and the second portion ( see part 3p of 3 fitted into a recess of 4;Fig.5).
Regarding claim 2, Yutaka discloses, in Fig.5, wherein the first portion has a recess, and the second portion is fitted in the recess (see part 3p of 3 fitted into a recess of 4;Fig.5).
Regarding claim 3, Yutaka discloses, in Fig.5, wherein in a planar view of the first main surface, a step of the recess extends in a direction perpendicular to a direction of ultrasonic vibration applied for the ultrasonic bonding ( see vertical up down direction of recess in 4 where the ultrasonic vibration is applied left to right ; see Fig.6a and 6b).
Regarding claim 10, Yutaka discloses, in Fig.5, wherein the insulating layer includes a second main surface (see bottom surface of 51) opposite to the first main surface, and the insulating substrate includes a heat dissipation plate (6) disposed on the second main surface. (see 6 disposed on the bottom surface of 51).
Regarding claim 11, Yutaka discloses preparing an insulating substrate and an electrode (3), the insulating substrate (51) including an insulating layer (52) and a circuit pattern ( 52a and 4) disposed on the insulating layer and including a first portion (4), the electrode including a second portion (3p); fitting one of the first portion (4) and the second portion into the other of the first portion and the second portion (see 3p fitted into the recess of 4); and ultrasonically bonding the first portion and the second portion (3p is ultrasonic bonded to 4 ; see Fig.5 and Fig.6).
Pertinent Art
The prior art made of record and not relied upon is considered pertinent toapplicant's disclosure.
Ogawa (US 20210313253 A1) discloses a power conversion device with bonded electrodes.
Asada (US 2016/0104651 A1) discloses a power semiconductor device.
Spletter et al. (US 5164566) discloses a electroless plating on a solder bump.
The above references are considered of particular relevance to the claimed invention but cannot be considered to teach the limitations or combined to being obvious to a person skilled in the art to disclose the claimed invention.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETE LEE whose telephone number is (571) 270-5921. The examiner can normally be reached on Monday-Friday (2nd & 4th Friday Off). If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Timothy Dole can be reached at (571) 272-2229 The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/PETE T LEE/Primary Examiner, Art Unit 2848