DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Foreign priority is not claimed for this application.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03/20/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, “a power supply input coupled to a second power supply node” from claim 4 and “a power supply input coupled to a third power supply node” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4 and 12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 4, it’s not clear where a power supply input coupled to a second power supply node is in the figures. This makes the claim indefinite as examiner is unsure how these connections are being made. Appropriate correction is required.
Regarding claim 12, it’s not clear where a power supply input coupled to a third power supply node is in the figures. This makes the claim indefinite as examiner is unsure how these connections are made. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 6-7, 17, and 20 is/are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by US 9564874 by Alzaher et al.
Regarding claim 1, Alzaher teaches an amplification circuit (fig. 3) comprising:
an amplifier (308) including an inverting input configured to receive a signal;
an impedance (302, 306) coupled between the inverting input and an output (Vo) of the amplifier; and
a resistive element (aR) including (i) a first terminal coupled to the inverting input and (ii) a second terminal coupled to a reference potential node (ground) for the amplification circuit.
Regarding claim 6, Alzaher teaches the amplification circuit of claim 1, wherein the amplifier further includes a non-inverting input coupled to a voltage reference node (Fig. 3).
Regarding claim 7, Alzaher teaches the amplification circuit of claim 1, wherein the amplifier comprises a class-AB or class-G output stage (Col. 15 lines 60-67 and Col. 16 lines 1-3).
Regarding claim 17, Alzaher teaches a method of wireless communication comprising:
amplifying an input signal via an amplification circuit (Fig. 3) to generate an amplified signal, wherein the amplification circuit comprises (i) an amplifier (308) including an inverting input configured to receive the input signal (Vi);
(ii) an impedance (302, 306) coupled between the inverting input and an output of the amplifier; and
(iii) a resistive element (aR) including a first terminal coupled to the inverting input and including a second terminal coupled to a reference potential node (ground) for the amplification circuit; and
outputting the amplified signal (Vo).
Regarding claim 20, Alzaher teaches the method of claim 17, wherein the amplifier comprises a class-AB or class-G output stage (Col. 15 lines 60-67 and Col. 16 lines 1-3).
Claim(s) 1 5-6, 17, and 19 is/are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by US 20140332670 by Tateiwa.
Regarding claim 1, Tateiwa teaches an amplification circuit (fig. 5) comprising:
an amplifier (62) including an inverting input (64a) configured to receive a signal;
an impedance (68, 72) coupled between the inverting input and an output (66) of the amplifier; and
a resistive element (80) including (i) a first terminal coupled to the inverting input and (ii) a second terminal coupled to a reference potential node (ground) for the amplification circuit.
Regarding claim 5, Tateiwa teaches the amplification circuit of claim 1, further comprising a capacitive element (82) coupled in series between the second terminal of the resistive element (80) and the reference potential node (ground).
Regarding claim 6, Tateiwa teaches the amplification circuit of claim 1, wherein the amplifier further includes a non-inverting input (64b) coupled to a voltage reference node (Vpd).
Regarding claim 17, Tateiwa teaches a method of wireless communication comprising:
amplifying an input signal via an amplification circuit (Fig. 5) to generate an amplified signal, wherein the amplification circuit comprises (i) an amplifier (62) including an inverting input configured to receive the input signal;
(ii) an impedance (68, 72) coupled between the inverting input and an output of the amplifier; and
(iii) a resistive element (80) including a first terminal coupled to the inverting input and including a second terminal coupled to a reference potential node (ground) for the amplification circuit; and
outputting the amplified signal (output of 62).
Regarding claim 19, Tateiwa teaches the method of claim 17, wherein the amplification circuit is a transimpedance amplification circuit (Par. 26).
Claim(s) 1, 8-10, 14, and 16-18 is/are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by US 6774725 by Miki et al.
Regarding claim 1, Miki teaches an amplification circuit (Fig. 3) comprising:
an amplifier (CMP) including an inverting input configured to receive a signal (Receives feedback signal);
an impedance (Rb1/Rb2) coupled between the inverting input and an output of the amplifier; and
a resistive element (Rb3) including (i) a first terminal coupled to the inverting input and (ii) a second terminal coupled to a reference potential node (ground) for the amplification circuit.
Regarding claim 8, Miki teaches the amplification circuit of claim 1, wherein the output of the amplifier (CMP) is coupled to a power supply node of another amplifier (HPA).
Regarding claim 9, Miki teaches the amplification circuit of claim 8, wherein the output of the amplifier comprises a power supply voltage (the output of CMP goes through inductor 234 and supplies power to the HPA).
Regarding claim 10, Miki teaches a wireless device comprising:
an amplification circuit (Fig. 3) comprising:
a first amplifier (CMP) including an inverting input configured to receive a signal (receives feedback signal);
an impedance (Rb1/Rb2) coupled between the inverting input and an output of the first amplifier; and
a resistive element (Rb3) including (i) a first terminal coupled to the inverting input and (ii) a second terminal coupled to a reference potential node (ground) for the amplification circuit; and
a second amplifier (HPA) including a first power supply node coupled to an output of the amplification circuit.
Regarding claim 14, Miki teaches the wireless device of claim 10, wherein the first amplifier further includes a non-inverting input coupled to a voltage reference node (Vref).
Regarding claim 16, Miki teaches the wireless device of claim 10, wherein:
the amplification circuit is configured to generate a power supply voltage based on the signal (Col. 8 lines 6-27); and
the output of the amplification circuit comprises the power supply voltage (output of CMP provides a voltage to the power supply node of the HPA).
Regarding claim 17, Miki teaches a method of wireless communication comprising:
amplifying an input signal via an amplification circuit (Fig. 3) to generate an amplified signal, wherein the amplification circuit comprises (i) an amplifier (CMP) including an inverting input configured to receive the input signal;
(ii) an impedance (Rb1/Rb2) coupled between the inverting input and an output of the amplifier; and
(iii) a resistive element (Rb3) including a first terminal coupled to the inverting input and including a second terminal coupled to a reference potential node (ground) for the amplification circuit; and
outputting the amplified signal (output of CMP).
Regarding claim 18, Miki teaches the method of claim 17, further comprising controlling a power supply voltage of another amplifier, based on the amplified signal (Col. 8 lines 6-27; output of CMP is coupled to the power supply node of the HPA).
Claim(s) 1, 6, 8-10, 14, and 16-18 is/are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by US 11705876 by Drogi et al.
Regarding claim 1, Drogi teaches an amplification circuit (Fig. 3a) comprising:
an amplifier (103) including an inverting input configured to receive a signal (Env);
an impedance (111) coupled between the inverting input and an output of the amplifier; and
a resistive element (113) including (i) a first terminal coupled to the inverting input and (ii) a second terminal coupled to a reference potential node (Env) for the amplification circuit.
Regarding claim 6, Drogi teaches the amplification circuit of claim 1, wherein the amplifier further includes a non-inverting input coupled to a voltage reference node (Vref).
Regarding claim 8, Drogi teaches the amplification circuit of claim 1, wherein the output of the amplifier (103) is coupled to a power supply node of another amplifier (51).
Regarding claim 9, Drogi teaches the amplification circuit of claim 8, wherein the output of the amplifier (103) comprises a power supply voltage (the output of 103 goes through inductor 131 and supplies power to 51).
Regarding claim 10, Drogi teaches a wireless device comprising:
an amplification circuit (Fig. 3a) comprising:
a first amplifier (103) including an inverting input configured to receive a signal (Env);
an impedance (111) coupled between the inverting input and an output of the first amplifier; and
a resistive element (113) including (i) a first terminal coupled to the inverting input and (ii) a second terminal coupled to a reference potential node (Env) for the amplification circuit; and
a second amplifier (51) including a first power supply node coupled to an output of the amplification circuit (103).
Regarding claim 14, Drogi teaches the wireless device of claim 10, wherein the first amplifier (103) further includes a non-inverting input coupled to a voltage reference node (Vref).
Regarding claim 16, Drogi teaches the wireless device of claim 10, wherein:
the amplification circuit (103) is configured to generate a power supply voltage based on the signal (Env); and
the output of the amplification circuit comprises the power supply voltage (output of 103 is supplied to 51 through inductor 131).
Regarding claim 17, Drogi teaches a method of wireless communication comprising:
amplifying an input signal via an amplification circuit (Fig. 3a) to generate an amplified signal, wherein the amplification circuit comprises (i) an amplifier (103) including an inverting input configured to receive the input signal;
(ii) an impedance (111) coupled between the inverting input and an output of the amplifier; and
(iii) a resistive element (113) including a first terminal coupled to the inverting input and including a second terminal coupled to a reference potential node (Env) for the amplification circuit; and
outputting the amplified signal (output of 103).
Regarding claim 18, Drogi teaches the method of claim 17, further comprising controlling a power supply voltage of another amplifier, based on the amplified signal (The output of 103 controls the power supply that’s provided to 51).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-3 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 9564874 by Alzaher et al. in view of US 20190199290 by Karmaker et al.
Regarding claim 2, Alzaher teaches the amplification circuit of claim 1, but fails to teach that it further comprises a current source coupled between a first power supply node and the first terminal of the resistive element.
However, Karmaker teaches an amplifier circuit (Fig. 6) with a current source (612) coupled between a first power supply node (Vdd) and the first terminal of the resistive element (602).
It would be obvious to a person of ordinary skill in the art before the effective filing date of the invention to combine the current source of Karmaker with the amplification circuit of Alzaher as the current source provides a biasing current (Par. 47 of Karmaker).
Regarding claim 3, the combination of Alzaher and Karmaker teaches the amplification circuit of claim 2, and while the current source 612 in fig. 6 is not programmable, this is simply a known design choice in the art and one can make the current programmable if they choose to. Fig. 6 of Karmaker shows another current source 426 that is variable.
Claim(s) 2-3 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20140332670 by Tateiwa in view of US 20190199290 by Karmaker et al.
Regarding claim 2, Tateiwa teaches the amplification circuit of claim 1, but fails to teach that it further comprises a current source coupled between a first power supply node and the first terminal of the resistive element.
However, Karmaker teaches an amplifier circuit (Fig. 6) with a current source (612) coupled between a first power supply node (Vdd) and the first terminal of the resistive element (602).
It would be obvious to a person of ordinary skill in the art before the effective filing date of the invention to combine the current source of Karmaker with the amplification circuit of Tateiwa as the current source provides a biasing current (Par. 47).
Regarding claim 3, the combination of Alzaher and Karmaker teaches the amplification circuit of claim 2, and while the current source 612 in fig. 6 is not programmable, this is simply a known design choice in the art and one can make the current programmable if they choose to. Fig. 6 of Karmaker shows another current source 426 that is variable.
Claim(s) 7 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20140332670 by Tateiwa.
Regarding claim 7, Tateiwa teaches the amplification circuit of claim 1, but is silent on the classes of the amplifiers. However, different amplifier classes are well known in the art as shown in the abstract for US 20240410922 by Abouzied.
Regarding claim 20, Tateiwa teaches the amplification circuit of claim 17, but is silent on the classes of the amplifiers. However, different amplifier classes are well known in the art as shown in the abstract for US 20240410922 by Abouzied.
Claim(s) 7, 15, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 11705876 by Drogi et al.
Regarding claim 7, Drogi teaches the amplification circuit of claim 1, but is silent on the class of the amplifier. However, different amplifier classes are well known in the art as shown in the abstract for US 20240410922 by Abouzied.
Regarding claim 15, Drogi teaches the amplification circuit of claim 10, but is silent on the class of the amplifier. However, different amplifier classes are well known in the art as shown in the abstract for US 20240410922 by Abouzied.
Regarding claim 20, Drogi teaches the amplification circuit of claim 17, but is silent on the classes of the amplifiers. However, different amplifier classes are well known in the art as shown in the abstract for US 20240410922 by Abouzied.
Allowable Subject Matter
Claims 11 and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 4 and 12 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NAREH SHAMIRYAN whose telephone number is (703)756-4616. The examiner can normally be reached M-F: 7:00AM-4:00PM PT.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren-Baltzell can be reached at (571) 272-5918. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NAREH SHAMIRYAN/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843
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