DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “first electrode is electrically connected to the first semiconductor layer, and the second electrode is electrically connected to the second semiconductor layer” (claim 13; figures 4+5 show opposite relationship (see specification objection)) must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
Par. 0128 describes first electrode 51 and second electrode 52 as electrically connected to first semiconductor layer 31 and second semiconductor layer 32, respectively, in figures 4 and 5. However, figures 4 and 5, and par. 0129 show and describe 51 connected to 32 and 52 connected to 31. Applicant is advised to clarify/correct the electrode identification and connections to provide consistency throughout specification and figures.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 7 rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. Claim 2 establishes that first grooves and second grooves are present within the first subdielectric layer and second subdielectric layer, respectively. Claim 7 recites that these first and/or second grooves must extend fully or partially through the first subdielectric layer and/or second subdielectric layer, respectively. However, all grooves necessarily extend either fully or partially through their respective subdielectric layer. These two options encompass all possible groove extensions/depths. Therefore, explicitly requiring either full or partial extension of the grooves in claim 7 does not further limit the subject matter of claim 2. Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 11, 13-15 is/are rejected under 35 U.S.C. 102a1/2 as being anticipated by Furuya (US-4464762-A).
Regarding claim 1, Furuya discloses a semiconductor structure (figs. 1-2), comprising: a substrate (substrate 19+20 col. 4 lines 20-35), wherein the substrate comprises a first region, a second region, and a third region disposed between the first region and the second region (19+20 comprises first region 11, second region 13, and third region 12 between 11 and 13, col. 4 lines 10-20); a first reflector structure disposed in the first region of the substrate (first reflector structure 22+29 in 11, col. 4 lines 30-50); a second reflector structure disposed in the second region of the substrate (second reflector structure 24+30 in 13), wherein the first reflector structure and the second reflector structure are disposed on a same side of the substrate (22+29 and 24+30 both on same (top) side of 19+20); and a light-emitting structure disposed in the third region of the substrate (light-emitting structure 16+17+18 in 12, col. 4 lines 20-25), wherein the light-emitting structure is disposed on the same side of the substrate as the first reflector structure (16+17+18 on same (top) side of 19+20 as corrugations in 22+29); wherein each of a reflective surface of the first reflector structure and a reflective surface of the second reflector structure faces a sidewall of the light-emitting structure (innermost corrugation surfaces in 22+29 and 24+30 face sidewall (left/right surface) of 16+17+18, cols. 3+4).
Regarding claim 11, Furuya discloses the semiconductor structure according to claim 1, wherein the light-emitting structure (16+17+18) comprises a first semiconductor layer (18), an active layer (17), and a second semiconductor layer (16) which are sequentially stacked on the substrate; wherein the first semiconductor layer and the second semiconductor layer have opposite conductivity types (18 (n) and 16 (p) have opposite conductivity, col. 5 lines 10-30).
Regarding claim 13, Furuya discloses the semiconductor structure according to claim 11, further comprising: a first electrode and a second electrode (first electrode 15 and second electrode 14, col. 4 lines 10-20, col. 2 line 60 – col. 3 line 10), wherein the first electrode is electrically connected to the first semiconductor layer (15 electrically connected to 18), and the second electrode is electrically connected to the second semiconductor layer (14 electrically connected to 16).
Regarding claim 14, Furuya discloses a semiconductor structure preparation method for preparing a semiconductor structure (figs. 1-2), wherein the semiconductor structure comprises a substrate (substrate 19+20 col. 4 lines 20-35), a first reflector structure disposed in a first region of the substrate (first reflector structure 22+29 in first region 11, col. 4 lines 30-50); a second reflector structure disposed in a second region of the substrate (second reflector structure 24+30 in second region 13); and a light-emitting structure disposed in a third region of the substrate (light-emitting structure 16+17+18 in third region 12, col. 4 lines 20-25); wherein the semiconductor structure preparation method comprises: providing the substrate (19+20 provided), wherein the substrate comprises the first region (11), the second region (13), and the third region disposed between the first region and the second region (12 between 11 and 13); and forming the first reflector structure in the first region of the substrate (22+29 in 11), the second reflector structure in the second region of the substrate (24+30 in 13), and the light-emitting structure in the third region of the substrate respectively (16+17+18 in 12), wherein the first reflector structure, the second reflector structure, and the light-emitting structure are disposed on a same side of the substrate (22+29, 24+30, and 16+17+18 on same (top) side of substrate 19+20), and each of a reflective surface of the first reflector structure and a reflective surface of the second reflector structure faces a sidewall of the light-emitting structure (innermost corrugation surfaces in 22+29 and 24+30 face sidewall (left/right surface) of 16+17+18, cols. 3+4).
Regarding claim 15, Furuya discloses the semiconductor structure preparation method according to claim 14, wherein forming the first reflector structure in the first region of the substrate, the second reflector structure in the second region of the substrate, and the light-emitting structure in the third region of the substrate respectively comprises: forming the light-emitting structure in the third region of the substrate after the first reflector structure is formed in the first region of the substrate and the second reflector structure is formed in the second region of the substrate; or forming the first reflector structure in the first region of the substrate and the second reflector structure in the second region of the substrate separately after the light-emitting structure is formed in the third region of the substrate.
Furuya discloses forming semiconductor heterostructure including light-emitting structure 16+17+18 and then heterostructure mesa in region 12 (col. 5 lines 15-20, col. 6 lines 20-45). Furuya then discloses forming waveguide core layers 22 and 24 and subsequently etching the corrugations forming the reflector structures (col. 7 lines 55-65, col. 9 lines 5-15, col. 9 line 60 – col. 10 line 5).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-3, 6-7, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Furuya in view of Huang (US-20230384610-A1).
Regarding claim 2, Furuya discloses the semiconductor structure according to claim 1, wherein at least one of the first reflector structure or the second reflector structure is a Bragg reflector structure (22+29 and 24+30 corrugations form Bragg reflectors, col. 4 lines 30-50), wherein the first reflector structure comprises a first sub-dielectric layer covering the sidewall of the light-emitting structure (22+29 comprises first sub-dielectric layer 22 covering (left) sidewall of 16+17+18), and the first sub-dielectric layer is provided with a plurality of first grooves uniformly distributed (22 has first grooves (between corrugations) uniformly distributed); and the second reflector structure comprises a second sub-dielectric layer covering the sidewall of the light-emitting structure (24+30 comprises second sub-dielectric layer 24 covering (right) sidewall of 16+17+18), and the second sub-dielectric layer is provided with a plurality of second grooves uniformly distributed (24 has second grooves (between corrugations) uniformly distributed).
Furuya does not disclose a third semiconductor layer prepared in each of the plurality of first grooves, a fourth semiconductor layer prepared in each of the plurality of second grooves.
Huang discloses a vertical grating filter with a dielectric layer with sets of grooves, where a semiconductor grating material/silicon is deposited into the grooves to form Bragg grating ridges (fig. 4 steps 430-435, figs. 5c-d ridges 150, dielectric layer 130, claim 1 “silicon”, 0030, 0045).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use third and fourth semiconductor layers at least in the first and second grooves to provide more flexibility in the wavelength tuning of the Bragg reflectors without being restricted to using the cladding layer 21 material or needing to alter the entire cladding layer 21 (Huang 0030).
Regarding claim 3, modified Furuya discloses the semiconductor structure according to claim 2, wherein each of the plurality of first grooves extends along a first direction (figs. 1+2 first grooves between corrugations 29 extend along first direction (into page in fig. 2)), and the plurality of first grooves are arranged at intervals along a second direction (first grooves arranged at intervals along second direction (left to right in fig. 2)); and each of the plurality of second grooves extends along the first direction (second grooves between corrugations 30 extend along same first direction into page in fig. 2), and the plurality of second grooves are arranged at intervals along the second direction (second grooves arranged at intervals along same second direction (left to right in fig. 2); wherein the second direction is a direction in which the first reflector structure is pointing to the light-emitting structure (left to right direction is direction in which 22+29 pointing to 16+17+18), and the first direction and the second direction are perpendicular to each other (into page in fig. 2 perpendicular to left to right in fig. 2).
Regarding claim 6, modified Furuya discloses the semiconductor structure according to claim 2, wherein each of the first sub-dielectric layer and the second sub-dielectric layer is a single layer of material, wherein a material of the first sub-dielectric layer comprises SiO2 or SiN, and a material of the second sub-dielectric layer comprises SiO2 or SiN (22 and 24 single layers of Si3N4, col. 5 lines 1-10); or the first sub-dielectric layer and the second sub-dielectric layer are each a stacked material layer, and each of the first sub-dielectric layer and the second sub-dielectric layer comprises a plurality of stacked distributed Bragg reflector (DBR) material layers perpendicular to the substrate, wherein a material of the first sub-dielectric layer comprises SiO2 and SiN, and a material of the second sub-dielectric layer comprises SiO2 and SiN.
Regarding claim 7, modified Furuya discloses the semiconductor structure according to claim 2, wherein a first groove of the plurality of first grooves extends through the first sub-dielectric layer or partially extends through the first sub-dielectric layer (annotated fig. 2 first groove 1G partially extends through 22); and/or a second groove of the plurality of second grooves extends through the second sub-dielectric layer or partially extends through the second sub-dielectric layer.
PNG
media_image1.png
478
772
media_image1.png
Greyscale
Annotated fig. 2
Regarding claim 20, Furuya discloses the semiconductor structure preparation method according to claim 14, wherein at least one of the first reflector structure or the second reflector structure is a Bragg reflector structure (22+29 and 24+30 corrugations form Bragg reflectors, col. 4 lines 30-50), wherein the first reflector structure comprises a first sub-dielectric layer covering the sidewall of the light-emitting structure (22+29 comprises first sub-dielectric layer 22 covering (left) sidewall of 16+17+18), and the first sub-dielectric layer is provided with a plurality of first grooves uniformly distributed (22 has first grooves (between corrugations) uniformly distributed); and the second reflector structure comprises a second sub-dielectric layer covering the sidewall of the light-emitting structure (24+30 comprises second sub-dielectric layer 24 covering (right) sidewall of 16+17+18), and the second sub-dielectric layer is provided with a plurality of second grooves uniformly distributed (24 has second grooves (between corrugations) uniformly distributed).
Furuya does not disclose a third semiconductor layer prepared in each of the plurality of first grooves, a fourth semiconductor layer prepared in each of the plurality of second grooves.
Huang discloses a vertical grating filter with a dielectric layer with sets of grooves, where a semiconductor grating material/silicon is deposited into the grooves to form Bragg grating ridges (fig. 4 steps 430-435, figs. 5c-d ridges 150, dielectric layer 130, claim 1 “silicon”, 0030, 0045).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use third and fourth semiconductor layers at least in the first and second grooves to provide more flexibility in the wavelength tuning of the Bragg reflectors without being restricted to using the cladding layer 21 material or needing to alter the entire cladding layer 21 (Huang 0030).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Furuya in view of Huang and Matsui (US-20140269807-A1).
Regarding claim 4, modified Furuya discloses the semiconductor structure according to claim 2.
Modified Furuya does not disclose wherein a number of the plurality of first grooves is less than a number of the plurality of second grooves.
Matsui discloses a DBR laser with a short DBR laser with a short DBR mirror having a smaller number of first grooves and a long DBR mirror having a larger number of second grooves (fig. 11 short DBR mirror 1114 and long DBR mirror 1112, 0102-0103).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a number of the plurality of first grooves is less than a number of the plurality of second grooves (i.e. longer second reflector) to establish a preferred optical output side at the shorter/lower reflectivity first reflector (Matsui 0103 and Furuya col. 3 line 65 – col. 4 line 5).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Furuya in view of Huang and Masui (US-20080002748-A1).
Regarding claim 5, modified Furuya discloses the semiconductor structure according to claim 2.
Modified Furuya does not disclose wherein a first groove of the plurality of first grooves has a width less than 100 nm, and an interval between the plurality of first grooves is less than 150 nm; and a second groove of the plurality of second grooves has a width less than 100 nm, and an interval between the plurality of second grooves is less than 150 nm.
Masui discloses a nitride semiconductor laser element with a diffraction grating having a groove width of 40 nm and a groove interval/pitch of 80 nm (figs. 1+2 grating 24 has groove width B = 40 nm and pitch P = 80 nm, 0089-0090).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a first groove of the plurality of first grooves has a width less than 100 nm, and an interval between the plurality of first grooves is less than 150 nm; and a second groove of the plurality of second grooves has a width less than 100 nm, and an interval between the plurality of second grooves is less than 150 nm to improve flatness of any embedded semiconductor layer above the first and second grooves/reflectors by minimizing impact of grooves on topography (Masui 0056-0058).
Claim(s) 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Furuya in view of Huang and Tsuda (US-20020056846-A1).
Regarding claim 8, modified Furuya the semiconductor structure according to claim 3.
Modified Furuya does not disclose wherein a material of the third semiconductor layer and a material of the fourth semiconductor layer each comprise a Group III nitride material; the first reflector structure further comprises a first partition groove extending along the second direction and intersecting the plurality of first grooves, and the Group III nitride material is prepared in the first partition groove; and the second reflector structure further comprises a second partition groove extending along the second direction and intersecting the plurality of second grooves, and the Group III nitride material is prepared in the second partition groove.
Tsuda discloses a semiconductor light emitting device with grooves perpendicularly arranged in a substrate and filled with GaN, AlGaN, or InGaN (figs. 2-4a, 0028, 0068-0071).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to arrange first and second partition grooves in plurality of first and second grooves and fill with GaN, AlGaN, or InGaN to provide an additional larger interconnected semiconductor structure of GaN, AlGaN, or InGaN material, improving structural integrity of device. See schematic X.
PNG
media_image2.png
220
591
media_image2.png
Greyscale
Schematic X
After modification (left to right), groove material (white space) now completely connected in both lateral and transverse directions, creating larger groove material structure and improving stability/durability of device.
Regarding claim 9, modified Furuya discloses the semiconductor structure according to claim 8, wherein the Group III nitride material comprises a gallium nitride material (claim 8 modification).
Modified Furuya does not disclose wherein the first direction is a [11-20] crystal orientation of a hexagonal crystal system of the gallium nitride material; and the second direction is a [1-100] crystal orientation of the hexagonal crystal system of the gallium nitride material.
Tsuda further discloses using the <1-100> and <11-20> directions as the directions of the grooves (0063-0067, 0122).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the first direction is a [11-20] crystal orientation of a hexagonal crystal system of the gallium nitride material; and the second direction is a [1-100] crystal orientation of the hexagonal crystal system of the gallium nitride material to provide good surface morphology of the semiconductor film (Tsuda 0066) and/or to relax crystal strain and suppress cracking (0064).
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Furuya in view of Uemura (US-20030151058-A1).
Regarding claim 12, Furuya discloses the semiconductor structure according to claim 11.
Furuya does not disclose wherein each of a material of the first semiconductor layer, a material of the active layer, and a material of the second semiconductor layer comprises a Group III nitride material.
Uemura discloses a light-emitting device with a GaN n type clad layer, a GaN emission layer, and an AlGaN p type clad layer (fig. 1 GaN n clad layer 14, GaN emission layer 15, AlGaN p clad layer 16, 0081-0084).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have each of a material of the first semiconductor layer, a material of the active layer, and a material of the second semiconductor layer comprises GaN, GaN, AlGaN, respectively to facilitate short-wavelength emission.
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Furuya in view of Zhang (US-20220206232-A1) and Huang.
Regarding claim 16, Furuya discloses the semiconductor structure preparation method according to claim 14, wherein forming the first reflector structure in the first region of the substrate and the second reflector structure in the second region of the substrate comprises: forming a dielectric material layer on a side surface of the substrate, wherein the dielectric material layer has a single-film structure or a multi-film structure (form 22+24 single film layer of Si3N4 on top side of 19+20, col. 5 lines 1-10, col. 9 lines 5-20); patterning the dielectric material layer to form a plurality of first grooves in the first region and a plurality of second grooves in the second region (22+24 patterned to form first grooves in 11 and second grooves in 13, col. 4 lines 30-55, col. 9 line 60 – col. 10 line 15), wherein the plurality of first grooves extend along a first direction and are arranged at uniform intervals along a second direction (figs. 1+2 first grooves between corrugations 29 extend along first direction (into page in fig. 2) and at uniform intervals along second direction (left to right in fig. 2)), the plurality of second grooves extend along the first direction and are arranged at uniform intervals along the second direction (second grooves between corrugations 30 extend along same first direction into page in fig. 2 and arranged at uniform intervals along left to right in fig. 2), the second direction is a direction in which the first reflector structure is pointing to the light-emitting structure (left to right direction is direction in which 22+29 pointing to 16+17+18), and the first direction and the second direction are perpendicular to each other (into page in fig. 2 perpendicular to left to right in fig. 2), wherein a dielectric material layer in the first region is used for forming a first sub-dielectric layer and a dielectric material layer in the second region is used for forming a second sub-dielectric layer (22+24 has 22 in 11 for forming first subdielectric, 22+24 has 24 in 13 for forming second subdielectric, col. 9 lines 5-15).
Furuya does not disclose preparing a Group III nitride material in each of the plurality of first grooves to form a third semiconductor layer, and preparing a Group III nitride material in each of the plurality of second grooves to form a fourth semiconductor layer.
Zhang discloses a grating with dielectric ridges and GaN grooves (fig. 7 ridges 722 and grooves 724, 0083-0085).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a Group III nitride material (GaN) in each of the plurality of first grooves to form a third semiconductor layer, and preparing a Group III nitride material (GaN) in each of the plurality of second grooves to form a fourth semiconductor layer to provide more flexibility in the wavelength tuning of the Bragg reflectors without being restricted to using the cladding layer 21 material or needing to alter the entire cladding layer 21 (Huang 0030).
Claim(s) 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Furuya in view of Furushima (US-20010010701-A1).
Regarding claim 18, Furuya discloses the semiconductor structure preparation method according to claim 14, wherein forming the light-emitting structure in the third region of the substrate comprises: forming a first semiconductor layer in the third region (first semiconductor layer 18 in region 12); forming an active layer on a side surface of the first semiconductor layer facing away from the substrate (forming active layer 17 on top side surface of 18 away from 19+20); and forming a second semiconductor layer on a side surface of the active layer facing away from the substrate (forming second layer 16 on top side surface of 17 away from 19+20).
Modified Furuya does not disclose etching a dielectric material layer in the third region until the substrate is exposed.
Furushima discloses disposing a dielectric material layer on a substrate and etching it in a light emitting region until the substrate is exposed (fig. 6 SiO2 layer 2a on substrate 1a then etched in light emitting region until substrate exposed and then light emitting structure grown in exposed region, 0091, 0095, 0098).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have etching a dielectric material layer in the third region until the substrate is exposed prior to growing light emitting structure in Furuya to provide more control over semiconductor active structure width and positioning (Furushima 0093).
Regarding claim 19, modified Furuya discloses the semiconductor structure preparation method according to claim 18, the method further comprises one of the following: forming a first electrode on a side of the second semiconductor layer facing away from the substrate (first electrode 14 on top side of 16 facing away from 19+20), and forming a second electrode on a side of the substrate facing away from the light-emitting structure (second electrode 15 on bottom side of 19+20 facing away from 16+17+18); or etching a part of the second semiconductor layer and a part of the active layer sequentially until a part of the first semiconductor layer is exposed, forming a first electrode on a side of the second semiconductor layer facing away from the substrate, and forming a second electrode on a side of the exposed part of the first semiconductor layer facing away from the substrate.
Modified Furuya does not disclose wherein after forming the light-emitting structure in the third region of the substrate.
Furushima discloses forming upper and lower electrodes on semiconductor device after formation of all semiconductor layers (fig. 6d electrodes 14 formed after 6a-c, 0099).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the electrodes after forming the light emitting structure to allow for more accurate placement of electrodes and obtain shortest possible distance between electrodes and light emitting structure.
Allowable Subject Matter
Claim 10, 17 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 10: Prior art of record does not disclose a depth of at least one of the first and second partition grooves being greater than or equal to a thickness of the corresponding reflector structure, in combination with the incorporated limitations of claims 1, 2, 3, 8. Although prior art of record does disclose a groove depth greater than a reflector structure thickness, it would not be obvious or reasonable to further modify the structure of claim 8’s modified Furuya in a manner suitable to read on claim 10. The motivations that apply to ensuring a generic groove depth/reflector thickness relationship would not apply to the specific structure after claim 8.
Claim 17: Prior art of record does not disclose depositing nitride material in partition grooves and subsequently preparing the nitride material from a partition groove to a plurality of first grooves by epitaxial lateral overgrowth, in combination with the remaining limitations of claim 17 and incorporated limitations of claims 14 and 16.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Gandrothula WO-2021081308-A1: Discloses nitride light emitting device with Bragg reflectors, epitaxial lateral overgrowth, and dielectric mask layers
Adachi US-20150214695-A1: Discloses surface emitting laser with active layer butt-joint integrated to two opposing DBR mirror units
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Alex Ehrlich whose telephone number is (703)756-5716. The examiner can normally be reached M-F 8-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MinSun Harvey can be reached at (571) 272-1835. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/A.E./Examiner, Art Unit 2828 /MINSUN O HARVEY/Supervisory Patent Examiner, Art Unit 2828
