DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to the filling of the Amendment on 06/15/2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 6, 9-12 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2016/0261184), hereinafter Chen, in view of Upadhayaya (US 2021/0408911).
Regarding claim 1, Chen discloses (see figures 1-7) a power supply circuit (figure 3), comprising: a switched-mode power supply (SMPS) (figure 3, part 3) (paragraph [0022]); a detector circuit (figure 3, part 35) coupled to the SMPS (figure 3, part 3; through P1-PM) and configured to detect (figure 3, part 35) a presence of one or more circuit elements (figure 3, part L1-LN) of the SMPS (figure 3, part 3) (paragraph [0026]; determining whether the inductors L1˜L4 in each phase exist or not, by determining whether the input ends P1˜PM and the input voltage VIN are conducted or not (open), so as to make the control circuit 33 determine whether to control conduction/cut-off status of the switching circuits SW1˜SW4 at each phase. That is, when the detecting circuit 35 of the instant disclosure determines that the inductors L3˜L4 do not exist), the detector circuit (figure 3, part 35) comprises: a voltage rail (figures 3 and 6, part Vin) and a switching voltage (VSW) node of the SMPS (figures 3 and 4, part a switching voltage node at Pi), when detecting the presence (figure 3, part through 35) of one or more circuit elements (figure 3, part L1-LN) (paragraph [0026]); and indicate the presence (figure 3, part through 35) of the one or more circuit elements (figure 3, part L1-LN) (paragraph [0026]); and a controller (figure 3, part 33) coupled to the detector circuit (figure 3, part 35) and configured to control the SMPS (figure 3, part 3) to operate with a number of converter phases (figure 3, part number of phases of 3) based on a number of the one or more circuit elements that are present (figure 3, part L1-LN) (paragraphs [0022]-[0026]; The detecting circuit 35 is coupled between each of the input ends P1˜PM and the control circuit 33. The detecting circuit 35 detects the conduction status of each of the input ends P1˜PM, for outputting a first control signal T1 accordingly. Then, the control circuit 33 selectively controls at least one of the switching circuits SW1˜SWM according to the first control signal T1… the main concept of the multi-phase boost converter 3 in the instant disclosure is determining whether the inductors L1˜L4 in each phase exist or not, by determining whether the input ends P1˜PM and the input voltage VIN are conducted or not (open), so as to make the control circuit 33 determine whether to control conduction/cut-off status of the switching circuits SW1˜SW4 at each phase. That is, when the detecting circuit 35 of the instant disclosure determines that the inductors L3˜L4 do not exist (indicated by only switching circuits SW1˜SW2 respectively coupling to inductors L1˜L2 as inputs), the detecting circuit 35 will output the related first control signal T1 to inform the control circuit 33 for turning-off the control of the switching circuit SW3˜SW4 corresponding to the phases not required to be switched).
Chen does not expressly disclose a first resistive element configured to be coupled between a voltage rail and a switching voltage (VSW) node of the SMPS; and a comparator configured to compare a voltage at the VSW node to a threshold.
Upadhayaya teaches (see figures 1-8) the detector circuit (figure 5, part detector circuit generated by R5, Q1, R2/R3 and 66) comprises: a first resistive element (figure 5, part R5) configured to be coupled between a voltage rail (figure 5, part Vin) and a switching voltage (VSW) node of the SMPS (figure 5, part SW; at detection in normal operation) (paragraph [0042]; In normal operation, the control signals HGATE and LGATE are asserted to close the disconnect transistors Q1 and Q2 and the power stage 50 is connected to the input voltage V.sub.IN and to the output node 56); and a comparator (figure 5, part 66) configured to compare a voltage at the VSW node (figure 5, part SW; through R2/R3) to a threshold (figure 5, part THD).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the detector circuit of Chen with the detector circuit features as taught by Upadhayaya and obtain a power supply circuit, comprising: a switched-mode power supply (SMPS);a detector circuit coupled to the SMPS and configured to detect a presence of one or more circuit elements of the SMPS, the detector circuit comprising: a first resistive element configured to be coupled between a voltage rail and a switching voltage (VSW) node of the SMPS, when detecting the presence of one or more circuit elements; and a comparator configured to compare a voltage at the VSW node to a threshold to indicate the presence of the one or more circuit elements; and a controller coupled to the detector circuit and configured to control the SMPS to operate with a number of converter phases based on a number of the one or more circuit elements that are present, because provides more efficient and accurate detection in order to obtain more efficient control.
Regarding claim 2, Chen and Upadhayaya teach everything claimed as applied above (see claim 1). Further, Chen discloses (see figures 1-7) the one or more circuit elements (figure 3, part L1-LN) of the SMPS (figure 3, part 3) comprise one or more of a plurality of inductive elements (figure 3, part L1-LN) associated with multiple converter phases of the SMPS (figure 3, part 3) (paragraph [0026]; determining whether the inductors L1˜L4 in each phase exist or not, by determining whether the input ends P1˜PM and the input voltage VIN are conducted or not (open), so as to make the control circuit 33 determine whether to control conduction/cut-off status of the switching circuits SW1˜SW4 at each phase. That is, when the detecting circuit 35 of the instant disclosure determines that the inductors L3˜L4 do not exist).
Regarding claim 3, Chen and Upadhayaya teach everything claimed as applied above (see claim 2). Further, Chen discloses (see figures 1-7) the SMPS (figure 3, part 3) comprises, for each of the multiple converter phases (figure 3, part multiple converter phases at 3): a high-side (HS) switch (figure 3, part inside in each SW1-SWm) (figure 4, part HS switch that received UGi) coupled a switching voltage (VSW) node (figures 3 and 4, part a switching voltage node at Pi), the VSW node (figures 3 and 4, part a switching voltage node at Pi) being coupled to a respective one of the plurality of inductive elements (figures 3 and 4, part L1-Ln); and a low-side (LS) switch (figure 4, part LS switch that received LGi) coupled between the VSW node (figures 3 and 4, part a switching voltage node at Pi) and a reference potential node (figure 4, part GND). However, Chen does not expressly disclose a high-side (HS) switch coupled between a voltage rail and a switching voltage (VSW) node.
Upadhayaya teaches (see figures 1-8) the SMPS (figure 1, part 10) comprises, for each of the multiple converter phases (figure 1, parts SPS1-SPSN+2): a high-side (HS) switch (figure 5, part Q3) coupled between a voltage rail (figure 5, part Vin) and a switching voltage (VSW) node (figure 5, parts SW node), the VSW node (figure 5, parts SW node)being coupled to a respective one of the plurality of inductive elements (figure 5, parts Lx); and a low-side (LS) switch (figure 5, part Q4) coupled between the VSW node (figure 5, parts SW node) and a reference potential node (figure 5, parts ground node).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to apply the detector and controller of Chen to the buck converter configuration as taught by Upadhayaya and obtain the SMPS comprises, for each of the multiple converter phases: a high-side (HS) switch coupled between a voltage rail and a switching voltage (VSW) node, the VSW node being coupled to a respective one of the plurality of inductive elements; and a low-side (LS) switch coupled between the VSW node and a reference potential node, because the combination result in more efficient step-down conversion based on the load demand.
Regarding claim 6, Chen and Upadhayaya teach everything claimed as applied above (see claim 1). Further, Chen discloses (see figures 1-7) the detector circuit (figure 3, part 35) further comprises detect (figure 3, part 35) the presence of the one or more circuit elements (figure 3, part L1-LN) (paragraph [0026]; determining whether the inductors L1˜L4 in each phase exist or not, by determining whether the input ends P1˜PM and the input voltage VIN are conducted or not (open), so as to make the control circuit 33 determine whether to control conduction/cut-off status of the switching circuits SW1˜SW4 at each phase. That is, when the detecting circuit 35 of the instant disclosure determines that the inductors L3˜L4 do not exist), and during voltage regulation via the SMPS (figure 3, part 3). However, Chen does not expressly disclose a switch coupled in series with the first resistive element, wherein the switch is configured to be closed to detect the presence of the one or more circuit elements, and wherein the switch is configured to be open during voltage regulation via the SMPS.
Upadhayaya teaches (see figures 1-8) the detector circuit (figure 5, part detector circuit generated by R5, Q1, R2/R3 and 66) further comprises a switch (figure 5, part Q1) coupled in series with the first resistive element (figure 5, part R5), wherein the switch is configured to be closed (figure 5, part Q1; closed), and wherein the switch is configured to be open (figure 5, part Q1; open).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the detector circuit of Chen with the detector circuit features as taught by Upadhayaya and obtain the detector circuit further comprises a switch coupled in series with the first resistive element, wherein the switch is configured to be closed to detect the presence of the one or more circuit elements, and wherein the switch is configured to be open during voltage regulation via the SMPS, because provides more efficient and accurate detection in order to obtain more efficient control.
Regarding claim 9, Chen and Upadhayaya teach everything claimed as applied above (see claim 1). Further, Chen discloses (see figures 1-7) the SMPS (figure 3, part 3). However, Chen does not expressly disclose a buck converter.
Upadhayaya teaches (see figures 1-8) the SMPS (figure 1, part 10) comprises a buck converter (figure 5, parts 50).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to apply the detector and controller of Chen to the buck converter configuration as taught by Upadhayaya and obtain the SMPS comprises a buck converter, because the combination result in more efficient step-down conversion based on the load demand.
Regarding claim 10, Chen discloses (see figures 1-7) a method for voltage regulation (figure 3), comprising: detecting (figure 3, part 35) a presence of one or more circuit elements (figure 3, part L1-LN) of a switched-mode power supply (SMPS) (figure 3, part 3) (paragraph [0026]; determining whether the inductors L1˜L4 in each phase exist or not, by determining whether the input ends P1˜PM and the input voltage VIN are conducted or not (open), so as to make the control circuit 33 determine whether to control conduction/cut-off status of the switching circuits SW1˜SW4 at each phase. That is, when the detecting circuit 35 of the instant disclosure determines that the inductors L3˜L4 do not exist); wherein detecting the presence (figure 3, part 35) comprises: a voltage rail (figures 3 and 6, part Vin) and a switching voltage (VSW) node of the SMPS (figures 3 and 4, part a switching voltage node at Pi); and to detect the presence (figure 3, part through 35) of the one or more circuit elements (figure 3, part L1-LN) (paragraph [0026]); configuring (figure 3, part through 33) the SMPS (figure 3, part 3) to operate with a number of converter phases (figure 3, part number of phases of 3) based on a number of the one or more circuit elements (figure 3, part L1-LN) that are present (figure 3, part through 35); and generating, via the SMPS (figure 3, part 3), a regulated voltage (figure 3, part Vout) using the number of converter phases (figure 3, part number of phases of 3) (paragraphs [0022]-[0026]; The detecting circuit 35 is coupled between each of the input ends P1˜PM and the control circuit 33. The detecting circuit 35 detects the conduction status of each of the input ends P1˜PM, for outputting a first control signal T1 accordingly. Then, the control circuit 33 selectively controls at least one of the switching circuits SW1˜SWM according to the first control signal T1… the main concept of the multi-phase boost converter 3 in the instant disclosure is determining whether the inductors L1˜L4 in each phase exist or not, by determining whether the input ends P1˜PM and the input voltage VIN are conducted or not (open), so as to make the control circuit 33 determine whether to control conduction/cut-off status of the switching circuits SW1˜SW4 at each phase. That is, when the detecting circuit 35 of the instant disclosure determines that the inductors L3˜L4 do not exist (indicated by only switching circuits SW1˜SW2 respectively coupling to inductors L1˜L2 as inputs), the detecting circuit 35 will output the related first control signal T1 to inform the control circuit 33 for turning-off the control of the switching circuit SW3˜SW4 corresponding to the phases not required to be switched).
Chen does not expressly disclose coupling a first resistive element between a voltage rail and a switching voltage (VSW) node of the SMPS; and comparing a voltage at the VSW node to a threshold.
Upadhayaya teaches (see figures 1-8) coupling a first resistive element (figure 5, part R5) between a voltage rail (figure 5, part Vin) and a switching voltage (VSW) node of the SMPS (figure 5, part SW; at detection in normal operation) (paragraph [0042]; In normal operation, the control signals HGATE and LGATE are asserted to close the disconnect transistors Q1 and Q2 and the power stage 50 is connected to the input voltage V.sub.IN and to the output node 56); and comparing (figure 5, part 66) a voltage at the VSW node (figure 5, part SW; through R2/R3) to a threshold (figure 5, part THD).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the detector circuit of Chen with the detector circuit features as taught by Upadhayaya and obtain a method for voltage regulation, comprising: detecting a presence of one or more circuit elements of a switched-mode power supply (SMPS), wherein detecting the presence comprises: coupling a first resistive element between a voltage rail and a switching voltage (VSW) node of the SMPS; and comparing a voltage at the VSW node to a threshold to detect the presence of the one or more circuit elements; configuring the SMPS to operate with a number of converter phases based on a number of the one or more circuit elements that are present; and generating, via the SMPS, a regulated voltage using the number of converter phases, because provides more efficient and accurate detection in order to obtain more efficient control.
Regarding claim 11, claim 2 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons.
Regarding claim 12, claim 3 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons.
Regarding claim 15, claim 6 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons.
Claims 5 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2016/0261184), hereinafter Chen, in view of Upadhayaya (US 2021/0408911), and further in view of Hartular et al. (US 2002/0015319), hereinafter Hartular.
Regarding claim 5, Chen and Upadhayaya teach everything claimed as applied above (see claim 1). Further, Chen discloses (see figures 1-7) the detector circuit (figure 3, part 35). However, Chen does not expressly disclose a second resistive element selectively coupled between an output node of the SMPS and a reference potential node of the SMPS.
Hartular teaches (see figures 1-6) the detector circuit (figure 3, part detector circuit generated by 182, 58’ and 74b’) further comprises a second resistive element (figure 3, part 182) selectively coupled (figure 3, part through 58’) between an output node of the SMPS (figure 3, part output node at Vout) and a reference potential node of the SMPS (figure 3, part ground 36’).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the combination of Chen and Upadhayaya with the detector circuit features as taught by Hartular and obtain the detector circuit further comprises a second resistive element selectively coupled between an output node of the SMPS and a reference potential node of the SMPS, because provides more accurate measurement of the circuit status.
Regarding claim 14, claim 5 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons.
Claims 7 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2016/0261184), hereinafter Chen, in view of Upadhayaya (US 2021/0408911), and further in view of Lu et al. (US 2022/0006376), hereinafter Lu.
Regarding claim 7, Chen and Upadhayaya teach everything claimed as applied above (see claim 1). Further, Chen discloses (see figures 1-7) the controller (figure 3, part 33) is further configured to reduce power consumption (figure 3, part through reduction of number of phases of 3) based on the number of the one or more circuit elements that are present (figure 3, part L1-LN) (paragraphs [0022]-[0026]; The detecting circuit 35 is coupled between each of the input ends P1˜PM and the control circuit 33. The detecting circuit 35 detects the conduction status of each of the input ends P1˜PM, for outputting a first control signal T1 accordingly. Then, the control circuit 33 selectively controls at least one of the switching circuits SW1˜SWM according to the first control signal T1… the main concept of the multi-phase boost converter 3 in the instant disclosure is determining whether the inductors L1˜L4 in each phase exist or not, by determining whether the input ends P1˜PM and the input voltage VIN are conducted or not (open), so as to make the control circuit 33 determine whether to control conduction/cut-off status of the switching circuits SW1˜SW4 at each phase. That is, when the detecting circuit 35 of the instant disclosure determines that the inductors L3˜L4 do not exist (indicated by only switching circuits SW1˜SW2 respectively coupling to inductors L1˜L2 as inputs), the detecting circuit 35 will output the related first control signal T1 to inform the control circuit 33 for turning-off the control of the switching circuit SW3˜SW4 corresponding to the phases not required to be switched. Therefore, compared to the conventional multiple-phases boost converter 2 shown in FIG. 2, the multi-phase boost converter 3 of the instant disclosure can further achieve the purpose of decreasing unnecessary power consumption). However, Chen does not expressly disclose one or more processing units.
Lu teaches (see figures 1-12) the controller (figure 3, part controller generated by 6 and 7) is further configured to cause one or more processing units to reduce power consumption (figure 2, part 206; when detect faulty phase) (paragraphs [0059]-[0061]; the multi-phase buck converter circuit 205 may provide electric energy for the processor 206. In operation of the multi-phase buck converter circuit 205, the multi-phase buck converter circuit 205 can detect whether the N phase buck circuits included in the multi-phase buck converter circuit 205 are faulty can be detected in real time and synchronously. When a phase buck circuit is faulty, driving of that phase buck circuit may be stopped. It should be understood that more than one phase buck circuit can be suspended, as needed).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the apparatus for voltage regulation of Chen with the processor features as taught by Lu and obtain the controller is further configured to cause one or more processing units to reduce power consumption based on the number of the one or more circuit elements that are present, because the combination result in more efficient voltage regulation for a processor system with prevention of wrong operation (paragraph [0004]).
Regarding claim 16, claim 7 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons.
Claims 8 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2016/0261184), hereinafter Chen, in view of Upadhayaya (US 2021/0408911), and further in view of You et al. (US 2023/0057705), hereinafter You.
Regarding claim 8, Chen and Upadhayaya teach everything claimed as applied above (see claim 1). Further, Chen discloses (see figures 1-7) the controller (figure 3, part 33 is further configured to obtain a notification (figure 3, part T1 from 35) of the number of the one or more circuit elements (figure 3, part L1-LN) that are present (paragraphs [0022]-[0026]; The detecting circuit 35 is coupled between each of the input ends P1˜PM and the control circuit 33. The detecting circuit 35 detects the conduction status of each of the input ends P1˜PM, for outputting a first control signal T1 accordingly. Then, the control circuit 33 selectively controls at least one of the switching circuits SW1˜SWM according to the first control signal T1… the main concept of the multi-phase boost converter 3 in the instant disclosure is determining whether the inductors L1˜L4 in each phase exist or not, by determining whether the input ends P1˜PM and the input voltage VIN are conducted or not (open), so as to make the control circuit 33 determine whether to control conduction/cut-off status of the switching circuits SW1˜SW4 at each phase. That is, when the detecting circuit 35 of the instant disclosure determines that the inductors L3˜L4 do not exist (indicated by only switching circuits SW1˜SW2 respectively coupling to inductors L1˜L2 as inputs), the detecting circuit 35 will output the related first control signal T1 to inform the control circuit 33 for turning-off the control of the switching circuit SW3˜SW4 corresponding to the phases not required to be switched). However, Chen does not expressly disclose the controller is further configured to output a notification of the number of the one or more circuit elements that are present.
You teaches (see figures 1-13) the controller (figure 2, part 140) is further configured to output a notification (figure 2, part 149) of the number of the one or more circuit elements that are failure (figure 2, parts 221-1 to 22N-1) (paragraph [0094]; the management resource 141 generates the status information 149 to indicate a respective identity (such as winding 221-1 as in FIG. 4) of the winding that experiences the short circuit condition. When tested individually, in a manner as previously discussed, the management resource 141 determines when any respective winding of the secondary windings 221-1, 221-2, etc., experiences a respective short circuit failure).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the controller of Chen with the notification features as taught by You and obtain the controller is further configured to output a notification of the number of the one or more circuit elements that are present, because it provides health status of the circuit in efficient manner in order to obtain more efficient management of system operation (paragraph [0026]).
Regarding claim 17, claim 8 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2016/0261184), hereinafter Chen, in view of Rahardjo et al. (US 2016/0033611), hereinafter Rahardjo.
Regarding claim 18, Chen discloses (see figures 1-7) an apparatus for voltage regulation (figure 3), comprising: one or more processors (figure 3, part 33), the one or more processors (figure 3, part 33) being configured to: receive (figure 3, part through T1) an indication of a presence (figure 3, part through 35) of one or more circuit elements (figure 3, part L1-LN) of a switched-mode power supply (SMPS) (figure 3, part 3) (paragraph [0026]; determining whether the inductors L1˜L4 in each phase exist or not, by determining whether the input ends P1˜PM and the input voltage VIN are conducted or not (open), so as to make the control circuit 33 determine whether to control conduction/cut-off status of the switching circuits SW1˜SW4 at each phase. That is, when the detecting circuit 35 of the instant disclosure determines that the inductors L3˜L4 do not exist); control (figure 3, part 33) the SMPS (figure 3, part 3) to operate with a number of converter phases (figure 3, part number of phases of 3) based on a number of the one or more circuit elements (figure 3, part L1-LN) that are present (figure 3, part through 35) to generate a regulated voltage (figure 3, part VOUT) via the SMPS (figure 3, part 3) using the number of converter phases (figure 3, part number of phases of 3); and power (figure 3, part through VOUT) from the SMPS (figure 3, part 3), based on the number of the one or more circuit elements (figure 3, part L1-LN) that are present (figure 3, part through 35) (paragraphs [0022]-[0026]; The detecting circuit 35 is coupled between each of the input ends P1˜PM and the control circuit 33. The detecting circuit 35 detects the conduction status of each of the input ends P1˜PM, for outputting a first control signal T1 accordingly. Then, the control circuit 33 selectively controls at least one of the switching circuits SW1˜SWM according to the first control signal T1… the main concept of the multi-phase boost converter 3 in the instant disclosure is determining whether the inductors L1˜L4 in each phase exist or not, by determining whether the input ends P1˜PM and the input voltage VIN are conducted or not (open), so as to make the control circuit 33 determine whether to control conduction/cut-off status of the switching circuits SW1˜SW4 at each phase. That is, when the detecting circuit 35 of the instant disclosure determines that the inductors L3˜L4 do not exist (indicated by only switching circuits SW1˜SW2 respectively coupling to inductors L1˜L2 as inputs), the detecting circuit 35 will output the related first control signal T1 to inform the control circuit 33 for turning-off the control of the switching circuit SW3˜SW4 corresponding to the phases not required to be switched).
Chen does not expressly disclose a memory; and one or more processors coupled to the memory; and supply power to one or more processing units; and cause the one or more processing units to reduce consumption of the power from the SMPS.
Rahardjo teaches (see figures 1-4) a memory; and one or more processors (figure 3, part CPU connected to 222 that receive power from multi-phase VR 144) coupled to the memory (figure 3, part memory of the CPU connected to 222 that receive power from multi-phase VR 144) (paragraph [0003]; a CPU typically utilize multi-phase voltage regulators (VR's) that include multiple CPU core voltage (Vcore) phases that are coupled together to provide power via a first Vcore power rail to the main core of a CPU… integrated memory controller circuitry of a CPU); and supply power (figure 3, part from 144 to 222) to one or more processing units (figure 3, part CPU connected to 222 that receive power from multi-phase VR 144); and cause the one or more processing units (figure 3, part CPU connected to 222 that receive power from multi-phase VR 144) to reduce consumption of the power from the SMPS (figure 3) (paragraph [0004]; Each given one of the multiple Vcore phases of a multi-phase voltage regulator includes a DC/DC voltage regulation circuitry (or a Vcore regulator circuit) that includes inductor direct-current resistance (DCR) current sense circuitry that is used to sense a value of current drawn from the given VR phase by the main core of the CPU of an information handling system, and each VR phase provides this sensed Vcore current value to the CPU. The CPU in turn uses the sensed Vcore current of the multiple VR phases to determine the total amount of power being drawn by the CPU, and to compare this total CPU power consumption to maximum allowable CPU power limit so as to maintain maximum CPU performance without exceeding the maximum allowable CPU power limit. In this regard, the CPU will reduce CPU power consumption (together with CPU performance) when the actual CPU power consumption approaches the maximum allowable CPU power consumption value to keep actual the CPU power consumption from exceeding the maximum allowable value, and will increase the CPU power consumption (together with CPU performance) when the actual CPU power consumption drops below the maximum allowable CPU power consumption value so as to maximize CPU performance when possible).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the apparatus for voltage regulation of Chen with the memory and processor features as taught by Rahardjo and obtain an apparatus for voltage regulation, comprising: memory; and one or more processors coupled to the memory, the one or more processors being configured to: receive an indication of a presence of one or more circuit elements of a switched- mode power supply (SMPS); control the SMPS to operate with a number of converter phases based on a number of the one or more circuit elements that are present to generate a regulated voltage via the SMPS using the number of converter phases and to supply power to one or more processing units; and cause the one or more processing units to reduce consumption of the power from the SMPS, based on the number of the one or more circuit elements that are present, because the combination result in more efficient and reliable voltage regulation for a processor system in order to obtain better system performance (paragraph [0005]).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2016/0261184), hereinafter Chen, in view of Rahardjo et al. (US 2016/0033611), hereinafter Rahardjo, and further in view of You et al. (US 2023/0057705), hereinafter You.
Regarding claim 20, Chen and Rahardjo teach everything claimed as applied above (see claim 18). Further, Chen discloses (see figures 1-7) the controller (figure 3, part 33 is further configured to obtain a notification (figure 3, part T1 from 35) of the number of the one or more circuit elements (figure 3, part L1-LN) that are present (paragraphs [0022]-[0026]; The detecting circuit 35 is coupled between each of the input ends P1˜PM and the control circuit 33. The detecting circuit 35 detects the conduction status of each of the input ends P1˜PM, for outputting a first control signal T1 accordingly. Then, the control circuit 33 selectively controls at least one of the switching circuits SW1˜SWM according to the first control signal T1… the main concept of the multi-phase boost converter 3 in the instant disclosure is determining whether the inductors L1˜L4 in each phase exist or not, by determining whether the input ends P1˜PM and the input voltage VIN are conducted or not (open), so as to make the control circuit 33 determine whether to control conduction/cut-off status of the switching circuits SW1˜SW4 at each phase. That is, when the detecting circuit 35 of the instant disclosure determines that the inductors L3˜L4 do not exist (indicated by only switching circuits SW1˜SW2 respectively coupling to inductors L1˜L2 as inputs), the detecting circuit 35 will output the related first control signal T1 to inform the control circuit 33 for turning-off the control of the switching circuit SW3˜SW4 corresponding to the phases not required to be switched). However, Chen does not expressly disclose the one or more processors are further configured to output a notification of the number of the one or more circuit elements that are present.
You teaches (see figures 1-13) the one or more processors (figure 2, part 140) are further configured to output a notification (figure 2, part 149) of the number of the one or more circuit elements that are failure (figure 2, parts 221-1 to 22N-1) (paragraph [0094]; the management resource 141 generates the status information 149 to indicate a respective identity (such as winding 221-1 as in FIG. 4) of the winding that experiences the short circuit condition. When tested individually, in a manner as previously discussed, the management resource 141 determines when any respective winding of the secondary windings 221-1, 221-2, etc., experiences a respective short circuit failure).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the combination of Chen and Rahardjo with the notification features as taught by You and obtain the one or more processors are further configured to output a notification of the number of the one or more circuit elements that are present, because it provides health status of the circuit in efficient manner in order to obtain more efficient management of system operation (paragraph [0026]).
Response to Arguments
Applicant's arguments filed 06/15/2026 have been fully considered but they are not persuasive.
Applicant’s argues on pages 6-7 of the Applicant's Response (“Applicant respectfully submits that Chen, in view of Upadhayaya fails to teach or suggest "a first resistive element configured to be coupled between a voltage rail and a switching voltage (VSW) node of the SMPS, when detecting the presence of one or more circuit elements; and a comparator configured to compare a voltage at the VSW node to a threshold to indicate the presence of the one or more circuit elements" as recited in claim 1”).
The Examiner respectfully disagrees with Applicant’s arguments, because the rejection is a 103 combination between Chen and Upadhayaya. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). In this case, the primary reference Chen discloses the detector circuit (figure 3, part 35) comprises: a voltage rail (figures 3 and 6, part Vin) and a switching voltage (VSW) node of the SMPS (figures 3 and 4, part a switching voltage node at Pi), when detecting the presence (figure 3, part through 35) of one or more circuit elements (figure 3, part L1-LN) (paragraph [0026]); and indicate the presence (figure 3, part through 35) of the one or more circuit elements (figure 3, part L1-LN) (paragraph [0026]; determining whether the inductors L1˜L4 in each phase exist or not, by determining whether the input ends P1˜PM and the input voltage VIN are conducted or not (open), so as to make the control circuit 33 determine whether to control conduction/cut-off status of the switching circuits SW1˜SW4 at each phase. That is, when the detecting circuit 35 of the instant disclosure determines that the inductors L3˜L4 do not exist). Upadhayaya teaches the detector circuit (figure 5, part detector circuit generated by R5, Q1, R2/R3 and 66) comprises: a first resistive element (figure 5, part R5) configured to be coupled between a voltage rail (figure 5, part Vin) and a switching voltage (VSW) node of the SMPS (figure 5, part SW; at detection in normal operation) (paragraph [0042]; In normal operation, the control signals HGATE and LGATE are asserted to close the disconnect transistors Q1 and Q2 and the power stage 50 is connected to the input voltage V.sub.IN and to the output node 56); and a comparator (figure 5, part 66) configured to compare a voltage at the VSW node (figure 5, part SW; through R2/R3) to a threshold (figure 5, part THD). It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the detector circuit of Chen with the detector circuit features as taught by Upadhayaya and obtain a power supply circuit, comprising: a switched-mode power supply (SMPS);a detector circuit coupled to the SMPS and configured to detect a presence of one or more circuit elements of the SMPS, the detector circuit comprising: a first resistive element configured to be coupled between a voltage rail and a switching voltage (VSW) node of the SMPS, when detecting the presence of one or more circuit elements; and a comparator configured to compare a voltage at the VSW node to a threshold to indicate the presence of the one or more circuit elements; and a controller coupled to the detector circuit and configured to control the SMPS to operate with a number of converter phases based on a number of the one or more circuit elements that are present, because provides more efficient and accurate detection in order to obtain more efficient control. As discussed above, the combination of the detection of the presence (figure 3, part through 35) of one or more circuit elements (figure 3, part L1-LN) as disclosed by Chen with the detector circuit features as taught by Upadhayaya result in the claimed limitation.
Applicant’s arguments with respect to claim 18 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Carlos O. Rivera-Pérez, whose telephone number is (571) 272-2432 and fax is (571) 273-2432. The examiner can normally be reached on Monday through Friday, 8:30 AM – 5:00 PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V. Tran can be reached on (571) 270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/C.O.R. /
Examiner, Art Unit 2838
/THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838
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