DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 10 and 11 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Chen et al. (US 2016/0261184), hereinafter Chen.
Regarding claim 1, Chen discloses (see figures 1-7) a power supply circuit (figure 3), comprising: a switched-mode power supply (SMPS) (figure 3, part 3) (paragraph [0022]); a detector circuit (figure 3, part 35) coupled to the SMPS (figure 3, part 3; through P1-PM) and configured to detect (figure 3, part 35) a presence of one or more circuit elements (figure 3, part L1-LN) of the SMPS (figure 3, part 3) (paragraph [0026]; determining whether the inductors L1˜L4 in each phase exist or not, by determining whether the input ends P1˜PM and the input voltage VIN are conducted or not (open), so as to make the control circuit 33 determine whether to control conduction/cut-off status of the switching circuits SW1˜SW4 at each phase. That is, when the detecting circuit 35 of the instant disclosure determines that the inductors L3˜L4 do not exist); and a controller (figure 3, part 33) coupled to the detector circuit (figure 3, part 35) and configured to control the SMPS (figure 3, part 3) to operate with a number of converter phases (figure 3, part number of phases of 3) based on a number of the one or more circuit elements that are present (figure 3, part L1-LN) (paragraphs [0022]-[0026]; The detecting circuit 35 is coupled between each of the input ends P1˜PM and the control circuit 33. The detecting circuit 35 detects the conduction status of each of the input ends P1˜PM, for outputting a first control signal T1 accordingly. Then, the control circuit 33 selectively controls at least one of the switching circuits SW1˜SWM according to the first control signal T1… the main concept of the multi-phase boost converter 3 in the instant disclosure is determining whether the inductors L1˜L4 in each phase exist or not, by determining whether the input ends P1˜PM and the input voltage VIN are conducted or not (open), so as to make the control circuit 33 determine whether to control conduction/cut-off status of the switching circuits SW1˜SW4 at each phase. That is, when the detecting circuit 35 of the instant disclosure determines that the inductors L3˜L4 do not exist (indicated by only switching circuits SW1˜SW2 respectively coupling to inductors L1˜L2 as inputs), the detecting circuit 35 will output the related first control signal T1 to inform the control circuit 33 for turning-off the control of the switching circuit SW3˜SW4 corresponding to the phases not required to be switched).
Regarding claim 2, Chen discloses everything claimed as applied above (see claim 1). Further, Chen discloses (see figures 1-7) the one or more circuit elements (figure 3, part L1-LN) of the SMPS (figure 3, part 3) comprise one or more of a plurality of inductive elements (figure 3, part L1-LN) associated with multiple converter phases of the SMPS (figure 3, part 3) (paragraph [0026]; determining whether the inductors L1˜L4 in each phase exist or not, by determining whether the input ends P1˜PM and the input voltage VIN are conducted or not (open), so as to make the control circuit 33 determine whether to control conduction/cut-off status of the switching circuits SW1˜SW4 at each phase. That is, when the detecting circuit 35 of the instant disclosure determines that the inductors L3˜L4 do not exist).
Regarding claim 10, Chen discloses (see figures 1-7) a method for voltage regulation (figure 3), comprising: detecting (figure 3, part 35) a presence of one or more circuit elements (figure 3, part L1-LN) of a switched-mode power supply (SMPS) (figure 3, part 3) (paragraph [0026]; determining whether the inductors L1˜L4 in each phase exist or not, by determining whether the input ends P1˜PM and the input voltage VIN are conducted or not (open), so as to make the control circuit 33 determine whether to control conduction/cut-off status of the switching circuits SW1˜SW4 at each phase. That is, when the detecting circuit 35 of the instant disclosure determines that the inductors L3˜L4 do not exist); configuring (figure 3, part through 33) the SMPS (figure 3, part 3) to operate with a number of converter phases (figure 3, part number of phases of 3) based on a number of the one or more circuit elements (figure 3, part L1-LN) that are present (figure 3, part through 35); and generating, via the SMPS (figure 3, part 3), a regulated voltage (figure 3, part Vout) using the number of converter phases (figure 3, part number of phases of 3) (paragraphs [0022]-[0026]; The detecting circuit 35 is coupled between each of the input ends P1˜PM and the control circuit 33. The detecting circuit 35 detects the conduction status of each of the input ends P1˜PM, for outputting a first control signal T1 accordingly. Then, the control circuit 33 selectively controls at least one of the switching circuits SW1˜SWM according to the first control signal T1… the main concept of the multi-phase boost converter 3 in the instant disclosure is determining whether the inductors L1˜L4 in each phase exist or not, by determining whether the input ends P1˜PM and the input voltage VIN are conducted or not (open), so as to make the control circuit 33 determine whether to control conduction/cut-off status of the switching circuits SW1˜SW4 at each phase. That is, when the detecting circuit 35 of the instant disclosure determines that the inductors L3˜L4 do not exist (indicated by only switching circuits SW1˜SW2 respectively coupling to inductors L1˜L2 as inputs), the detecting circuit 35 will output the related first control signal T1 to inform the control circuit 33 for turning-off the control of the switching circuit SW3˜SW4 corresponding to the phases not required to be switched).
Regarding claim 11, claim 1 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 7, 9, 12, 16, 18 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2016/0261184), hereinafter Chen, in view of Lu et al. (US 2022/0006376), hereinafter Lu.
Regarding claim 3, Chen discloses everything claimed as applied above (see claim 2). Further, Chen discloses (see figures 1-7) the SMPS (figure 3, part 3) comprises, for each of the multiple converter phases (figure 3, part multiple converter phases at 3): a high-side (HS) switch (figure 3, part inside in each SW1-SWm) (figure 4, part HS switch that received UGi) coupled a switching voltage (VSW) node (figures 3 and 4, part a switching voltage node at Pi), the VSW node (figures 3 and 4, part a switching voltage node at Pi) being coupled to a respective one of the plurality of inductive elements (figures 3 and 4, part L1-Ln); and a low-side (LS) switch (figure 4, part LS switch that received LGi) coupled between the VSW node (figures 3 and 4, part a switching voltage node at Pi) and a reference potential node (figure 4, part GND). However, Chen does not expressly disclose a high-side (HS) switch coupled between a voltage rail and a switching voltage (VSW) node.
Lu teaches (see figures 1-12) the SMPS (figure 1, part 100) comprises, for each of the multiple converter phases (figure 1, parts 3): a high-side (HS) switch (figure 1, part HS switch between d1/s1) coupled between a voltage rail (figure 1, part voltage rail from 1) and a switching voltage (VSW) node (figure 1, parts switching voltage node between s1/d2), the VSW node (figure 1, parts switching voltage node between s1/d2) being coupled to a respective one of the plurality of inductive elements (figure 1, parts 4); and a low-side (LS) switch (figure 1, part LS switch between d2/s2) coupled between the VSW node (figure 1, parts switching voltage node between s1/d2) and a reference potential node (figure 1, parts reference potential node at s2).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to apply the detector and controller of Chen to the buck converter configuration as taught by Lu and obtain the SMPS comprises, for each of the multiple converter phases: a high-side (HS) switch coupled between a voltage rail and a switching voltage (VSW) node, the VSW node being coupled to a respective one of the plurality of inductive elements; and a low-side (LS) switch coupled between the VSW node and a reference potential node, because the combination result in more efficient buck conversion for a processor system with prevention of wrong operation (paragraph [0004]).
Regarding claim 7, Chen discloses everything claimed as applied above (see claim 1). Further, Chen discloses (see figures 1-7) the controller (figure 3, part 33) is further configured to reduce power consumption (figure 3, part through reduction of number of phases of 3) based on the number of the one or more circuit elements that are present (figure 3, part L1-LN) (paragraphs [0022]-[0026]; The detecting circuit 35 is coupled between each of the input ends P1˜PM and the control circuit 33. The detecting circuit 35 detects the conduction status of each of the input ends P1˜PM, for outputting a first control signal T1 accordingly. Then, the control circuit 33 selectively controls at least one of the switching circuits SW1˜SWM according to the first control signal T1… the main concept of the multi-phase boost converter 3 in the instant disclosure is determining whether the inductors L1˜L4 in each phase exist or not, by determining whether the input ends P1˜PM and the input voltage VIN are conducted or not (open), so as to make the control circuit 33 determine whether to control conduction/cut-off status of the switching circuits SW1˜SW4 at each phase. That is, when the detecting circuit 35 of the instant disclosure determines that the inductors L3˜L4 do not exist (indicated by only switching circuits SW1˜SW2 respectively coupling to inductors L1˜L2 as inputs), the detecting circuit 35 will output the related first control signal T1 to inform the control circuit 33 for turning-off the control of the switching circuit SW3˜SW4 corresponding to the phases not required to be switched. Therefore, compared to the conventional multiple-phases boost converter 2 shown in FIG. 2, the multi-phase boost converter 3 of the instant disclosure can further achieve the purpose of decreasing unnecessary power consumption). However, Chen does not expressly disclose one or more processing units.
Lu teaches (see figures 1-12) the controller (figure 3, part controller generated by 6 and 7) is further configured to cause one or more processing units to reduce power consumption (figure 2, part 206; when detect faulty phase) (paragraphs [0059]-[0061]; the multi-phase buck converter circuit 205 may provide electric energy for the processor 206. In operation of the multi-phase buck converter circuit 205, the multi-phase buck converter circuit 205 can detect whether the N phase buck circuits included in the multi-phase buck converter circuit 205 are faulty can be detected in real time and synchronously. When a phase buck circuit is faulty, driving of that phase buck circuit may be stopped. It should be understood that more than one phase buck circuit can be suspended, as needed).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the apparatus for voltage regulation of Chen with the processor features as taught by Lu and obtain the controller is further configured to cause one or more processing units to reduce power consumption based on the number of the one or more circuit elements that are present, because the combination result in more efficient voltage regulation for a processor system with prevention of wrong operation (paragraph [0004]).
Regarding claim 9, Chen discloses everything claimed as applied above (see claim 1). Further, Chen discloses (see figures 1-7) the SMPS (figure 3, part 3). However, Chen does not expressly disclose a buck converter.
Lu teaches (see figures 1-12) the SMPS (figure 1, part 100) comprises a buck converter (figure 1, part 100) (paragraph [0053]; A multi-phase buck converter circuit).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to apply the detector and controller of Chen to the buck converter configuration as taught by Lu and obtain the SMPS comprises, for each of the multiple converter phases: a high-side (HS) switch coupled between a voltage rail and a switching voltage (VSW) node, the VSW node being coupled to a respective one of the plurality of inductive elements; and a low-side (LS) switch coupled between the VSW node and a reference potential node, because the combination result in more efficient buck conversion for a processor system with prevention of wrong operation (paragraph [0004]).
Regarding claim 12, claim 3 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons.
Regarding claim 16, claim 7 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons.
Regarding claim 18, Chen discloses (see figures 1-7) an apparatus for voltage regulation (figure 3), comprising: one or more processors (figure 3, part 33), the one or more processors (figure 3, part 33) being configured to: receive (figure 3, part through T1) an indication of a presence (figure 3, part through 35) of one or more circuit elements (figure 3, part L1-LN) of a switched-mode power supply (SMPS) (figure 3, part 3) (paragraph [0026]; determining whether the inductors L1˜L4 in each phase exist or not, by determining whether the input ends P1˜PM and the input voltage VIN are conducted or not (open), so as to make the control circuit 33 determine whether to control conduction/cut-off status of the switching circuits SW1˜SW4 at each phase. That is, when the detecting circuit 35 of the instant disclosure determines that the inductors L3˜L4 do not exist); and control (figure 3, part 33) the SMPS (figure 3, part 3) to operate with a number of converter phases (figure 3, part number of phases of 3) based on a number of the one or more circuit elements (figure 3, part L1-LN) that are present (figure 3, part through 35) to generate a regulated voltage (figure 3, part VOUT) via the SMPS (figure 3, part 3) using the number of converter phases (figure 3, part number of phases of 3) (paragraphs [0022]-[0026]; The detecting circuit 35 is coupled between each of the input ends P1˜PM and the control circuit 33. The detecting circuit 35 detects the conduction status of each of the input ends P1˜PM, for outputting a first control signal T1 accordingly. Then, the control circuit 33 selectively controls at least one of the switching circuits SW1˜SWM according to the first control signal T1… the main concept of the multi-phase boost converter 3 in the instant disclosure is determining whether the inductors L1˜L4 in each phase exist or not, by determining whether the input ends P1˜PM and the input voltage VIN are conducted or not (open), so as to make the control circuit 33 determine whether to control conduction/cut-off status of the switching circuits SW1˜SW4 at each phase. That is, when the detecting circuit 35 of the instant disclosure determines that the inductors L3˜L4 do not exist (indicated by only switching circuits SW1˜SW2 respectively coupling to inductors L1˜L2 as inputs), the detecting circuit 35 will output the related first control signal T1 to inform the control circuit 33 for turning-off the control of the switching circuit SW3˜SW4 corresponding to the phases not required to be switched).
Chen does not expressly disclose a memory; and one or more processors coupled to the memory.
Lu teaches (see figures 1-12) an apparatus for voltage regulation (figure 2), comprising: a memory (figure 2, part 203); and one or more processors (figure 2, parts 201/206) coupled to the memory (figure 2, part 203; through 202), the one or more processors (figure 2, parts 201/206) (paragraphs [0054]-[0061]).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the apparatus for voltage regulation of Chen with the memory and processor features as taught by Lu and obtain an apparatus for voltage regulation, comprising: a memory; and one or more processors coupled to the memory, the one or more processors being configured to: receive an indication of a presence of one or more circuit elements of a switched-mode power supply (SMPS); and control the SMPS to operate with a number of converter phases based on a number of the one or more circuit elements that are present to generate a regulated voltage via the SMPS using the number of converter phases, because the combination result in more efficient voltage regulation for a processor system with prevention of wrong operation (paragraph [0004]).
Regarding claim 19, claim 7 has the same limitations, based on this is rejected for the same reasons.
Claims 4, 6, 13 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2016/0261184), hereinafter Chen, in view of Upadhayaya (US 2021/0408911).
Regarding claim 4, Chen discloses everything claimed as applied above (see claim 1). Further, Chen discloses (see figures 1-7) the detector circuit (figure 3, part 35) comprises: a voltage rail (figures 3 and 6, part Vin) and a switching voltage (VSW) node of the SMPS (figures 3 and 4, part a switching voltage node at Pi); and an input (figures 3 and 6, part input of 35 connected to Pi) coupled to the VSW node (figures 3 and 4, part a switching voltage node at Pi). However, Chen does not expressly disclose a first resistive element selectively coupled between a voltage rail and a switching voltage (VSW) node of the SMPS; and a comparator having an input coupled to the VSW node.
Upadhayaya teaches (see figures 1-8) the detector circuit (figure 5, part detector circuit generated by R5, Q1, R2/R3 and 66) comprises: a first resistive element (figure 5, part R5) selectively (figure 5, part through Q1 and Q3) coupled between a voltage rail (figure 5, part Vin) and a switching voltage (VSW) node of the SMPS (figure 5, part SW); and a comparator (figure 5, part 66) having an input (figure 5, part 66; lower input) coupled to the VSW node (figure 5, part SW; through R2/R3).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the detector circuit of Chen with the detector circuit features as taught by Upadhayaya and obtain the detector circuit comprises: a first resistive element selectively coupled between a voltage rail and a switching voltage (VSW) node of the SMPS; and a comparator having an input coupled to the VSW node, because provides more efficient and accurate detection in order to obtain more efficient control.
Regarding claim 6, Chen and Upadhayaya teach everything claimed as applied above (see claim 4). Further, Chen discloses (see figures 1-7) the detector circuit (figure 3, part 35) further comprises detect (figure 3, part 35) the presence of the one or more circuit elements (figure 3, part L1-LN) (paragraph [0026]; determining whether the inductors L1˜L4 in each phase exist or not, by determining whether the input ends P1˜PM and the input voltage VIN are conducted or not (open), so as to make the control circuit 33 determine whether to control conduction/cut-off status of the switching circuits SW1˜SW4 at each phase. That is, when the detecting circuit 35 of the instant disclosure determines that the inductors L3˜L4 do not exist), and during voltage regulation via the SMPS (figure 3, part 3). However, Chen does not expressly disclose a switch coupled in series with the first resistive element, wherein the switch is configured to be closed to detect the presence of the one or more circuit elements, and wherein the switch is configured to be open during voltage regulation via the SMPS.
Upadhayaya teaches (see figures 1-8) the detector circuit (figure 5, part detector circuit generated by R5, Q1, R2/R3 and 66) further comprises a switch (figure 5, part Q1) coupled in series with the first resistive element (figure 5, part R5), wherein the switch is configured to be closed (figure 5, part Q1; closed), and wherein the switch is configured to be open (figure 5, part Q1; open).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the detector circuit of Chen with the detector circuit features as taught by Upadhayaya and obtain the detector circuit further comprises a switch coupled in series with the first resistive element, wherein the switch is configured to be closed to detect the presence of the one or more circuit elements, and wherein the switch is configured to be open during voltage regulation via the SMPS, because provides more efficient and accurate detection in order to obtain more efficient control.
Regarding claim 13, claim 4 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons.
Regarding claim 15, claim 6 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons.
Claims 5 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2016/0261184), hereinafter Chen, in view of Upadhayaya (US 2021/0408911), and further in view of Hartular et al. (US 2002/0015319), hereinafter Hartular.
Regarding claim 5, Chen and Upadhayaya teach everything claimed as applied above (see claim 4). Further, Chen discloses (see figures 1-7) the detector circuit (figure 3, part 35). However, Chen does not expressly disclose a second resistive element selectively coupled between an output node of the SMPS and a reference potential node of the SMPS.
Hartular teaches (see figures 1-6) the detector circuit (figure 3, part detector circuit generated by 182, 58’ and 74b’) further comprises a second resistive element (figure 3, part 182) selectively coupled (figure 3, part through 58’) between an output node of the SMPS (figure 3, part output node at Vout) and a reference potential node of the SMPS (figure 3, part ground 36’).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the combination of Chen and Upadhayaya with the detector circuit features as taught by Hartular and obtain the detector circuit further comprises a second resistive element selectively coupled between an output node of the SMPS and a reference potential node of the SMPS, because provides more accurate measurement of the circuit status.
Regarding claim 14, claim 5 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons.
Claims 8 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2016/0261184), hereinafter Chen, in view of You et al. (US 2023/0057705), hereinafter You.
Regarding claim 8, Chen discloses everything claimed as applied above (see claim 1). Further, Chen discloses (see figures 1-7) the controller (figure 3, part 33 is further configured to obtain a notification (figure 3, part T1 from 35) of the number of the one or more circuit elements (figure 3, part L1-LN) that are present (paragraphs [0022]-[0026]; The detecting circuit 35 is coupled between each of the input ends P1˜PM and the control circuit 33. The detecting circuit 35 detects the conduction status of each of the input ends P1˜PM, for outputting a first control signal T1 accordingly. Then, the control circuit 33 selectively controls at least one of the switching circuits SW1˜SWM according to the first control signal T1… the main concept of the multi-phase boost converter 3 in the instant disclosure is determining whether the inductors L1˜L4 in each phase exist or not, by determining whether the input ends P1˜PM and the input voltage VIN are conducted or not (open), so as to make the control circuit 33 determine whether to control conduction/cut-off status of the switching circuits SW1˜SW4 at each phase. That is, when the detecting circuit 35 of the instant disclosure determines that the inductors L3˜L4 do not exist (indicated by only switching circuits SW1˜SW2 respectively coupling to inductors L1˜L2 as inputs), the detecting circuit 35 will output the related first control signal T1 to inform the control circuit 33 for turning-off the control of the switching circuit SW3˜SW4 corresponding to the phases not required to be switched). However, Chen does not expressly disclose the controller is further configured to output a notification of the number of the one or more circuit elements that are present.
You teaches (see figures 1-13) the controller (figure 2, part 140) is further configured to output a notification (figure 2, part 149) of the number of the one or more circuit elements that are failure (figure 2, parts 221-1 to 22N-1) (paragraph [0094]; the management resource 141 generates the status information 149 to indicate a respective identity (such as winding 221-1 as in FIG. 4) of the winding that experiences the short circuit condition. When tested individually, in a manner as previously discussed, the management resource 141 determines when any respective winding of the secondary windings 221-1, 221-2, etc., experiences a respective short circuit failure).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the controller of Chen with the notification features as taught by You and obtain the controller is further configured to output a notification of the number of the one or more circuit elements that are present, because it provides health status of the circuit in efficient manner in order to obtain more efficient management of system operation (paragraph [0026]).
Regarding claim 17, claim 8 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2016/0261184), hereinafter Chen, in view of Lu et al. (US 2022/0006376), hereinafter Lu, and further in view of You et al. (US 2023/0057705), hereinafter You.
Regarding claim 20, Chen and Lu teach everything claimed as applied above (see claim 18). Further, Chen discloses (see figures 1-7) the controller (figure 3, part 33 is further configured to obtain a notification (figure 3, part T1 from 35) of the number of the one or more circuit elements (figure 3, part L1-LN) that are present (paragraphs [0022]-[0026]; The detecting circuit 35 is coupled between each of the input ends P1˜PM and the control circuit 33. The detecting circuit 35 detects the conduction status of each of the input ends P1˜PM, for outputting a first control signal T1 accordingly. Then, the control circuit 33 selectively controls at least one of the switching circuits SW1˜SWM according to the first control signal T1… the main concept of the multi-phase boost converter 3 in the instant disclosure is determining whether the inductors L1˜L4 in each phase exist or not, by determining whether the input ends P1˜PM and the input voltage VIN are conducted or not (open), so as to make the control circuit 33 determine whether to control conduction/cut-off status of the switching circuits SW1˜SW4 at each phase. That is, when the detecting circuit 35 of the instant disclosure determines that the inductors L3˜L4 do not exist (indicated by only switching circuits SW1˜SW2 respectively coupling to inductors L1˜L2 as inputs), the detecting circuit 35 will output the related first control signal T1 to inform the control circuit 33 for turning-off the control of the switching circuit SW3˜SW4 corresponding to the phases not required to be switched). However, Chen does not expressly disclose the one or more processors are further configured to output a notification of the number of the one or more circuit elements that are present.
Lu teaches (see figures 1-12) the one or more processors (figure 2, parts 201/206) (paragraphs [0054]-[0061]).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the apparatus for voltage regulation of Chen with the memory and processor features as taught by Lu, because the combination result in more efficient voltage regulation for a processor system with prevention of wrong operation (paragraph [0004]).
You teaches (see figures 1-13) the one or more processors (figure 2, part 140) are further configured to output a notification (figure 2, part 149) of the number of the one or more circuit elements that are failure (figure 2, parts 221-1 to 22N-1) (paragraph [0094]; the management resource 141 generates the status information 149 to indicate a respective identity (such as winding 221-1 as in FIG. 4) of the winding that experiences the short circuit condition. When tested individually, in a manner as previously discussed, the management resource 141 determines when any respective winding of the secondary windings 221-1, 221-2, etc., experiences a respective short circuit failure).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the combination of Chen and Lu with the notification features as taught by You and obtain the one or more processors are further configured to output a notification of the number of the one or more circuit elements that are present, because it provides health status of the circuit in efficient manner in order to obtain more efficient management of system operation (paragraph [0026]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Carlos O. Rivera-Pérez, whose telephone number is (571) 272-2432 and fax is (571) 273-2432. The examiner can normally be reached on Monday through Friday, 8:30 AM – 5:00 PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V. Tran can be reached on (571) 270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/C.O.R. /
Examiner, Art Unit 2838
/THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838