CTNF 18/610,917 CTNF 91316 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1 and 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over CHANG et al. "A 2.5GHz 32nm 0.35mm 2 3.5dB NF 5dBm P1dB fully differential CMOS push-pull LNA with integrated 34dBm T/R switch and ESD protection" (NPL cited by Applicants) in view of Ayranci et al. (US 2024/0007060 and Ayranci hereinafter) . Regarding claim 1, Chang discloses a system [see fig. 3.3.3] comprising: a low-noise amplifier (LNA) comprising: a first transistor [M1p], wherein a gate of the first transistor is coupled to a first input of the LNA [RXINP]; a second transistor [M10], wherein a gate of the second transistor is coupled to a second input of the LNA [RXINN]; a load [load coupled to OUTP/OUTN] coupled to a drain of the first transistor [drain M1p] and a drain of the second transistor [drain M1n]; a first reactive impedance matching network [formed by Ls1p, M1p, Lgp] comprising a first inductor [Ls1p] and a second inductor [Lgp] inductively coupled with the first inductor, wherein the first inductor is coupled to a source of the first transistor [source M1p], and the second inductor [Lgp] is coupled to the gate of the first transistor; a second reactive impedance matching network [Ls1n, M1n, Lgn, M1n] comprising a third inductor [Ls1n] and a fourth inductor [Lgn] inductively coupled with the third inductor, wherein the third inductor is coupled to a source of the second transistor [source M1n], and the fourth inductor is coupled to the gate of the second transistor [gate M1n]. Chang does not explicitly disclose a switching circuit configured to enable or disable each of the first reactive impedance matching network and the second reactive impedance matching network. However, Ayranci discloses switching circuit [Sw1-Sw5, fig. 7] configured to enable or disable reactive impedance matching network [102a]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the invention of Chang by incorporating the switching circuit as taught in Ayranci in order to improve impedance matching network. Regarding claim 10, Chang in view of Ayranci discloses wherein the LNA further comprises a third transistor [M3p], a source of the third transistor is coupled to the drain of the first transistor and the drain of the second transistor, a gate of the third transistor [gate M3p] is coupled to a bias circuit [circuit generates Vbgn], and the load is coupled between a supply rail [gnd] and a drain of the third transistor [drain M3p]. Regarding claim 11, Chang in view of Ayranci discloses [see fig. 3.3.1] wherein the load comprises a transformer [transformer connected to output] including a fifth inductor and a sixth inductor [inductors in the transformer] inductively coupled with the fifth inductor, wherein the fifth inductor is coupled between the supply rail and the drain of the third transistor, and the sixth inductor is coupled between a first output of the LNA and a second output of the LNA [fig. 3.3.1] . 07-21-aia AIA Claim s 2-4 and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over CHANG et al. in view of Ayranci et al . Regarding claims 2 and 3, Chang in view of Ayranci discloses all the features with respect to claim 1 as outlined above. Chang in view of Ayranci further discloses [see fig. 3.3.3] wherein the switching circuit comprises: a first switch [Sw3] coupled between the first inductor and a ground [gnd]; a second switch [Sw4] coupled between the second inductor and the ground. Chang in view of Ayranci does not discloses a third switch coupled between the third inductor and the ground; and a fourth switch coupled between the fourth inductor and the ground. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the invention of Chang in view of Ayranci applying a third switch coupled between the third inductor and the ground; and a fourth switch coupled between the fourth inductor and the ground. However, these additional features is a predictable implementation of the same switch control already taught by Ayranci for the purpose of improving impedance matching network. Regarding claim 4, Chang in view of Ayranci discloses further comprising: a first pad [fig. 3.3.1]; a second pad coupled to the second input of the LNA [fig. 3.3.1]; a power amplifier (PA) [transformer coupled to the power AP]; and a transformer [fig. 3.3.1] including a fifth inductor and a sixth inductor [connected to output inductor] inductively coupled with the fifth inductor, wherein the fifth inductor is coupled between a first output of the PA and a second output of the PA [inductor connected to PA first and second output], and the sixth inductor is coupled between the first pad and the first input of the LNA. Regarding claim 16, Chang in view of Ayranci discloses [see fig. 3.3.1], wherein the system is integrated on a chip. Regarding claim 17, Chang discloses a system [see fig. 3.3.3] comprising: a low-noise amplifier (LNA) comprising: a first transistor [M1p], wherein a gate of the first transistor [gate M1p] is coupled to a first input of the LNA [RXINP]; a first inductor [Ls1p]; a second inductor [Lgp] inductively coupled with the first inductor; a second transistor [M1n], wherein a gate of the second transistor [gate M1n] is coupled to a second input of the LNA [RXINN]; a third inductor [Ls1n]; a fourth inductor [Lgn] inductively coupled with the third inductor; and a load [load coupled to OUTP/OUTN] coupled to a drain of the first transistor [drain M1p] and a drain of the second transistor [drain M10]. Chang does not disclose a first switch, wherein the first inductor and the first switch are coupled in series between a source of the first transistor and a ground; a second switch, wherein the second inductor and the second switch are coupled in series between the gate of the first transistor and the ground; a third switch, wherein the third inductor and the third switch are coupled in series between a source of the second transistor and the ground; a fourth switch, wherein the fourth inductor and the fourth switch are coupled in series between the gate of the second transistor and the ground. However, Ayranci discloses [see fig. 7] a first switch [Sw3], wherein a first inductor [Lsb] and the first switch are coupled in series between a source of the first transistor [source transistor in 104, fig. 2] and a ground; a second switch [Sw4], wherein a second inductor [LG] and the second switch are coupled in series between a gate of the first transistor [gate transistor in 104, fig. 2] and the ground. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the invention of Chang by incorporating the first and second switch as taught in Ayranci in order to improve impedance matching network. Chang in view of Ayranci does not discloses a third switch, wherein the third inductor and the third switch are coupled in series between a source of the second transistor and the ground; a fourth switch, wherein the fourth inductor and the fourth switch are coupled in series between the gate of the second transistor and the ground. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the invention of Chang in view of Ayranci applying a third switch, wherein the third inductor and the third switch are coupled in series between a source of the second transistor and the ground; a fourth switch, wherein the fourth inductor and the fourth switch are coupled in series between the gate of the second transistor and the ground. However, these additional features are a predictable implementation of the same switch control already taught by Ayranci for the purpose of improving impedance matching network. Regarding claim 18, Chang in view of Ayranci discloses [see fig. 7] wherein the LNA further comprises: a fifth inductor [Lsa]; and a fifth switch [Sw2], wherein the fifth inductor and the fifth switch are coupled in series between the source of the second transistor and the ground. Regarding claim 19, Chang in view of Ayranci discloses [see fig. 7] wherein the LNA further comprises a shunt switch [Sw2] coupled between a tap on the third inductor [Lsa] and the ground. Regarding claim 20, Chang in view of Ayranci discloses [see fig. 3.3.1] a first pad [first pad connected to Balun]; a second pad [[first pad connected to Balun]] coupled to the second input of the LNA; a power amplifier [PA]; and a transformer [transformer connected to PA] including a fifth inductor [inductor in transformer connected to PA] and a sixth inductor [inductor in transformer] inductively coupled with the fifth inductor, wherein the fifth inductor is coupled between a first output of the PA and a second output of the PA [inductor connected to PA first and second input], and the sixth inductor is coupled between the first pad and the first input of the LNA . 07-21-aia AIA Claim s 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over CHANG et al. in view of Ayranci et al. further in view of Hassan et al. (US 2022/0158343 and Hassan hereinafter) . Regarding claim 5, Chang in view of Ayranci discloses all the features with respect to claim 4 as outlined above. Chang in view of Ayranci does not explicitly disclose a switch coupled between the sixth inductor and a ground. However, Hassan discloses [see fig. 6] a switch [480] coupled between an inductor [450] and a ground [gnd]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the invention of Chang/Ayranci by incorporating the switch as taught in Hassan in order to improves power loss. Regarding claim 6, Chang in view of Ayranci discloses all the features with respect to claim 4 as outlined above. Chang in view of Ayranci does not explicitly disclose further comprising: an antenna; and a switch coupled to the antenna, the first pad, and the second pad, wherein the switch is configured to couple the antenna to the first pad or the second pad. However, Hassan discloses [see fig. 6] an antenna [22]; and a switch [475] coupled to the antenna, a first pad [620], and a second pad [630], wherein the switch is configured to couple the antenna to the first pad or the second pad. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the invention of Chang/Ayranci by incorporating the switch as taught in Hassan in order to improves power loss . 07-21-aia AIA Claim s 12-15 are rejected under 35 U.S.C. 103 as being unpatentable over CHANG et al. in view of Ayranci et al. further in view of Liang et al. “Design and Analysis of CMOS LNAs with Transformer Feedback for Wideband Input Matching and Noise Cancellation” (NPL cited by Applicants) . Regarding claims 12-15, Chang in view of Ayranci discloses all the features with respect to claim 1 as outlined above. Chang in view of Ayranci does not explicitly disclose wherein: the second inductor comprises a first spiral inductor; the fourth inductor comprises a second spiral inductor; and the first spiral inductor is located within an area enclosed by the second spiral inductor; wherein: the first inductor comprises a first loop inductor; the third inductor comprises a second loop inductor; and the first loop inductor is located within the second loop inductor; wherein the third inductor further comprises a third loop inductor coupled in parallel with the second loop inductor, wherein: the second inductor comprises a first spiral inductor; and the fourth inductor comprises a second spiral inductor interleaved with the first spiral inductor. However, Liang disclose [fig. 7b] discloses a transformer layout the primary and the secondary coils are interleaved inductors. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the invention of Chang/Ayranci by incorporating the switch as taught in Liang in order to maximize the coupling and save chip area . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 7-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to METASEBIA T RETEBO whose telephone number is (571)272-9299. The examiner can normally be reached M - F 8:30 - 5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Regis Betsch can be reached at 571-270-7101. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /METASEBIA T RETEBO/ Primary Examiner, Art Unit 2836 Application/Control Number: 18/610,917 Page 2 Art Unit: 2836 Application/Control Number: 18/610,917 Page 3 Art Unit: 2836 Application/Control Number: 18/610,917 Page 4 Art Unit: 2836 Application/Control Number: 18/610,917 Page 5 Art Unit: 2836 Application/Control Number: 18/610,917 Page 6 Art Unit: 2836 Application/Control Number: 18/610,917 Page 7 Art Unit: 2836 Application/Control Number: 18/610,917 Page 8 Art Unit: 2836 Application/Control Number: 18/610,917 Page 9 Art Unit: 2836
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