Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 7, 8, 10-15, 17-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by LEE (US 20160065139 A1), hereafter referred to as “Lee”.
Regarding claims 1, 8, 11, 15 and 18, in the embodiment of Figs. 2, 7, and 8, Lee discloses:
a signal processing circuit (Figs. 1, 2, 7, and 8, RF integrated circuit RF IC, per claim 18) configured to process a radio-frequency signal;
a radio-frequency circuit including a power amplifier (RF PA 210, per claim 18) that is configured to amplify the radio-frequency signal;
A tracker circuit (Figs. 2, 7 and 8, supply modulator (SM) used for radio transmitters in communication systems per paragraph [0003]), comprising:
an analog envelope tracking (A-ET) circuit (the linear regulator 204 and switching regulator 205 form the analog envelope tracking circuit) configured to generate a continuously varying voltage (paragraph [0047], output voltage from linear regulator 204 in the ET (Envelope Tracking) mode straight to the RF PA 210 via switch 207) that is associated with an envelope of a signal (per paragraph [0048]) to be amplified by the power amplifier (RF PA 210);
a voltage generating circuit (buck booster 203) configured to generate a peak voltage (output voltage straight to RF PA 210 via switch 207 per paragraph [0047]) that is higher than a maximum voltage value of the continuously varying voltage; and
an output switching circuit (switch 207) configured to receive the continuously varying voltage and the peak voltage (per paragraphs [0047]-[0048]),
wherein the output switching circuit is configured to, when an envelope value of the signal to be amplified by the power amplifier is smaller than a threshold (a predetermined value per paragraph [0014], RF PA operates in average power tracking (APT) or envelope tracking (ET) mode depending on the output is less or greater than a predetermined value), output the continuously varying voltage to the power amplifier as a first supply voltage of the power amplifier, and
when the envelope value is greater than the threshold, output the peak voltage to the power amplifier as the first supply voltage of the power amplifier (per paragraph [0014], RF PA operates in ET mode when output power is greater than the predetermined value), wherein the tracker circuit includes
a control terminal configured to receive a data signal for controlling the output switching circuit, the data signal being generated based on the signal to be amplified by the power amplifier (paragraph [0047] lines 6-7, contact of the switch 207 is controlled by an external control signal per claims 8 and 15), and to select one of the peak voltage and the continuously varying voltage based on the data signal (paragraph [0066] and [0068], switch 207 connected to buck booster or combiner 208 (connected to linear regulator and switching regulator) depending on the operating mode, per claim 15).
Regarding claims 2, 12, 13, and 19, in the embodiment of Figs. 2, 7, and 8, Lee discloses:
the A-ET circuit includes an amplifier (paragraph [0008] lines 7-11, SM with both a high bandwidth and efficiency typically employs a hybrid structure in which a linear regulator includes a linear amplifier and switching regulator) that is configured to receive a first voltage as a second supply voltage (paragraph [0048], linear regulator 204 receives a fixed supply voltage from the buck booster 203) of the amplifier and to amplify an envelope signal (Envelope signal shown in Figs. 2, 7, and 8 per paragraph [0048]) corresponding to the envelope of the signal to be amplified by the power amplifier to generate an amplified envelope signal according to the second supply voltage (paragraph [0076] lines 1-9, a low fixed supply voltage causes the envelope signal to be low, when high output power is required the level of the envelope signal increases), and
the A-ET circuit is configured to generate the continuously varying voltage by combining the amplified envelope signal with a second voltage (paragraph [0049], output voltage from linear regulator and signal output from switching regulator are combined at combiner 208 and provides fixed supply voltage at RF PA), wherein
the combining comprises combining the amplified envelope signal with the second voltage by a capacitor (AC coupling capacitor 501 of AC coupling/DC feedback controller 206 connected to output of linear regulator 204 and output gain/offset controller output and combined at combiner 208, per claim 13).
Regarding claim 7 and 14, in the embodiment of Figs. 2, 7, and 8, Lee discloses:
the first voltage is obtained by subtracting the second voltage from a third voltage that is higher than the second voltage (paragraph [0058], comparator 403 outputs a supply voltage Vref of the buck booster 203 by comparing the value from the subtractor 401 with a minimum voltage value), and the peak voltage is higher than the third voltage.
Regarding claim 10, 17 and 20, in the embodiment of Figs. 2, 7, and 8, Lee discloses:
the amplifier is configured to be de-activated when the envelope value is greater than the threshold (paragraph [0066], In APT mode buck booster is disconnected from linear regulator 204 (including a linear amplifier), as linear regulator receives a fixed supply voltage from the buck booster per paragraph [0048], per claims 10, 17, and 20).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over LEE (US 20160065139 A1) in view of Takinami (US 20090191826 A1), hereafter referred to as “LEE” and “Takinami”, respectively.
Regarding claims 3 and 4, in the embodiment of Figs. 2, 7, and 8, LEE discloses:
the A-ET circuit includes:
a first input terminal configured to receive the first voltage (input of linear regulator 204 receiving a fixed supply voltage from the buck booster 203 per [0048]);
a second input terminal configured to receive the second voltage (input terminal of feedback controller 206 receiving a reference value from gain/offset controller 201 per paragraph [0061]);
a third input terminal configured to receive the envelope signal (input terminal connected to Envelope signal, as shown in Figs. 2, 7, and 8);
a first output terminal (output terminal at combiner 208) configured to output the continuously varying voltage; and
the amplifier (paragraph [0008] lines 7-11, SM with both a high bandwidth and efficiency typically employs a hybrid structure in which a linear regulator includes a linear amplifier and switching regulator) and a second output terminal (output of linear regulator 204) coupled to the first output terminal; and
the second input terminal is coupled to the first output terminal (input at 206 is connected to combiner 208); and wherein the
A-ET circuit includes a capacitor (AC coupling capacitor 501 of AC coupling/DC feedback controller 206) that connects the first output terminal to the second output terminal, combining the amplified envelope signal with the second voltage (output terminal at combiner 208 and linear regulator output per claim 4);
However, Lee is silent in teaching the amplifier includes a power supply terminal coupled to the first input terminal, a fourth input terminal coupled to the third input terminal.
Takinami teaches:
the amplifier includes a power supply terminal (Fig. 8, Vsupply connected to 806) coupled to the first input terminal (input to linear regulator 808), a fourth input terminal (Fig. 5 and 8, positive input of 506/808) coupled to the third input terminal (envelope signal Venv, shown in Fig. 8).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify the amplifier in the linear regulator as taught by Lee (Figs. 2, 7 and 8, paragraph [0008]) with the linear amplifier configuration, such as the amplifier in the linear regulator taught by Takinami (Fig. 8) to track amplitude variations in the envelope signal (paragraph [0026] lines 4-9), especially since the linear regulator would have performed the same function as the linear regulator taught by Lee, thereby suggesting the obviousness of such a modification.
Claims 9 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over LEE (US 20160065139 A1) and Takinami (US 20090191826 A1) in further view of Jiang (US 20150236654 A1), hereafter referred to as “LEE”, “Takinami”, and “Jiang”, respectively.
Regarding claims 9 and 16, Lee discloses:
the output switching circuit and the power amplifier the output as the first supply voltage of the power amplifier (Lee, paragraph [0049]).
However Lee and Takinami is silent in teaching a filter circuit coupled between the output switching circuit and the power amplifier, filtering an output of the output switching circuit.
Jiang teaches:
a filter circuit coupled between the output switching circuit and the power amplifier, filtering an output of the output switching circuit (Fig. 2, LC Filter 208, shown between output switchers 206 and PA 108).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention for the tracker circuit as taught by Lee (Figs. 2, 7 and 8) to further include a filter circuit, such as the LC Filter in the tracking circuit taught by Jiang (Fig. 2) to have an adjustable output voltage (paragraph [0033] lines 1-3), thereby suggesting the obviousness of such a combination.
Allowable Subject Matter
Claims 5 and 6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 5 and 6:
the cited prior art of record, LEE (US 20160065139 A1), either singly or in proper combination, does not teach or make obvious, along with the other claimed features, “the voltage generating circuit includes:
a first converter configured to convert an input voltage into the peak voltage;
a second converter configured to convert the input voltage into the first voltage; and a third converter configured to convert the input voltage into the second voltage”, per claim 5, and
“the voltage generating circuit includes a switched capacitor circuit configured to receive an input voltage and to generate the peak voltage, the first voltage, and the second voltage according to the input voltage” per claim 6.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MALANE LIENG whose telephone number is (571) 272-5739. The examiner can normally be reached Monday-Friday 6:30 - 4:00 CST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Baltzell can be reached at (571) 272-5918. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Malane Lieng/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843
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