Detailed Action
Summary
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1. This office action is in response to the application filed on March 20, 2024.
2. Claims 1-17 are pending and has been examined.
Information Disclosure Statement
3. The information disclosure statement (IDS) submitted on 08/11/2024 and 03/20/2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
4. The drawings submitted on 03/20/2024 are acceptable
Claim Rejections - 35 USC § 102
5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2,4-8, 14-15 and 17 are rejected under 35 U.S.C. 102(a)(1) (a)(2) as being anticipated by Wong “9740225”.
In re to claim 1, Wong discloses a power supply circuit (Fig. 4 shows an LDO regulator circuit supplying power to the output) comprising:
a first transistor (Fig. 4 shows M2,432) including a source coupled to an input voltage (Vin) node ( VDD node, 402) and a drain coupled to an output voltage (Vout) node (Vout node, 410) ;
a second transistor (M0, 416) including a drain coupled to a gate of the first transistor (drain of 416 is coupled to the gate of transistor 432 via resistor R1);
a third transistor (414) including a drain coupled to the drain of the second transistor and to the gate of the first transistor (drain of 414 is coupled to the drain of 416 and to the gate of the first transistor 432 via resistor R1) , wherein a source of the third transistor (414) is coupled to a reference potential node of the power supply circuit (ground);
an amplifier (A1,412) including a first input coupled to a reference voltage (Vref) node (Vref, 404) and an output coupled to a gate of the third transistor (414) ; and
a voltage offset circuit (capacitor 430 and resistor 428 form a lead-lag pole-zero pair and are configured to compensate a voltage difference between the gate voltage of 416 and 432 of the current mirror, thus equivalent to voltage offset circuit) coupled between the gate of the first transistor (432) and a gate of the second transistor (416)
In re to claim 2, Wong discloses (Figs. 1-11), wherein the voltage offset circuit (resistor 428 and capacitor 430) comprises a resistive element (428) coupled between the gate of the first transistor (432) and the gate of the second transistor (416).
In re to claim 4, Wong discloses (Figs. 1-11),wherein the voltage offset circuit (resistor, R 428 and capacitor 430) is configured to generate an offset voltage to effectively offset a gate voltage of the second transistor from a gate voltage of the first transistor (transistor 416 and 432 are configured as a current mirror. When the gate voltage of the 416 changes quickly , the voltage on the gate of the pass transistor is kept at its previous value by the capacitor (430) , a voltage drop appears on the resistor (428), thus creating a current flowing through it, charging/discharging the capacitor (430) . If , e.g the gate voltage of 416 abruptly falls, the capacitor (430) source a current that flows through the resistor (428), generating the voltage offset)
In re to claim 5, Wong discloses (Figs. 1-11), wherein the offset voltage of the voltage offset circuit (430 and 428) is sufficiently high such that a pole associated with the gate of the first transistor is outside a loop bandwidth for the power supply circuit (resistor 428 and capacitor 430 inserted to effectively move the pole associated with the pass transistor outside the loop bandwidth of LDO and therefore improve the stability of the feedback loop circuit, see col. 12, lines 1-58).
In re to claim 6, Wong discloses (Fig. 4), wherein the power supply circuit comprises a low-dropout (LDO) regulator (LDO 400) and wherein the first transistor is a pass transistor of the LDO regulator (432 is a pass transistor see Col. 11, lines 38-40) .
In re to claim 7, Wong discloses (Figs. 1-11), wherein the first transistor comprises a p-type metal-oxide-semiconductor field-effect transistor (MOSFET) (432 is P-Type MOSFET), wherein the second transistor is a same type of p-type MOSFET as the first transistor (416 is P-Type MOSFET), and wherein the second transistor is disposed adjacent to the first transistor (transistor 432 is disposed adjacently/next to transistor 416).
In re to claim 8, Wong discloses (Figs. 1-11), further comprising a voltage divider (resistor 420 and a resistor 422) coupled between the Vout node (resistor 420 is coupled to Vout node) and the reference potential node (resistor 422 is coupled to ground), wherein a tap of the voltage divider (connection node between resistor 420 and a resistor 422) is coupled to a second input of the amplifier (Vfb is coupled to negative terminal of 412).
In re to claim 14, Wong discloses (Fig. 4), A low-dropout (LDO) voltage regulator (Figs. 4 shows a LDO regulator circuit 400) comprising a skewed current mirror (transistor 416, and 432 are configured as a current mirror), wherein: the skewed current mirror (416 and 432) is configured to have an offset voltage (capacitor 430 and resistor 428 form a lead-flag pole-zero pair and are configured to compensate a voltage difference between the gate voltage of 416 and 432 of the current mirror, thus equivalent to voltage offset voltage) between a gate of a first transistor (416) in a first branch (first branch being the branch of 414 and 416) of the skewed current mirror and a gate of a second transistor (432) in a second branch (second branch being the branch of transistor 432) of the skewed current mirror (416 and 432) ; and the second transistor (432) is a pass transistor of the LDO voltage regulator (432 is a pass transistor, see col. 11, lines 39-40).
In re to claim 15, Wong discloses (Fig. 4), wherein the skewed current mirror (416 and 432) comprises a resistive element (428) coupled between the gate of the first transistor (416) and the gate of the second transistor (432) .
In re to claim 17, Wong discloses (Fig. 4), wherein the first transistor comprises a p-type metal-oxide-semiconductor field-effect transistor (MOSFET) (M2, 432 is P-Type MOSFET), wherein the second transistor is a same type of p-type MOSFET as the first transistor (M0, 416 is P-Type MOSFET), and wherein the second transistor is disposed adjacent to the first transistor ( Examiner noted that transistor 432 is adjacent to transistor 416).
Claims 9-10 and 12-13 are rejected under 35 U.S.C. 102(a)(1) (a)(2) as being anticipated by Wu “10545523”.
In re to claim 9, Wu discloses a method of supplying power (Figs. 5 and 7 shows an LDO regulator 510 is configured to supply power to the output) , the method comprising:
driving a gate of a first transistor (Figs. 5 and 7 shows bias driving gate of transistor 320) to control a first current (current flowing thru transistor 530) in a first branch (the first branch being the branch of 530) of a current mirror (current mirror 530 and 120 are configured as a current mirror);
generating an offset voltage (by a means of voltage source 520 ) between a gate and a drain of a second transistor (530) in the first branch of the current mirror (530 and 120); and
generating a second current (current flowing thru 120) in a second branch (second branch being the branch of 120) of the current mirror based on the first current (530), wherein a gate voltage of a third transistor (120) in the second branch of the current mirror is higher than a gate voltage of the second transistor by the offset voltage (Fig 5 shows signs + and – of 520 and Fig. 7 shows a detail view of the circuit generating offset voltage source 520 , wherein the current (Is) shows that the voltage on the gate of 120 is configured to receive from + sign/positive voltage higher than the voltage on the gate of 530 is configured to receive – sign/negative voltage); .
In re to claim 10, Wu discloses (Figs. 5 and 7), wherein generating the offset voltage comprises at least one of sinking or sourcing a bias current through a resistive element coupled between the gate and the drain of the second transistor (Fig. 7 shows current sinking 720 is coupled between resistor Rg and gate of 530 and current source 710 is generate current to flow thru a resistor coupled between the gate and drain of 530)
In re to claim 12, Wu discloses (Figs. 5 and 7); wherein the third transistor (120) is a pass transistor of a low-dropout (LDO) regulator (LDO 510) , wherein a source of the third transistor (source of 120 ) is coupled to an input voltage node of the LDO regulator (VDD), and wherein a drain of the third transistor is coupled to an output voltage node of the LDO regulator (output voltage at the Cload node) .
In re to claim 13, Wu discloses (Figs. 5 and 7); wherein the second transistor comprises a p-type metal-oxide-semiconductor field-effect transistor (MOSFET) (transistor 530 is PMOSFET) , wherein the third transistor is a same type of p-type MOSFET as the second transistor (transistor 120 is PMOSFET) , and wherein the second transistor is disposed adjacent to the third transistor (transistor 530 and 120 are disposed adjacently/ next each other) .
Claim Rejections - 35 USC § 103
6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Wong “9740225” in a view of Wu “10545523”.
In re to claim 3, Wong discloses (Figs. 1-11) , wherein the voltage offset circuit (resistor 428 and capacitor 430) but fails to discloses comprises at least one of a: a current sink coupled between the gate of the second transistor and a reference potential node; or a current source coupled between a power supply rail and the gate of the first transistor.
Whereas, Wu discloses LDO regulator (Fig. 7) having a current sink coupled between the gate of the second transistor and a reference potential node; or a current source coupled between a power supply rail and the gate of the first transistor (Fig. 7 shows LDO regulator 510 also includes a load circuit 515 having current source (710) coupled between a power supply rail (Vdd) and the gate of the pass transistor (120) and current sink (720) a current sink (720) coupled between the gate of the second transistor (530) and a reference potential node (ground).
Therefore, it would have been obvious to one of skilled person in the art before the effective filing date of the claimed invention to have modified the LDO of Wang to include the a current sink coupled between the gate of the second transistor and a reference potential node and ; or a current source coupled between a power supply rail and the gate of the first transistor as taught by Wu in order to the improved loop stability over the large current load see col. 6, lines 5-17 .
In re to claim 16, Wong discloses (Figs. 1-11), wherein the skewed current mirror (416 and 432) but fails having a comprises at least one of a: a current sink coupled between the gate of the first transistor and a reference potential node; or a current source coupled between a power supply rail and the gate of the second transistor.
Whereas, Wu discloses LDO regulator (Fig. 7) having a current sink coupled between the gate of the second transistor and a reference potential node; or a current source coupled between a power supply rail and the gate of the first transistor (Fig. 7 shows LDO regulator 510 also includes a load circuit 515 having current source (710) coupled between a power supply rail (Vdd) and the gate of the pass transistor (120) and current sink (720) a current sink (720) coupled between the gate of the second transistor (530) and a reference potential node (ground).
Therefore, it would have been obvious to one of skilled person in the art before the effective filing date of the claimed invention to have modified the LDO of Wang to include the a current sink coupled between the gate of the second transistor and a reference potential node and ; or a current source coupled between a power supply rail and the gate of the first transistor as taught by Wu in order to the improved loop stability over the large current load, see col, 6, lines 5-17.
Allowable Subject Matter
7. Claim 11 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 11 , the prior art of record fails to disclose or suggest the method including the limitation of “ voltage dividing a drain voltage of the third transistor to generate a feedback voltage, wherein the driving comprises driving the gate of the first transistor with an amplifier such that the feedback voltage at a first input of the amplifier is within an amplifier offset voltage of a reference voltage at a second input of the amplifier ”.
Conclusion
8. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Jiang “20240319755” the present disclosure generally relate to electronic circuits and, more particularly, to a power supply circuit and techniques for voltage regulation.
Jiang “20230198394” certain aspects of the present disclosure generally relate to electronic circuits and, more particularly, to a power supply circuit and techniques for voltage regulation.
Sun”11632838” present disclosure relates to a negative feedback circuit. In particular, the present disclosure relates to a negative feedback circuit for reducing a noise signal on a node and on a power rail.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SISAY G TIKU whose telephone number is (571)272-6898. The examiner can normally be reached 8:30AM-6:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tran, Thienvu Vu can be reached on (571) 270-1276.. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SISAY G TIKU/
Primary Examiner, Art Unit 2838