Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 9 is objected to because of the following informalities: Claim 9 depends on claim 4, which has been cancelled. For further prosecution, it will be treated that claim 9 depends on claim 1. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-8 and 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over Hartog (GB 2374780) in view of Seiler (US 20170345122 and further in view of Bu (CN 109144894).
Regarding claim 1, Hartog teaches:
A tile address computation module configured to convert a cache line address into a two-dimensional address based on a stride width, to transform the two-dimensional address into a pixel address, and to compute a tile address using the pixel address and a main memory configuration (Page 5, Paragraph 1, This algorithm translates the scalar memory address initially provided by the operating system or the software application, and that is intended for use with a memory in which the pixel values are linearly arranged);
While Hartog fails to disclose the following, Seiler teaches:
An image attributes cache module coupled to the tile address computation module, the image attributes cache module configured to store one or more image attributes (Paragraph 199, image/texture data stored in the one or more cache(s)).
Seiler and Hartog are both considered to be analogous to the claimed invention because they are in the same field of tiling. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Hartog to incorporate the teachings of Seiler and couple an image cache module to the tile address computation module. Doing so would have allowed for storing additional image information related to the compressed tile address.
While the combination of Hartog and Seiler fails to disclose the following, Bu teaches:
Send the cache line address to a stash/snoop computation module to produce a plurality of remaining cache line addresses while reading and a plurality of remaining cache line addresses while writing (Page 4, Paragraph 6, The invention adds two key module on the memory controller a position mapping module and a memory controller buffer. position mapping module mapping the physical address of the request to the memory with a different encrypted duplicate data block of the plurality of physical addresses. the module will record all key information needed by the address conversion, the address mapping corresponding relation, encryption/decryption, and which blocks are used between the data aggregation technology. besides the location map, we also needs a memory controller buffer to temporarily store some of the data block has been read). Note: Bu teaches that the module provides other addresses during read and write.
Bu and the combination of Hartog and Seiler are both considered to be analogous to the claimed invention because they are in the same field of tiling. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Hartog and Seiler to incorporate the teachings of Bu and provide other addresses during read and write. Doing so would have allowed for storing necessary information needed to efficiently process read and write.
Method claim 10 corresponds to apparatus claim 1. Therefore, claim 10 is rejected for the same reasons as used above.
Regarding claim 2, the combination of Hartog, Seiler, and Bu teaches the apparatus of claim 1. While the combination as previously presented fails to disclose the following, Seiler further teaches:
Wherein the one or more image attributes includes a compression ratio parameter (Paragraph 31, That format is used to compress groups of 2 units, four units, eight units (and so forth) for whatever maximum compression ratio that is specified for a given product).
Seiler and the combination of Hartog and Bu are both considered to be analogous to the claimed invention because they are in the same field of tiling. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Hartog and Bu to incorporate the teachings of Seiler and cache a compression ratio. Doing so would have allowed for effectively and easily decompressing the compressed image.
Method claim 11 corresponds to apparatus claim 2. Therefore, claim 11 is rejected for the same reasons as used above.
Regarding claim 3, the combination of Hartog, Seiler, and Bu teaches the apparatus of claim 1, wherein the two-dimensional address comprises a first dimension address and a second dimension address (Hartog, Page 12, Paragraph 1, initially provided scalar address is first converted to an-x, y rectangular address).
Method claim 12 corresponds to apparatus claim 3. Therefore, claim 12 is rejected for the same reasons as used above.
Regarding claim 5, the combination of Hartog, Seiler, and Bu teaches the apparatus of claim 1. While the combination as presented previously fails to disclose the following, Seiler further teaches:
Wherein the tile address computation module is further configured to receive one or more tile address requests (Paragraph 43, the CG system receives an access request (e.g., read or write) to a memory resource (e.g., a tiled resource)).
Seiler and the combination of Hartog and Bu are both considered to be analogous to the claimed invention because they are in the same field of tiling. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Hartog and Bu to incorporate the teachings of Seiler and receive a tile address request. Doing so would allow for easily accessing the stored tile information.
Regarding claim 6, the combination of Hartog, Seiler, and Bu teaches the apparatus of claim 5. While the combination as presented previously fails to disclose the following, Seiler further teaches:
Wherein the one or more tile address requests includes one or more read requests and one or more write requests (Paragraph 68, This includes ignoring writes and returning a null value, typically all zeros, on reads).
Seiler and the combination of Hartog and Bu are both considered to be analogous to the claimed invention because they are in the same field of tiling. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Hartog and Bu to incorporate the teachings of Seiler and handle both a read request and a write request. Doing so would prevent race conditions, deadlocks, or inconsistent results when reading from or writing to memory.
Regarding claim 7, the combination of Hartog, Seiler, and Bu teaches the apparatus of claim 6. While the combination as presented previously fails to disclose the following, Seiler further teaches:
A tile hazard module coupled to the tile address computation module, the tile hazard module configured to check dependencies between the one or more read requests and the one or more write requests (Paragraph 148, While waiting for data from memory or one of the shared functions, dependency logic within the execution units 1308A-1308N causes a waiting thread to sleep until the requested data has been returned).
Seiler and the combination of Hartog and Bu are both considered to be analogous to the claimed invention because they are in the same field of tiling. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Hartog and Bu to incorporate the teachings of Seiler and handle dependencies between a read request and a write request. Doing so would prevent race conditions, deadlocks, or inconsistent results when reading from or writing to memory.
Regarding claim 8, the combination of Hartog, Seiler, and Bu teaches the apparatus of claim 7. While the combination as presented previously fails to disclose the following, Seiler further teaches:
Wherein the tile hazard module is further configured to segregate the one or more read requests and the one or more write requests (Paragraph 214, the access request being a write operation; Paragraph 225, the access requesting being a read operation). Seiler teaches various workflows that perform different actions depending on the type of request.
Seiler and the combination of Hartog and Bu are both considered to be analogous to the claimed invention because they are in the same field of tiling. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Hartog and Bu to incorporate the teachings of Seiler and segregate a read request and a write request. Doing so would allow for efficiently handling different types of requests to the module.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Hartog in view of Seiler and further in view of Bu as applied to claims 1-3, 5-8 and 10-12 above and further in view of Beard (US 20220327009).
Regarding claim 9, the combination of Hartog, Seiler, and Bu teaches the apparatus of claim 2. While the combination fails to disclose the following, Beard teaches:
Further comprising a stash/snoop address computation module coupled to the image attributes cache module, the stash/snoop address computation module configured to produce a stash address and a snoop address (Paragraph 57, cache stash requests may specify the virtual address and address space identifier registered with it; Paragraph 123, a snoop response 134 indicating the translated physical address).
Beard and the combination of Hartog, Seiler, and Bu are both considered to be analogous to the claimed invention because they are in the same field of tiling. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Hartog, Seiler, and Bu to incorporate the teachings of Beard and produce a stash address and snoop address. Doing so would allow for efficiently tracking the cache requests and responses.
Claims 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Hartog in view of Seiler and further in view of Bu as applied to claims 1-3, 5-8 and 10-12 above and further in view of Champion (US 20020109698).
Regarding claim 13, the combination of Hartog, Seiler, and Bu teaches the method of claim 12. While the combination fails to disclose the following, Champion teaches:
Wherein the stride width measures a memory address distance between consecutive pixels of an image (Paragraph 96, Accordingly, pixel data for vertically adjacent pixels do not have adjacent memory addresses. For example, referring to FIGS. 6A, 6B, and 6C, pixels 0, 8, 16, and 24 are a series of vertically adjacent pixels, forming a vertical column. However, pixel data for pixels 0 and 16 are not at neighboring addresses in first memory device 650 (pixel data for pixels 15 and 18 are at neighboring addresses to pixel data for pixel 16)). Champion teaches calculating the difference between memory addresses for consecutive pixels.
Champion and the combination of Hartog, Seiler, and Bu are both considered to be analogous to the claimed invention because they are in the same field of tiling. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination Hartog, Seiler, and Bu to incorporate the teachings of Champion and use a stride width to measure memory address distance between consecutive pixels of an image. Doing so would allow for determining how to effectively reconstruct/decompress the desired image by determining locations of consecutive pixels.
Regarding claim 14, the combination of Hartog, Seiler, Bu, and Champion teaches the method of claim 13, wherein the first dimension address depends on a remainder function of a ratio between the cache line address and the stride width (Hartog, Page 12, Paragraphs 10-11, The hardware will perform equation (1) backwards to determine the x and y coordinates for use in the tiling algorithm. The hardware subtracts the surface base address from the linear address, and this result is divided by P. The integer portion of the quotient is the y coordinate, and the remainder of the quotient is the x coordinate).
Regarding claim 15, the combination of Hartog, Seiler, Bu, and Champion teaches the method of claim 13, wherein the second dimension address depends on a quotient of the cache line address and the stride width. (Hartog, Page 12, Paragraphs 10-11, The hardware will perform equation (1) backwards to determine the x and y coordinates for use in the tiling algorithm. The hardware subtracts the surface base address from the linear address, and this result is divided by P. The integer portion of the quotient is the y coordinate, and the remainder of the quotient is the x coordinate).
Claims 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Hartog in view of Seiler and further in view of Bu as applied to claims 1-3, 5-8 and 10-12 above and further in view of Berger (US 20220222771).
Regarding claim 16, the combination of Hartog, Seiler, and Bu teaches the method of claim 12. While the combination fails to disclose the following, Berger teaches:
Wherein the pixel address depends on an image format (Paragraph 108, calculating cache virtual pixel addresses for the input image pixel coordinates… virtual address values may be assigned to pixels according to an algorithm such as a standard or technique, for example NV12 format).
Berger and the combination of Hartog, Seiler, and Bu are both considered to be analogous to the claimed invention because they are in the same field of tiling. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Hartog, Seiler, and Bu to incorporate the teachings of Berger and use image format to determine pixel address. Doing so would allow for segregating different areas of memory for different image formats, allowing for more efficient image reconstruction.
Regarding claim 17, the combination of Hartog, Seiler, Bu, and Berger teaches the method of claim 16. While the combination as presented previously fails to disclose the following, Berger further teaches:
Retrieving a compressed tile data from a compressed memory using the tile address (Paragraph 100, receives the addresses (virtual or physical) and then performs the read of the addressed tiles. This may include obtaining multiple tiles on a single read access or cycle, such as four tiles forming a rectangular block, but the tiles could be retrieved in any desired combination that can be handled by the system).
Berger and the combination of Hartog, Seiler, and Bu are both considered to be analogous to the claimed invention because they are in the same field of tiling. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Hartog, Seiler, and Bu to incorporate the teachings of Berger and retrieve compressed tile data using the tile address. Doing so would allow for efficient access to the compressed tile data.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Hartog in view of Seiler and further in view of Bu and further in view of Berger as applied to claims 16-17 above and further in view of Jain (US 20220012592).
Regarding claim 18, the combination of Hartog, Seiler, Bu, and Berger teaches the method of claim 17. While the combination fails to disclose the following, Jain teaches:
Converting the compressed tile data into a cache line data using a decompression process (Paragraph 64, the meta-data cache line 502 indicates a decompression process to be executed for the respective tiles).
Jain and the combination of Hartog, Seiler, Bu, and Berger are both considered to be analogous to the claimed invention because they are in the same field of tiling. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Hartog, Seiler, Bu, and Berger to incorporate the teachings of Jain and convert the compressed tile data into cache line data using a decompression process. Doing so would allow for efficiently reconstructing the compressed tile data using the cache line.
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hartog in view of Jain and further in view of Bu.
Regarding claim 19, Hartog teaches:
A non-transitory computer-readable medium storing computer executable code, operable on a device comprising at least one processor and at least one memory coupled to the at least one processor, wherein the at least one processor is configured to implement processor access to compressed multimedia data, the computer executable code comprising:
Instructions for causing a computer to convert a cache line address into a two-dimensional address based on a stride width (Page 5, Paragraph 1, This algorithm translates the scalar memory address initially provided by the operating system or the software application, and that is intended for use with a memory in which the pixel values are linearly arranged);
Instructions for causing the computer to transform the two-dimensional address into a pixel address (Page 5, Paragraph 1, This algorithm translates the scalar memory address initially provided by the operating system or the software application, and that is intended for use with a memory in which the pixel values are linearly arranged);
Instructions for causing the computer to compute the tile address using the pixel address and a main memory configuration (Page 5, Paragraph 1, This algorithm translates the scalar memory address initially provided by the operating system or the software application, and that is intended for use with a memory in which the pixel values are linearly arranged);
While Hartog fails to disclose the following, Jain teaches:
Instructions for causing the computer to retrieve a compressed tile data from a compressed memory using a tile address (Paragraph 67, the data bridging circuitry 604 can determine the meta-data associated with the tile based on an address of the tile);
Instructions for causing the computer to convert the compressed tile data into a cache line data using a decompression process (Paragraph 64, the meta-data cache line 502 indicates a decompression process to be executed for the respective tiles); and
Instructions for causing the computer to retrieve a memory read request with the cache line address on an input databus (Paragraph 74, the memory 616 includes the meta-data (e.g., the meta-data cache line 502 of FIG. 5) and the tiles associated therewith… the data decompressing circuitry 614 can access the meta-data and the tiles stored in the memory 616 via the bus).
Jain and Hartog are both considered to be analogous to the claimed invention because they are in the same field of tiling. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Hartog to incorporate the teachings of Jain and retrieve compressed tile data using a tile address, convert the compressed tile data into cache line data using a decompression process, and receive a memory read request with the cache line address on an input databus. Doing so would have allowed for efficiently accessing the stored compressed tile data.
While the combination of Hartog and Jain fails to disclose the following, Bu teaches:
Instructions for causing the computer to send the cache line address to produce a plurality of remaining cache line addresses while reading and a plurality of remaining cache line addresses while writing (Page 4, Paragraph 6, The invention adds two key module on the memory controller a position mapping module and a memory controller buffer. position mapping module mapping the physical address of the request to the memory with a different encrypted duplicate data block of the plurality of physical addresses. the module will record all key information needed by the address conversion, the address mapping corresponding relation, encryption/decryption, and which blocks are used between the data aggregation technology. besides the location map, we also needs a memory controller buffer to temporarily store some of the data block has been read). Note: Bu teaches that the module provides other addresses during read and write.
Bu and the combination of Hartog and Jain are both considered to be analogous to the claimed invention because they are in the same field of tiling. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Hartog and Jain to incorporate the teachings of Bu and provide other addresses during read and write. Doing so would have allowed for storing necessary information needed to efficiently process read and write.
Regarding claim 20, the combination of Hartog, Jain, and Bu teaches the apparatus of claim 19, wherein the two-dimensional address comprises a first dimension address wherein the first dimension address depends on a remainder function of a ratio between the cache line address and the stride width, and a second dimension address wherein the second dimension address depends on a quotient of the cache line address and the stride width (Hartog, Page 12, Paragraphs 10-11, The hardware will perform equation (1) backwards to determine the x and y coordinates for use in the tiling algorithm. The hardware subtracts the surface base address from the linear address, and this result is divided by P. The integer portion of the quotient is the y coordinate, and the remainder of the quotient is the x coordinate).
Response to Amendment
Applicant’s arguments with respect to claims 1, 10, and 19 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Bu teaches using a module to map addresses and store addresses in a buffer during read and write as cited above. It would have been obvious to a person of ordinary skill in the art use these teachings and send the cache line address to a stash/snoop computation module and producing remaining cache line addresses during read and write.
Conclusion
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/SNIGDHA SINHA/ Examiner, Art Unit 2619
/JASON CHAN/ Supervisory Patent Examiner, Art Unit 2619
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