Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 3-8 and 13-19 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Cappetta (US 2024/0330677).
Regarding claim 1, Cappetta discloses a system comprising: a first hardware accelerator programmed to accelerate performance of a first stage of a data processing pipeline with respect to input data received from a computing device; and a second hardware accelerator programmed to accelerate performance of a second stage of the data processing pipeline, the second hardware accelerator coupled directly to the first hardware accelerator and configured to receive intermediate data of the data processing pipeline directly from the first hardware accelerator, the second hardware accelerator further configured to transfer final data resulting from the second stage(Paragraph 33, The stream engine 106 provides the feature data to the processing chain. The feature data 116 flows through each hardware accelerator 108 of the processing chain. Each hardware accelerator 108 performs operations on the feature data 116 and provides the feature data to the next hardware accelerator 108 of the processing chain. At the end of the processing chain, the feature data 116 is passed back to the stream engine 106), wherein the first hardware accelerator and the second hardware accelerator are of different types of hardware accelerators having different hardware architectures(Paragraph 29, The hardware accelerators 108 can include convolution accelerators, activation units, pooling units, multiply and accumulate (MAC) units, decompression units, and other types of units).
Regarding claim 3, Cappetta discloses the system of claim 1, wherein the first hardware accelerator is configured to accelerate linear algebra operations as compared to the second hardware accelerator(Paragraph 29, The hardware accelerators 108 can include convolution accelerators, activation units, pooling units, multiply and accumulate (MAC) units, decompression units, and other types of units)).
Regarding claim 4, Cappetta discloses the system of claim 1, wherein the second hardware accelerator is configured to accelerate sequential processing in multiple pipelines as compared to the first hardware accelerator(Paragraph 29, The hardware accelerators 108 can include convolution accelerators, activation units, pooling units, multiply and accumulate (MAC) units, decompression units, and other types of units)).
Regarding claim 5, Cappetta discloses the system of claim 1, wherein the first hardware accelerator is a tensor streaming processor (TSP)(Paragraph 52, the feature data 116 is passed to the processing chain 120 as tensor data. Each hardware accelerator 108 may receive the feature data in a tensor form, may process the feature data, and may provide the processed feature data in a tensor form to the next hardware accelerator 108).
Regarding claim 6, Cappetta discloses the system of claim 1, wherein the second hardware accelerator is a field programmable gate array (FPGA)(Paragraph 103, in some embodiments, some or all of the methods and/or functionality may be implemented or provided in other manners, such as field-programmable gate arrays (FPGAs)).
Regarding claim 7, Cappetta discloses the system of claim 1, further comprising a computing device coupled to the first hardware accelerator and the second hardware accelerator for delivering input data and receiving output data, wherein the first hardware accelerator is a tensor streaming processor (TSP) and the second hardware accelerator is a field programmable gate array (FPGA) (Paragraph 33, The stream engine 106 provides the feature data to the processing chain. The feature data 116 flows through each hardware accelerator 108 of the processing chain. Each hardware accelerator 108 performs operations on the feature data 116 and provides the feature data to the next hardware accelerator 108 of the processing chain. At the end of the processing chain, the feature data 116 is passed back to the stream engine 106, (Paragraph 29, The hardware accelerators 108 can include convolution accelerators, activation units, pooling units, multiply and accumulate (MAC) units, decompression units, and other types of units), )(Paragraph 103, in some embodiments, some or all of the methods and/or functionality may be implemented or provided in other manners, such as field-programmable gate arrays (FPGAs)).
Regarding claim 8, Cappetta discloses the system of claim 1, wherein the first hardware accelerator is coupled to the second hardware accelerator via a chip-to-chip (C2C) connection(Figure 2A, chips 108a connected to chip 108b).
Regarding claim 13, Cappetta discloses the system of claim 1, wherein the computing device comprises: a computing device coupled to the computing device; and at least one memory device, or at least one storage device, or at least one memory device and at least one storage device coupled to the computing device(Paragraphs 102-103, the medium may be a physical storage medium, such as for example a Read Only Memory (ROM) chip, or a disk such as a Digital Versatile Disk (DVD-ROM), Compact Disk (CD-ROM), a hard disk, a memory and in some embodiments, some or all of the methods and/or functionality may be implemented or provided in other manners, such as at least partially in firmware and/or hardware, including, but not limited to one or more application-specific integrated circuits (ASICs), digital signal processors, discrete circuitry, logic gates, standard integrated circuits, controllers (e.g., by executing appropriate instructions, and including microcontrollers and/or embedded controllers)).
Regarding claim 14, Cappetta discloses the system of claim 13, wherein the first hardware accelerator and the second hardware accelerator are coupled to the computing device via a data bus(Figure 2, Hardware accelerators 108 are coupled to the computing device via a bus.).
Claims 15-19 recite similar limitations as claims 1-14 and thus taught by Cappetta, as explained above
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) s 9-12 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cappetta and Liu(US 2020/0304835).
Regarding claim 9, Cappetta discloses the system of claim 1, but does not specifically disclose wherein the first stage implements a lossy compression algorithm and the second stage implements a lossless compression algorithm. However, Cappetta discloses in paragraph 29, the hardware accelerators 108 can include convolution accelerators, activation units, pooling units, multiply and accumulate (MAC) units, decompression units, and other types of units)) and Liu disclose end to end deep architecture for multiple image compression (e.g., stereo image compression) is provided. The architecture can provide implicit depth estimation and compression that are performed jointly in the machine learned image compression model. In this manner, the bit rate of a combined latent code can be lower than the sum of the bit rates if images are compressed separately. This can be achieved using a single image compression model that jointly compresses multiple images such as two stereo images. As much information as possible can be extracted from a first image in order to reduce the bit rate in a second image, such that the total bit rate is lower than the result of independent single image compression. Multilevel, parametric skip functions can be utilized to propagate information from a first image to encoders and/or decoders for a second image in order to reduce the bit rate of the second image. A conditional entropy model can be utilized to model the correlation between image codes of the two images in order to further reduce the bit rate of the image codes. The architecture can be trained end to end to minimize an objective function including terms for encoding a reconstruction quality of both images and providing a rate predicted by the entropy model(Paragraph 41). It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to combine the teachings of Cappetta and Liu to have the first stage implements a lossy compression algorithm and the second stage implements a lossless compression algorithm. The motivation to do so be to reducing data size and bit rate.
Regarding claim 10, Cappetta and Liu disclose the system of claim 9, wherein the lossy compression algorithm is a machine learning model(Liu: Paragraph 41, the machine learned image compression model).
Regarding claim 11, Cappetta and Liu disclose the system of claim 10, wherein the lossy compression algorithm is a learned image compression (LIC) machine learning model(Liu: Paragraph 41, the machine learned image compression model).
Regarding claim 12, Cappetta and Liu disclose the system of claim 9, wherein the lossless compression algorithm is an entropy encoder(Liu: Paragraph 41, A conditional entropy mode).
Regarding claim 20, Cappetta does not specifically disclose wherein processing the input data comprises implementing a learned image compression (LIC) machine learning model and processing the intermediate data comprises implementing an entropy encoding. However, Cappetta discloses in paragraph 29, the hardware accelerators 108 can include convolution accelerators, activation units, pooling units, multiply and accumulate (MAC) units, decompression units, and other types of units)) and Liu disclose end to end deep architecture for multiple image compression (e.g., stereo image compression) is provided. The architecture can provide implicit depth estimation and compression that are performed jointly in the machine learned image compression model. In this manner, the bit rate of a combined latent code can be lower than the sum of the bit rates if images are compressed separately. This can be achieved using a single image compression model that jointly compresses multiple images such as two stereo images. As much information as possible can be extracted from a first image in order to reduce the bit rate in a second image, such that the total bit rate is lower than the result of independent single image compression. Multilevel, parametric skip functions can be utilized to propagate information from a first image to encoders and/or decoders for a second image in order to reduce the bit rate of the second image. A conditional entropy model can be utilized to model the correlation between image codes of the two images in order to further reduce the bit rate of the image codes. The architecture can be trained end to end to minimize an objective function including terms for encoding a reconstruction quality of both images and providing a rate predicted by the entropy model(Paragraph 41). It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to combine the teachings of Cappetta and Liu to have processing the input data comprises implementing a learned image compression (LIC) machine learning model and processing the intermediate data comprises implementing an entropy encoding. The motivation to do so be to reducing data size and bit rate.
Response to Arguments
Applicant's arguments have been fully considered but they are not persuasive. Applicant argues that paragraph 57 of Cappetta does not disclose the first hardware accelerator and the second hardware accelerator are of different types of hardware accelerators having different hardware architectures because the paragraph just discloses a laundry list of accelerators. Examiner respectfully disagrees. Cappetta discloses, in Paragraph 29, The hardware accelerators 108 can include convolution accelerators, activation units, pooling units, multiply and accumulate (MAC) units, decompression units, and other types of units). Cappetta further discloses in Figure 2a, several 108 accelerators(108a, 108b, 108c). In paragraph 50, only accelerator 108b is reconfigured. Thus, considering the whole disclosure, Cappetta discloses first hardware accelerator(e.g. 108a) and the second hardware accelerator(e.g. 108b) are of different types of hardware accelerators having different hardware architectures(Cappetta’s different hardware accelerators have different hardware architectures due to different configurations).
Thus, Applicant’s arguments are not found persuasive.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/NIMESH G PATEL/Primary Examiner, Art Unit 2187
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