DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 3/20/2024 has been considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
A title such as the following is suggested: Voltage regulating circuit with improved temperature invariance.
Claim Objections
Claims 1-9 are objected to because of the following informalities: in claim 1, line 12 should be terminated with a comma. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 16-17 are rejected under 35 U.S.C. 102a1 as being anticipated by Wang (CN 204576336).
With respect to claim 16, Wang discloses a voltage regulation circuit, comprising: an input node (Fig. 1 O) configured to receive an input voltage (Fig. 1 VIN); a voltage reference circuit (Fig. 1 MN1) coupled to ground (Fig. 1 GND), the voltage reference circuit including a first enhancement transistor (Fig. 1 MN1); a current generator circuit (Fig.1 MNd3) coupled between the input node and the voltage reference circuit, the current generator circuit including a first depletion transistor (Fig. 1 MNd3); a voltage divider circuit (Fig. 1 110) coupled to ground; an output stage (Fig. 1 MN2) coupled between the input node and the voltage divider circuit, the output stage including a second depletion transistor (Fig. 1 MN2); and an output node configured to output a regulated voltage (Fig. 1 VR), the output node being between the voltage divider circuit and the output stage.
With respect to claim 17, Wang discloses the voltage regulation circuit according to claim 16, wherein the voltage reference circuit and the current generator circuit are in parallel (Fig. 1 in parallel between VIN and ground) with the voltage divider circuit and the output stage.
Claim(s) 16-17 are rejected under 35 U.S.C. 102a1 as being anticipated by Inoue (US 2020/0264644).
With respect to claim 16, Inoue discloses a voltage regulation circuit (Fig. 7 12), comprising: an input node (Fig. 7 node at Vin) configured to receive an input voltage (Fig. 7 Vin); a voltage reference circuit (Fig. 7 N12) coupled to ground (Fig. 7 ground symbol), the voltage reference circuit including a first enhancement transistor (Fig. 7 N12); a current generator circuit (Fig. 7 N13) coupled between the input node and the voltage reference circuit, the current generator circuit including a first depletion transistor (Fig. 7 N13); a voltage divider circuit (Fig. 7 R11,R12) coupled to ground; an output stage (Fig. 7 N10) coupled between the input node and the voltage divider circuit, the output stage including a second depletion transistor (Fig. 7 N10); and an output node (Fig. 7 node at Vout) configured to output a regulated voltage (Fig. 7 Vout), the output node being between the voltage divider circuit and the output stage.
With respect to claim 17, Inoue discloses the voltage regulation circuit according to claim 16, wherein the voltage reference circuit and the current generator circuit are in parallel (Fig. 7 in parallel between Vin and ground) with the voltage divider circuit and the output stage.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 7, 9, 16-18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Smith (US 8,237,425) in view of Matsumura (US 2024/0321877).
With respect to claim 1, Smith discloses a voltage regulation circuit (Fig. 5 200), comprising: a first circuit branch (Fig. 5 generates Vref) and a second circuit branch (Fig. 5 220, 242,244) in parallel and coupled between an input voltage (Fig. 5 Vcc) and ground (Fig. 5 Gnd), the second circuit branch including an output stage (Fig. 5 220) coupled between the input voltage and an output node (Fig. 5 node Vreg1) on which a regulated voltage (Fig. 5 Vreg1) is output, the output stage including a MOSFET transistor (Fig. 5 220); and a resistive voltage divider (Fig 5 242,244) coupled to the output node, the resistive voltage divider configured to output, on a divider output node (Fig. 5 246), a divided output regulated voltage (Fig. 5 voltage at node 246) that is input as a process variable of a negative feedback loop (Fig. 5 output voltage Vreg1 fedback through 240) coupled to the reference voltage (Fig. 5 Vref and feedback voltage coupled to 210), an output of the negative feedback loop controlling a gate (Fig. 5 224) of the MOSFET transistor (Fig. 5 220) of the output stage. Smith indicates the reference voltage of the first circuit branch is provided by a bandgap generator and does not disclose wherein the first circuit branch contains a depletion MOSFET transistor.
Matsumura discloses a voltage reference generator circuit (Fig. 4 100), comprising: a first circuit branch (Fig. 4 110,115,120,125) coupled between an input voltage (Fig. 4 VDD) and ground (Fig. 4 150), the first circuit branch including a current generator (Fig. 4 110,115) including a first depletion MOSFET transistor (Fig.4 110), which gate source voltage is a Proportional To Absolute Temperature (PTAT) voltage, the input voltage being a direct current (DC) voltage supply; a voltage reference circuit (Fig. 4 120,125) configured to supply a reference voltage (Fig. 4 Vref) that is independent with respect to temperature variations (Fig. 7(a) Δvref_t), the first depletion MOSFET transistor being coupled between the input voltage (Fig. 4 VDD) and the voltage reference circuit (Fig. 4 120,125), the voltage reference circuit including a first enhancement MOSFET transistor (Fig. 4 120), which gate source voltage is a Complementary To Absolute Temperature (CTAT) voltage, a source of the first enhancement MOSFET transistor being coupled to the ground through a source resistor (Fig. 4 125) the reference voltage (Fig. 4 170), which is a sum of the PTAT voltage drop (Fig. 4 I1 x Rb) on the source resistor and the gate source voltage of the first enhancement MOSFET transistor, being formed on the first enhancement MOSFET transistor, the first enhancement MOSFET transistor being arranged on the first circuit branch, a drain of the first enhancement MOSFET transistor being coupled (Fig. 4 170) to the first depletion MOSFET transistor through a control node (Fig. 4 gate 110), the control node being coupled to a gate of the first enhancement MOSFET transistor, the first depletion MOSFET transistor configured to inject a PTAT current in the first circuit branch that determines a PTAT voltage drop on the source resistor. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing of the invention to implement a voltage regulation circuit, comprising: a first circuit branch and a second circuit branch in parallel and coupled between an input voltage and ground, the first circuit branch including a current generator including a first depletion MOSFET transistor, which gate source voltage is a Proportional To Absolute Temperature (PTAT) voltage, the input voltage being a direct current (DC) voltage supply; a voltage reference circuit configured to supply a reference voltage that is independent with respect to temperature variations, the first depletion MOSFET transistor being coupled between the input voltage and the voltage reference circuit, the voltage reference circuit including a first enhancement MOSFET transistor, which gate source voltage is a Complementary To Absolute Temperature (CTAT) voltage, a source of the first enhancement MOSFET transistor being coupled to the ground through a source resistor the reference voltage, which is a sum of the PTAT voltage drop on the source resistor and the gate source voltage of the first enhancement MOSFET transistor, being formed on the first enhancement MOSFET transistor, the first enhancement MOSFET transistor being arranged on the first circuit branch, a drain of the first enhancement MOSFET transistor being coupled to the first depletion MOSFET transistor through a control node, the control node being coupled to a gate of the first enhancement MOSFET transistor, the first depletion MOSFET transistor configured to inject a PTAT current in the first circuit branch that determines a PTAT voltage drop on the source resistor, the second circuit branch including an output stage coupled between the input voltage and an output node on which a regulated voltage is output, the output stage including a MOSFET transistor; and a resistive voltage divider coupled to the output node, the resistive voltage divider configured to output, on a divider output node, a divided output regulated voltage that is input as a process variable of a negative feedback loop coupled to the reference voltage, an output of the negative feedback loop controlling a gate of the MOSFET transistor of the output stage, in order to provide a simple reference voltage circuit with temperature invariance.
With respect to claim 7, Smith in view of Matsumura make obvious the voltage regulation circuit according to claim 1, wherein the negative feedback loop includes a differential amplifier (Smith Fig. 5 210) having inputs coupled to the divider output node (Fig. 5 240) and to the control node (In combination Smith Fig. 5 212 connected to Matsumura Fig. 4 Vref), the gate of the first enhancement MOSFET transistor is coupled to the drain of the first enhancement MOSFET transistor (Fig. 4 120), an output of the differential amplifier being coupled to the gate (Fig. 5 224) of the MOSFET transistor of the output stage.
With respect to claim 9, Smith in view of Matsumura make obvious the voltage regulation circuit according to claim 1, wherein the MOSFET transistor (Fig. 5 220) of the output stage is a second depletion MOSFET transistor (column 4, lines 4-5).
With respect to claim 16, Smith discloses a voltage regulation circuit, comprising: an input node configured to receive an input voltage (Fig. 5 Vcc); a voltage reference circuit (Fig. 5 generates Vref); a voltage divider circuit (Fig. 5 240) coupled to ground (Fig. 5 Gnd); an output stage (Fig. 5 220) coupled between the input node and the voltage divider circuit, the output stage including a second depletion transistor (Fig. 5 220; column 4, lines 4-5); and an output node (Fig. 5 node Vreg1) configured to output a regulated voltage (Fig. 5 Vreg1), the output node being between the voltage divider circuit and the output stage. Smith discloses a bandgap generator creating the reference voltage and does not disclose the generator of Vref comprising a depletion transistor.
Matsumura discloses a voltage reference generator circuit, comprising: a voltage reference circuit (Fig. 4 120,125) coupled to ground (Fig. 4 150), the voltage reference circuit including a first enhancement transistor (Fig. 4 120); a current generator circuit (Fig. 4 110,115) coupled between the input node (Fig. 4 node VDD) and the voltage reference circuit, the current generator circuit including a first depletion transistor (Fig. 4 110). It would have been obvious to one of ordinary skill in the art at the time of filing of the invention to implement a voltage regulation circuit, comprising: an input node configured to receive an input voltage; a voltage reference circuit coupled to ground, the voltage reference circuit including a first enhancement transistor; a current generator circuit coupled between the input node and the voltage reference circuit, the current generator circuit including a first depletion transistor; a voltage divider circuit coupled to ground; an output stage coupled between the input node and the voltage divider circuit, the output stage including a second depletion transistor; and an output node configured to output a regulated voltage, the output node being between the voltage divider circuit and the output stage, in order to provide a simple circuit to generate the reference voltage with temperature invariance.
With respect to claim 17, Smith in view of Matsumura make obvious the voltage regulation circuit according to claim 16, wherein the voltage reference circuit and the current generator circuit (in combination Matusumura Fig. 4 110,115,120,125) are in parallel with the voltage divider circuit and the output stage (Smith Fig. 5 220,242,244).
With respect to claim 18, Smith in view of Matsumura make obvious the voltage regulation circuit according to claim 16, further comprising: a capacitor (Fig. 5 230) coupled between gates (Fig. 4 224) of the first depletion transistor and the second depletion transistor (in combination, Matsumuta Fig. 4 gate 110).
With respect to claim 20, Smith in view of Matsumura make obvious the voltage regulation circuit according to claim 16, further comprising: an amplifier (Fig. 5 210) including a first input (Fig. 5 212) coupled to a node between the voltage reference circuit and the current generator circuit, a second input (Fig. 5 214) coupled to the voltage divider circuit, and an output (Fig. 5 210 output to 220) coupled to the output stage.
Claim(s) 8 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Smith (US 8,237,425) in view of Matsumura (US 2024/0321877) and further in view of Bimbi (Single-Branch Wide-Swing-Cascode Subthreshold GaN Monolithic Voltage Reference).
With respect to claim 8, Smith in view of Matsumura make obvious voltage regulation circuit according to claim 1 as set forth above, and remain silent as to the fabrication technology of the MOSFETs. The use of GaN transistors were well known at the time of filing of the invention.
Bimbi discloses the use of wherein the first and second depletion MOSFET transistors (Fig. 3 QD1,QD2) and the first enhancement MOSFET transistor (Fig. 3 QE3) are Gallium Nitride (GaN) High Electron Mobility Transistors. It would have been obvious to one of ordinary skill in the art at the time of filing of the invention to implement wherein the first and second depletion MOSFET transistors and the first enhancement MOSFET transistor are Gallium Nitride (GaN) High Electron Mobility Transistors, to take advantage of the high temperature capability of the technology.
With respect to claim 19, Smith in view of Matsumura make obvious the voltage regulation circuit according to claim 16 as set forth, and remain silent as to implementing a protection circuit including third depletion transistor coupled between the input node and the first depletion transistor, and a fourth depletion transistor coupled between the input node and the second depletion transistor.
Bimbi discloses a protection circuit including third depletion transistor (Fig. 5 QD2) coupled between the input node (Fig. 5 VDD) and the first depletion transistor (Fig. 5 QD1).It would have been obvious to one of ordinary skill in the art at the time of filing of the invention to implement a protection circuit including third depletion transistor coupled between the input node and the first depletion transistor, and a fourth depletion transistor coupled between the input node and the second depletion transistor, in order to protect the circuit and to decrease the dependence on the supply voltage.
Allowable Subject Matter
Claims 10-15 are allowed while Claims 2-6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and if the claim objections stated above were overcome. The following is an examiner’s statement of reasons for allowance:
With respect to claim 10, the prior art does not disclose or suggest, primarily, the output stage including a second depletion MOSFET transistor coupled to a gate of the first depletion MOSFET transistor; and a resistive voltage divider that couples the output node to a gate of the first enhancement MOSFET transistor on which the reference voltage, which is a sum of the PTAT voltage drop on the source resistor and the gate source voltage of the first enhancement MOSFET transistor, is formed.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 2, the prior art does not disclose or suggest, in combination with the limitations of the base claim and any intervening claims, primarily, a source of the first enhancement MOSFET transistor being coupled to the ground through a source resistor, wherein the MOSFET transistor of the output stage is coupled to a gate of the first depletion MOSFET transistor, and the negative feedback loop includes a coupling of the divider output node to the gate of the first enhancement MOSFET transistor.
The aforementioned limitations in combination with all remaining limitations of the respective claims are believed to render the aforementioned indicated claim and any dependent claims thereof patentable over the art of record.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Yamamoto (US 2010/0127689) discloses voltage reference circuits. Ogura (US 2023/0015014) discloses a voltage regulator.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HARRY RAYMOND BEHM whose telephone number is (571)272-8929. The examiner can normally be reached M-F: 8-5 EST.
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/HARRY R BEHM/Primary Examiner, Art Unit 2838