DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to communication from applicant received on January 20, 2026.
Response to Amendment
Applicant's submission filed on January 20, 2026 has been entered. Claims 1-20 are pending in the current application. Claims 1-20 are rejected herein.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Independent claims 1, 11 and 20 recite “wherein the maximum data retention parameter corresponds to a time between an erase operation performed on the second memory block and a current time”. Such limitation is considered new matter by examiner, as the specification does not explicitly disclose the “maximum data retention parameter” to correspond “to a time between an erase operation performed on the second memory block and a current time”, nor does the specification disclose a time between an erase operation performed on the second memory block and a current time to correspond to a maximum data retention parameter and for that specific teaching of the maximum data retention parameter to be used in conjunction with the rest of the limitations of the independent claims. The term/phrase “maximum data retention parameter” is disclosed in paragraphs [0049]-[0050], [0074], [0098], [0100], [0103], [0125], [0138], and [0152]. However, none of the aforementioned paragraphs disclose that the maximum data retention parameter corresponds to a time between an erase operation performed on the second memory block and a current time. Furthermore, paragraph [0077] recites “Here, the retention duration during which the first memory blocks are at least partly in the erased state may be understood as a time difference between the initial powering-up of the memory block having no data written therein or the moment of completing the erase operation on the memory block for the erase operation and the moment of receiving the write command.” Paragraph [0114] recites “the acquiring a retention duration during which the first memory blocks are at least partly in the erased state comprises: based on a time difference recorded by a timer of the memory system, determining a time difference for the first memory blocks between the initial powering-up of a memory block having no data written therein or a moment of completing the erase operation on the memory block for the erase operation and a moment of receiving the write command; and using the determined time difference as the retention duration.” Paragraphs [0077] and [0114] teach determining the retention duration, and indicate that the moment of receiving a write command is used in determining the retention duration. If such teaching is what applicant intends to refer to as support for the rejected limitation regarding the “current time”, such paragraphs do not explicitly disclose that the “current time” can correspond to “moment of receiving the write command”. Therefore, the teachings in the specification regarding determining the retention duration do not explicitly support a “current time” as being used as a parameter when determining a “maximum data retention parameter”.
All dependent claims are rejected for having the same deficiency as the claim(s) that they depend on.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 10, 11-13 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kanno et al. (Hereinafter Kanno, U.S. Publication No. 2019/0138226) in view of Punzo et al. (Hereinafter Punzo, U.S. Publication No. 2024/0103737).
Regarding claim 1, Kanno teaches:
A memory system, comprising:
a memory device including memory blocks (See Figure 1, NAND flash memory 5. The NAND flash memory includes memory blocks B0, B1, B2, etc.); and
a memory controller coupled with the memory device (See Figure 1, Controller 4.) and configured to:
in response to a write command, based on a data retention parameter of each of the memory blocks, determine a second memory block from first memory blocks being at least partly in an erased state among the memory blocks (See Figure 6, Figure 8., Figure 9 and Figure 10. See [0047] “Blocks B0 to Bm−1 have the limited erase count. The erase count may be indicated by the number of program/erase cycles. One program/erase cycle for a certain block includes erase operation for causing all the memory cells of the block to be in an erased state and write operation (program operation) for writing data to each page of the block.” See [0094] “the controller 4 selects, from blocks of the free block pool 52, a block in which a data retention term estimated from wear of the block is longer than or equal to the data retention term specified by a write request (write command) as a write destination block of the data received from the host 2. In this case, the controller 4 performs erase operation for the selected block to cause the selected block to be in a writable erased state.”), wherein the second memory block is a first memory block of the first memory blocks with a maximum data retention parameter among the first memory blocks…; and
write to-be-written data to the second memory block (See Figure 6, in which a level 1 block (i.e. block #10, #11, #23, #30) having a maximum data retention of 10 years corresponding to zero-500 erase counts may be selected for storing data based on wear and data retention requirements. See Figure 8 and Figure 9, which teach selecting a memory block based on data retention requirements. See [0105] “In the example of FIG. 6, the estimated data retention term of the blocks of level 1 (in which the erase count is 0 to 500) is ten years.” See [0127] “In FIG. 10 to FIG. 12, it is assumed that the wears of blocks 301 to 335 are managed by classifying it into 10 stages from level 1 to level 10…The wear of blocks 301 to 303 is equivalent to level 1 (the data retention term is ten years).” See [0163] “when a wear corresponding to a data retention term which is equal to the data retention term specified by the write command is level 3, and further when neither a block having a wear of level 3 nor a block having a wear of level 2 is present, the controller 4 selects, as a write destination block, a block having a wear corresponding to the longest data retention term among the blocks having a wear corresponding to a data retention term longer than or equal to the data retention term specified by the write command, in other words, a block having a wear of level 1.”).
Kanno does not explicitly disclose what Punzo teaches:
wherein the maximum data retention parameter corresponds to a time between an erase operation performed on the second memory block and a current time (See Abstract “The memory device may determine whether a block, of the plurality of blocks, satisfies at least one of an age condition that is based on a difference between a current time and an opening time associated with opening the block for programming, or a temperature condition that is based on a difference between a current temperature and an opening temperature associated with the block at the opening time.” See [0032] “a closed block 230 may transition to an open block 225 when the closed block 230 is erased by an erase operation.”)
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the data retention based writing method of Kanno with the memory block refresh method of Punzo to enable refreshing of memory blocks on power up based on an age and/or temperature condition, thus mitigating data retention degradation along a life span of the non-volatile memory devices, reducing refresh operation performed under unsafe conditions, and improving data integrity (See [0016]-[0017] of Punzo.).
Regarding claim 2, Kanno teaches:
The memory system of claim 1, wherein the first memory block includes at least one of the following:
a memory block having no data written therein (See [0082] “In a process for selecting a write destination block to which write data should be written, the write destination block may be selected from a group of free blocks which do not include valid data.” See [0098].).;
a memory block that had dummy data written therein and the dummy data has been erased; or
a memory block that had user data written therein, wherein at least part of the user data is invalid data and the invalid data has been erased (See [0098] “When the valid data in a certain block in the active block pool 51 is partially invalidated by data updating, etc., and the amount of invalid data is reduced to a value smaller than or equal to a predetermined value, the block is a target for garbage collection. All the valid data in the block are copied to another block (free block) by the garbage collection. When all the valid data in the block are copied to another block, the controller 4 moves this block to the free block pool 52.”).
Regarding claim 3, Kanno teaches:
The memory system of claim 2, wherein the memory controller is configured to,
upon determining that at least part of the user data written to the memory block that had the user data written therein is invalid data, perform the erase operation on the memory block having the user data written therein (See [0098] “When the valid data in a certain block in the active block pool 51 is partially invalidated by data updating, etc., and the amount of invalid data is reduced to a value smaller than or equal to a predetermined value, the block is a target for garbage collection. All the valid data in the block are copied to another block (free block) by the garbage collection. When all the valid data in the block are copied to another block, the controller 4 moves this block to the free block pool 52.”).
Regarding claim 10, Kanno teaches:
The memory system of claim 2, wherein the invalid data includes data indicated by a host system as to be erased, updated or rewritten (See [0098] “When the valid data in a certain block in the active block pool 51 is partially invalidated by data updating, etc., and the amount of invalid data is reduced to a value smaller than or equal to a predetermined value, the block is a target for garbage collection. All the valid data in the block are copied to another block (free block) by the garbage collection. When all the valid data in the block are copied to another block, the controller 4 moves this block to the free block pool 52.”).
Claim 11 and claim 20 are rejected for the same reasons as claim 1. Claim 12 is rejected for the same reasons as claim 2. Claim 13 is rejected for the same reasons as claim 3.
Claims 4 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Kanno in view of Punzo in view of Micheloni et al. (Hereinafter Micheloni, U.S. Publication No. 9,747,200.) in view of Kuo et al. (Hereinafter Kuo, U.S. Patent No. 10,403,379).
Regarding claim 4, Micheloni teaches:
The memory system of claim 2, wherein the memory controller is configured to,
if the memory blocks have the dummy data written therein when the memory system leaves a factory, perform the erase operation on the memory blocks at an initial power-on (See Figure 11. See Abstract “The non-volatile memory, such as flash memory, is pre-aged before first use in a host system. Pre-aging includes execution of a plurality of dummy program and erase cycles as part of the memory system or before assembly as part of the memory system. The memory system can include an NVDIMM having flash memory backup. The pre-aged flash memory programs a page of data in a shorter period of time relative to new flash memory. Fewer flash memory chips are needed in the memory system relative to memory systems using new flash memory chips, thereby reducing cost of the memory system.”. See Col. 10, lines 33-39 “At 304, the tester controls the NVDIMM to execute dummy program/erase cycles. For example, the NVDIMM can have special test modes accessible by the NVDIMM manufacturer through a special command issued to the flash controller. The flash controller then repeatedly programs dummy data to each page of each memory block of the flash devices, and then erases each memory block.” See Col. 6, lines 11-16 “In order to improve the programming speed of flash memory chips according to a present embodiment, the flash memory chips can be pre-aged before first use in a host system or the memory system it is a part of. First use can refer to the first time the flash memory chips are booted or powered up for operation in a host system.” See Figure 4. See Col. 11, lines 25-26 “Before, during or after 400, the operations of 402 and 404 are executed.”).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the data retention based writing method of Kanno and the memory block refresh method of Punzo with the flash memory pre-aging method of Micheloni to improve programming speed and reduce the amount of flash memory chips needed in a memory system, thereby reducing cost of the memory system (See Abstract and Col. 6, lines 11-63 of Micheloni).
Micheloni does not explicitly disclose what Kuo teaches:
after the memory system leaves the factory (See Col. 5, lines 37-39 “The erased block reverification method includes the following steps. Firstly, an erase command corresponding to a selected block is issued to the array control circuit.” See Col. 8, lines 47-54 “After the solid state storage device 10 leaves the factory, the solid state storage device 10 is used by the user. For enhancing the performance of the solid state storage device 10, the interface controller 101 performs the selected block reverification process on the inferior block according to the block erase time. That is, after the solid state storage device 10 leaves the factory, the interface controller 101 performs all steps of the flowchart as shown in FIG. 5.”)
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the data retention based writing method of Kanno and the memory block refresh method of Punzo and the flash memory pre-aging method of Micheloni with the erased block verification method of Kuo to reduce the amount of read failures, thus increasing data retrieval reliability (See Col. 7 line 65 - Col. 8 line 4 of Kuo. See Col. 9 lines 6-30 of Kuo).
Claim 14 is rejected for the same reasons as claim 4.
Claims 5-6 and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Kanno in view of Punzo in view of Lee et al. (Hereinafter Lee, U.S. Publication No. 2023/0030620).
Regarding claim 5, Lee teaches:
The memory system of claim 2, wherein the memory controller is configured to:
in response to an initial power-on of the memory block having no data written therein or a completion of the erase operation on the memory block having no data written, acquire a characteristic operating temperature of the memory system (See Figure 3, in which temperature readings can be obtained (Step 302) after an erase operation (Step 314). See [0041] “In step 314, a preventative operation is performed. If the block is storing data, then a garbage collection operation is performed to read the data from the block, and to write the data to a new (currently erased) block. If the block is an erased block, then a re-erase operation is performed on the block. The re-erase operation removes any accumulated charge in the block. Other preventative operations may be performed as an alternative to, or in addition to, the aforementioned preventative operations. Non-limiting examples of these preventative operations include, changing the read voltage(s) for a block, modifying the time when a partially-filed block should be closed.” See [0042] “In step 316, once the preventative operation is performed, the counter value for the block is reset to a value, which may be the default value or another value. Further, in the case where step 314 included a garbage collection operation, the counter value of the new block (i.e., the block to which data from the block was written) is also set to the default value.”);
acquire a retention duration during which the first memory blocks are at least partly in the erased state (See [0023] “the storage module controller (202) includes counters which track counter values associated with each block, sets of blocks or any combination thereof. The counter values correspond to temperature modified retention times or temperature modified erase bake times.” Also, see [0045]-[0050], which teach a default counter value (i.e. retention duration) based on a default temperature and/or a constant operating temperature. See Figure 3, which teaches acquiring and adjusting the counters (i.e. retention duration) for memory blocks. See Table 1 depicted in [0046].); and
based on the characteristic operating temperature of the memory system and the retention duration during which the first memory blocks are at least partly in the erased state, determine data retention parameters of the first memory blocks (See [0014] “One or more embodiments of the invention address this issue by monitoring the actual operating temperature of the SSM, and modifying the retention time in a manner that takes into account the actual operating temperature (referred to a temperature modified retention time). For example, if the actual temperature of the SSM is greater than the default temperature, the temperature modified retention time will indicate that the data has been stored longer at the location than it actually has.” See [0034] “In step 306, an unprocessed block is selected. A block is an unprocessed block when the counter value associated with the block has not been updated after the composite temperature has been obtained in step 302.” See [0035] “In step 308, the counter increment value for the block selected in step 306 is determined based on the composite temperature. More specifically, as discussed above, the counter value corresponds to either a temperature modified retention time (for blocks with data) or a temperature modified erase bake time (for erased blocks). If the composite temperature value equals the default temperature then the counter increment value is set as the default counter increment value (e.g., 1). If the composite temperature value is greater than the default temperature, the counter increment value is set to a value that is greater than the default counter increment value. The specific value of the counter increment value is determined as a function of the difference between the composite temperature value and the default temperature value. The function may be a linear function, the function may be a geometric function, or any other type of function.”. See Figure 3, which teaches determining the counter values (i.e. retention duration) for memory blocks based on temperature. See Table 1 depicted in [0046].).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the data retention based writing method of Kanno and the memory block refresh method of Punzo with the temperature-adjusted data retention tracking method of Lee to improve performance, which includes both throughput and latency, as well as endurance (i.e., the number of P/E cycles incurred), in scenarios in which the operating temperature of storage device differs from the default temperature (See [0013]-[0014] of Lee.).
Regarding claim 6, Lee teaches:
The memory system of claim 5, wherein when the first memory blocks are at least partly in the erased state, the characteristic operating temperature of the memory system experiences temperature intervals (See [0050] “The NAND flash operates at a constant temperature of 82° C. for five hours and then operates at a temperature of 72° C. thereafter.”), and
the memory controller is configured to:
acquire the characteristic operating temperature of the memory system in each temperature interval of the temperature intervals (See [0050] “The NAND flash operates at a constant temperature of 82° C. for five hours and then operates at a temperature of 72° C. thereafter.”);
acquire the retention duration corresponding to each of the temperature intervals;
sequentially determine a data retention sub-parameter corresponding to each temperature segment of the temperature intervals, wherein, for each temperature segment, the data retention sub-parameter corresponding to the temperature segment is determined based on the characteristic operating temperature of the memory system in the temperature interval and the retention duration corresponding to the temperature interval (See [0050] “The NAND flash operates at a constant temperature of 82° C. for five hours and then operates at a temperature of 72° C. thereafter. In this scenario, the default counter value is 1. Further, based on the above table, the counter increment value at each ten minute interval is 81 when the temperature is 82° C. and the counter increment value at each ten minute interval is 32 when the temperature is 72° C. Thus, the counter value for a block in the NAND flash operating under the aforementioned temperature conditions will reach 4320 in 14.8 hours (i.e., 5 + (4320-1-5*6*81)/(32*6)).”); and
calculate a sum of data retention sub-parameters corresponding to each temperature segment to obtain the data retention parameters of the first memory blocks (See [0031] “In step 302, one or more temperature readings are obtained from the internal temperature sensors and used to generate a composite temperature. In scenarios in which there is only one temperature sensor, a single temperature reading may be taken directly as the composite temperature, or multiple temperature readings may be taken over a period of time and then averaged to generate a composite temperature. In scenarios in which there are multiple temperature sensors, a single temperature reading may be taken from each sensor to determine a composite temperature, or multiple temperature readings may be continuously obtained from each of the sensors (e.g., every minute) and then an average of the most recent k temperature readings per temperature sensor is used to obtain a composite temperature periodically (e.g., every 10 minutes).”).
Claim 15 is rejected for the same reasons as claim 5. Claim 16 is rejected for the same reasons as claim 6.
Allowable Subject Matter
Claims 7-9 and 17-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record failed to teach the claimed limitations and the relational expression set forth in claim 7, nor would it have been obvious.
The prior art of record failed to explicitly teach “from initial power-on of the memory block having no data written therein or a moment of completing the erase operation on the memory block for the erase operation to a moment of receiving the write command”, as recited in claim 8, in combination with the rest of the limitations of claim 8, nor would it have been obvious. That is, although Figure 2 and [0031] of Lee (U.S. Publication No. 2023/0030620) teach all other limitations of claim 8, such teachings are silent in regards to “from initial power-on of the memory block having no data written therein or a moment of completing the erase operation on the memory block for the erase operation to a moment of receiving the write command”, nor would it have been obvious over the cited art of record.
The prior art of record failed to teach the totality of the claimed limitations set forth in claim 9, nor would it have been obvious. That is, the prior art of record failed to teach “record a time difference, wherein the memory controller is configured to: based on the time difference recorded by the timer, determine a time difference for the first memory blocks between initial power-on of the memory block having no data written therein or a moment of completing the erase operation on the memory block for the erase operation and a moment of receiving the write command; and use the determined time difference as the retention duration.”, as recited in claim 9, nor would it have been obvious.
Claim 17 is deemed allowable subject matter for the same reasons as claim 7. Claim 18 is deemed allowable subject matter for the same reasons as claim 8. Claim 19 is deemed allowable subject matter for the same reasons as claim 9.
Response to Arguments
Applicant’s arguments, filed January 20, 2026, with respect to the current amendments filed on January 20, 2026 have been fully considered and are persuasive. However, upon further consideration, a new ground(s) of rejection is made in view of newly found prior art Punzo. All pending claims in the instant application are rejected herein.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL L WESTBROOK whose telephone number is (571)270-5028. The examiner can normally be reached Mon-Fri 9am-5pm.
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/MICHAEL L WESTBROOK/Examiner, Art Unit 2139
/REGINALD G BRAGDON/Supervisory Patent Examiner, Art Unit 2139