DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The prior art documents submitted by applicant in the Information Disclosure Statements filed on April 20, 2024 have all been considered and made of record (note the attached copies of form PTO-1449).
Drawings
Nine (9) sheets of drawings were filed on March 20, 2024.
Specification
Applicant’s cooperation is requested in correcting any errors of which applicant may become
aware in the specification.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 10-11, 13-14, and 18 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Amano et al. (US20210104637A1), hereafter Amano.
Regarding claim 1, Amano discloses a semiconductor package (FIG.1. Opto-electronic integrated circuit) comprising: a printed circuit board (Circuit board 100. Par. [0080]) defining a cavity extending inward from an upper surface thereof (FIG.15); an optical waveguide extending above the cavity from the upper surface of the printed circuit board (FIG. 2. Waveguide 320); a first semiconductor chip (Semiconductor chip 200) positioned inside the cavity (FIG.2. Par.[0081] 200 embedded in 100) and comprising a photonic integrated circuit (Par. [0081]: 200 is a PIC) overlapping a portion of the optical waveguide (Waveguide 320) in a vertical direction(FIG.2); an interposer (Insulating layer 300. Par. [0040] of the present application describes the interposer as a passive intermediate substrate that routes electrical signals, which aligns with the definition of the insulation layer of Amano as described in Par. [0082]) on the first semiconductor chip (FIG.2 ); and a second semiconductor chip on the interposer (FIG.2. Semiconductor Chip 400).
Regarding claim 2, Amano discloses the device of claim 1. Amano further discloses a lower surface of the optical waveguide is divided into a first area and a second area (See annotated FIG. 2), the first area contacts the printed circuit board (Circuit board 100), and the second area is above the cavity and faces a light-receiving section of the photonic integrated circuit (See annotated FIG.2. Par. [0081]: 200 is a PIC). Amano teaches a structure that is substantially identical to that of the claimed invention, therefore the claimed properties and functions are presumed to be necessarily present. The burden is on the applicant to show that the device of Amano does not possess and is not capable of these functional characteristics or properties. See MPEP 2112.01.
PNG
media_image1.png
842
1310
media_image1.png
Greyscale
Regarding claim 3, Amano discloses the device of claim 1. Amano further discloses the photonic integrated circuit (Par. [0081]: 200 is a PIC ) is separated from the second area of the optical waveguide in the vertical direction(FIG. 5 illustrates a second waveguide 210 separating the second area of the optical waveguide 320 from Semiconductor/PIC 200).
Regarding claim 4, Amano discloses the device of claim 1. Amano further discloses a portion of the optical waveguide is under the interposer (layer 300b) in the vertical direction (FIG.2).
Regarding claim 10, Amano discloses the device of claim 1. Amano further discloses the cavity is separated from a side surface (FIG. 15) of the printed circuit board (FIG.1 ).
Regarding claim 11, Amano discloses the device of claim 1. Amano further discloses first semiconductor chip (Semiconductor chip 200) is configured to convert an optical signal from the optical waveguide (Par.[0069]) into an electrical signal and transfer the electrical signal to the second semiconductor chip (Semiconductor chip 400) through the interposer (insulating layer 300)(Par.[0069] and [0087]) . Amano teaches a structure that is substantially identical to that of the claimed invention, therefore the claimed properties and functions are presumed to be necessarily present. The burden is on the applicant to show that the device of Amano does not possess and is not capable of these functional characteristics or properties. See MPEP 2112.01.
Regarding claim 13, Amano discloses the device of claim 1. Amano further discloses a redistribution structure on at least one of an upper surface of the interposer or a lower surface of the interposer (Par. [0082] and [0083]).
Regarding claim 14, Amano discloses a semiconductor package (FIG.1. Opto-electronic integrated circuit) comprising: a main printed circuit board (Circuit board 100. Par. [0080]) defining at least one cavity extending inward from an upper surface thereof (FIG.15); a plurality of main optical waveguides (Par. [0072]:Two waveguides 320) extending above the at least one cavity from the upper surface of the printed circuit board (FIG. 1 and 2. Par.[0072]); a plurality of first semiconductor chips (Par. [0072]:Semi-conductor chip 200) positioned inside the at least one cavity (FIG.2) to each overlap a portion of one of the plurality of main optical waveguides (waveguide 320) in a vertical direction (FIG. 2) and comprising an active surface (First surface 202. Par. [0081]) and an inactive surface (Second surface 204); an interposer (Insulating layer 300. Par. [0040] of the present application describes the interposer as a passive intermediate substrate that routes electrical signals, which aligns with the definition of the insulation layer of Amano as described in Par. [0082]) on the plurality of first semiconductor chips (FIG.1); and a second semiconductor chip on the interposer (FIG.2. Semiconductor Chip 400), wherein the interposer overlaps at least a portion of each of the plurality of first semiconductor chips in the vertical direction (FIG.1.Par.[0074]), and the plurality of first semiconductor chips are mounted inside the at least one cavity such that the active surface faces the interposer (FIG. 2).
Regarding claim 18, Amano discloses the device of claim 14. Amano further discloses at least two first semiconductor chips are inside a cavity of the main printed circuit board (Par. [0072]; FIG.1 and 2).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7-9, 15-17, and 19 rejected under 35 U.S.C. 103 as being unpatentable over Amano et al. (US20210104637A1), hereafter Amano.
Regarding claim 7, Amano discloses the device of claim 1. Amano further discloses the first semiconductor chip comprises an active surface (First surface 202. Par. [0081]) and an inactive surface (Second surface 204), wherein the first semiconductor chip (Semi-conductor chip 200) is inside the cavity such that the active surface faces the interposer (FIG. 2. insulating layer 300). Amano fails to disclose the photonic circuit is on the active surface.
Before the effective filing date of the present invention, it would have been obvious to a person of ordinary skill in the art to place a photonic integrated circuit (PIC) on the active surface of the semiconductor chip (200) in Amano. Placing the photonic circuit on the active surface provides direct, efficient light coupling to waveguides as illustrated in FIG.5
Regarding claim 8, Amano discloses the device of claim7. Amano further discloses the first semiconductor chip (Semiconductor chip 200) further comprises a plurality of connection pads (Electrodes 206) electrically connecting the first semiconductor chip to the interposer (FIG. 2), and wherein the plurality of connection pads are on the active surface (Par. [0081]:Plurality of electrodes 206 at a first surface 202).
Regarding claim 9, Amano discloses the device of claim 1. Amano further discloses plurality of connection pads (electrodes 206) overlap the second semiconductor chip (Semiconductor chip 400) in the vertical direction (FIG. 2). Amano fails to disclose some of the plurality of connection pads do not overlap the second semiconductor chip in the vertical direction.
Before the effective filing date of the present invention, it would have been obvious to a person of ordinary skill in the art to place some connection pads in position that does not overlap the second semiconductor chip in the vertical direction since it has been held that rearranging parts of an invention involves only routine skill in the art (In re Japikse, 86 USPQ 70).
Regarding claims 15 and 16, Amano discloses the device of claim 14. Amano fails to disclose, a sub-printed circuit board on the upper surface of the main printed circuit board; a sub-optical waveguide on an upper surface of the sub-printed circuit board; and a third semiconductor chip on the sub-printed circuit board and the sub-optical waveguide and electrically connected to the sub-printed circuit board, wherein the third semiconductor chip is configured to convert an optical signal received from the sub-optical waveguide into an electrical signal and transfer the electrical signal to the second semiconductor chip through the sub-printed circuit board, the main printed circuit board, and the interposer. wherein the sub-optical waveguide is between the sub-printed circuit board and the third semiconductor chip in the vertical direction, and wherein the main printed circuit board and the plurality of first semiconductor chips are under the plurality of main optical waveguides in the vertical direction.
Before the effective filing date of the present invention, it would have been obvious to a person of ordinary skill in the art to duplicate the essential working parts of Amano’s device since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art (St Regis Paper Co. v. Bemis Co., 193 USPQ 8.).
Regarding claim 17, Amano discloses the device of claim 14. Amano further discloses a first cavity and a second cavity in the main printed circuit board (FIG.1 shows Semiconductors 200 are with a cavity of circuit board 100). Amano fails to disclose the first cavity and the second cavity are arranged in a zigzag manner along one edge of the main printed circuit board.
Before the effective filing date of the present invention, it would have been obvious to a person of ordinary skill in the art to rearrange the first and second cavities of the main printed circuit board of Amano to be in a zigzag manner along one edge of the main printed circuit board since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Regarding claim 19, Amano discloses a semiconductor package (FIG.1. Opto-electronic integrated circuit) comprising: a printed circuit board (Circuit board 100. Par. [0080]) with a cavity extending inward from an upper surface thereof (FIG. 15); an optical waveguide extending above the cavity from the upper surface of the printed circuit board(FIG. 2. Waveguide 320); a first semiconductor chip (Semiconductor chip 200) positioned inside the cavity (FIG.2) and comprising a photonic integrated circuit (Par. [0081]: 200 is a PIC) overlapping a portion of the optical waveguide(Waveguide 320) above the cavity in a vertical direction (FIG.2); an interposer (Insulating layer 300. Par. [0040] of the present application describes the interposer as a passive intermediate substrate that routes electrical signals, which aligns with the definition of the insulation layer of Amano as described in Par. [0082]) on the first semiconductor chip (FIG.2); and a second semiconductor chip on the interposer(FIG.2. Semiconductor Chip 400)., wherein the photonic integrated circuit comprises a light-receiving section(See annotated FIG.2. Par. [0081]: 200 is a PIC) configured to receive an optical signal discharged from the optical waveguide(Abstract: Waveguide 320 is optically coupled to semiconductor chip 200) and is configured to convert the optical signal into an electrical signal(Par.[0087] 200 in electrically connected to 400) , the first semiconductor chip (Semiconductor 200) is inside the cavity(FIG.2) ,and at least a portion of the optical waveguide (waveguide 321) is between the interposer(layer 300b) and the first semiconductor chip(FIG.2). Amano fails to disclose the photonic circuit is separated from the bottom surface of the cavity.
Before the effective filing date of the present invention, it would have been obvious to a person of ordinary skill in the art to place a photonic integrated circuit (PIC) on the active surface of the semiconductor chip (200) in Amano, separating it from the bottom surface of the cavity. Placing the photonic circuit on the active surface provides direct, efficient light coupling to waveguides as illustrated in FIG.5
Claims 5-6 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Amano et al. (US20210104637A1), hereafter Amano, in view of Lu et al. (US 11257763 B2), hereafter Lu.
Regarding claim 5 and 6 , Amano discloses the device of claim 1. Amano further discloses a first semiconductor chip (Semiconductor chip 200), an interposer (Insulating layer 300. Par. [0040] of the present application describes the interposer as a passive intermediate substrate that routes electrical signals, which aligns with the definition of the insulation layer of Amano as described in Par. [0082]), and an optical waveguide (waveguide 320). Amano fails to disclose a transparent encapsulation material between the first semiconductor chip and the interposer and between the optical waveguide and the interposer.
Lu teaches a transparent encapsulation material (Encapsulant 40. Column 4 lines 20-23: epoxy resin and silicon oxide fillers) between the first semiconductor chip (semiconductor die 30) and the interposer (RDL 50) and between the optical waveguide (Waveguide 32) and the interposer (RDL 50: Par. [0040] of the present application describes the interposer as a passive intermediate substrate that routes electrical signals, which aligns with the definition of the redistribution layer (RDL) of Lu as described in Column 4 lines 50-62).
Before the effective filing date of the present invention, it would have been obvious to a person of ordinary skill in the art to modify the device of Amano with a transparent encapsulant in order to improve the reliability of the optical coupling between the semiconductor chip and the optical waveguide and provide protection against moisture or contamination.
Regarding claim 12, Amano discloses the device of claim 1. Amano further discloses a through via (Conductive path 310) penetrating into the interposer (Insulating layer 300. Par. [0040] of the present application describes the interposer as a passive intermediate substrate that routes electrical signals, which aligns with the definition of the insulation layer of Amano as described in Par. [0082]). Amano fails to disclose the interposer comprises glass.
Lu teaches the interposer(RDL 50: Par. [0040] of the present application describes the interposer as a passive intermediate substrate that routes electrical signals, which aligns with the definition of the redistribution layer (RDL) of Lu as described in Column 4 lines 50-62) comprises glass (Colum 4 lines 60-66: silicon oxide).
Before the effective filing date of the present invention, it would have been obvious to a person of ordinary skill in the art to modify the interposer of Amano to comprise glass since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. Glass is a well-known, high-quality, insulating material often used in semiconductor manufacturing for its dielectric properties and stability
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s
disclosure:
➢ Joerg et al. (EP-4307023-A1 )see the entire disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAJANAE N GREEN whose telephone number is (571)272-2188. The examiner can normally be reached Tues-Fri. 5:30a-3:30p.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Uyen-Chau Le can be reached at (571) 272-2397. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TAJANAE NICOLE GREEN/Examiner, Art Unit 2874
/UYEN CHAU N LE/Supervisory Patent Examiner, Art Unit 2874
Prosecution Insights