DETAILED ACTION
This action is responsive to the following communications: the Application filed March 20, 2024.
Claims 1-20 are pending. Claims 1, 13 and 20 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 6, 8-9, 13-14, 17 and 19-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Thorp et al. (US 2008/0184057).
Regarding independent claim 1, Thorp et al. disclose a device comprising: an integrated circuit (figure 1) comprising a voting circuit (130, figure 1) that is configured to: receive a plurality of redundant copies (106, 108 and 110, figure 1) of a signal input (In operation, once identical configuration is programmed into each of the configuration arrays 106, 108, 110, a control signal may be used to initiate a read of the configuration information) ; and remedy faults (see para.[0029] below discloses: The majority voting logic 130 is adapted to select the most likely correct value of the configuration information based on the most)in a transmission pathway (The selected value is passed to the support logic 116 of the data array 104 and is used to configure the memory array 114 of the data array 104)
of the signal input by producing a signal output that reflects a majority (The majority voting logic 130 is adapted to select the most likely correct value of the configuration information based on the most frequently occurring value from among the plurality of configuration arrays 106, 108, 110).among received versions of the plurality of redundant copies of the signal input (see para.[0029] and para.[0028] below).
[0029] In operation, once identical configuration is programmed into each of the configuration arrays 106, 108, 110, a control signal may be used to initiate a read of the configuration information. For example, scan chains in the support logic 124, 126, 128 of the configuration arrays may be used to program the configuration information into the configuration arrays 106, 108, 110. The configuration information from the same memory locations in each of the different configuration arrays 106, 108, 110 is transferred to the majority voting logic 130 to be compared. The majority voting logic 130 is adapted to select the most likely correct value of the configuration information based on the most frequently occurring value from among the plurality of configuration arrays 106, 108, 110. The selected value is passed to the support logic 116 of the data array 104 and is used to configure the memory array 114 of the data array 104.
[0028] In some embodiments, the configuration arrays 106, 108, 110 may be disposed on different substrates to further electrically and physically isolate the configuration arrays 106, 108, 110 from each other. In other words, if a physical impact or short occurs in one configuration array, the system 100 may be made more fault tolerant by locating the remaining configuration arrays on a different chip. In other embodiments, the configuration arrays 106, 108, 110 may be disposed upon the same substrate but distributed at different locations on the substrate. The locations of the configuration arrays 106, 108, 110 may be selected based upon a number of different considerations. For example, the configuration arrays 106, 108, 110 may be located to avoid physical or electrical stress points on the substrate 102 (e.g., corners of the substrate 102), and/or located to physically separate the configuration arrays 106, 108, 110 by a maximized possible distance, and/or located to comply with signal timing requirements between the system components, and/or located to improve reliability, and/or located to improve yield, and/or located based on any practicable combination of the above considerations.
Regarding claim 2, Thorp et al. disclose the limitation of claim 1.
Thorp et al. further disclose wherein the integrated circuit comprises a three- dimensional integrated circuit ([0022] The data array 104 and the configuration arrays 106, 108, 110 may each include any type of memory arrays including arrays comprising two-terminal memory cells, three dimensional (3D) memory (e.g., any memory that includes two or more active memory elements vertically arranged).
Regarding claim 6, Thorp et al. disclose the limitation of claim 1.
Thorp et al. further disclose wherein the plurality of redundant copies comprises three redundant copies of the signal input (see rejection of claim 1).
Regarding claim 8, Thorp et al. disclose the limitation of claim 1.
Thorp et al. further disclose wherein the signal input (para.[0029]) is transmitted before the integrated circuit loads fuse data ([0022] The data array 104 and the configuration arrays 106, 108, 110 may each include any type of memory arrays including arrays comprising two-terminal memory cells, three dimensional (3D) memory (e.g., any memory that includes two or more active memory elements vertically arranged), antifuse based memory cells, fuse based memory cells). Noted: the signal input must be transmitted before the integrated circuit loads fuse data.
Regarding claim 9, Thorp et al. disclose the limitation of claim 1.
Thorp et al. further disclose wherein the integrated circuit requires the signal input to be correct (see para.[0028] para.[0029]) at power-on (Noted: power must be on during the integrated circuit operates).
Regarding independent claim 13, Thorp et al. disclose system comprising: an integrated circuit comprising a voting circuit that is configured to: receive a plurality of redundant copies of a signal input; and remedy faults in a transmission pathway of the signal input by producing a signal output that reflects a majority among received versions of the plurality of redundant copies of the signal input (see rejection of claim 1); and a physical memory that stores an output (104, figures 1 and 2) of the integrated circuit (figure 1).
0028] In some embodiments, the configuration arrays 106, 108, 110 may be disposed on different substrates to further electrically and physically isolate the configuration arrays 106, 108, 110 from each other. In other words, if a physical impact or short occurs in one configuration array, the system 100 may be made more fault tolerant by locating the remaining configuration arrays on a different chip. In other embodiments, the configuration arrays 106, 108, 110 may be disposed upon the same substrate but distributed at different locations on the substrate. The locations of the configuration arrays 106, 108, 110 may be selected based upon a number of different considerations. For example, the configuration arrays 106, 108, 110 may be located to avoid physical or electrical stress points on the substrate 102 (e.g., corners of the substrate 102), and/or located to physically separate the configuration arrays 106, 108, 110 by a maximized possible distance, and/or located to comply with signal timing requirements between the system components, and/or located to improve reliability, and/or located to improve yield, and/or located based on any practicable combination of the above considerations.
14. The system of claim 13, wherein the integrated circuit comprises a three- dimensional integrated circuit (see rejection of claim 2).
17. The system of claim 13, wherein the plurality of redundant copies comprises three redundant copies of the signal input (see rejection of claim 1).
Regarding claim 19, Thorp et al. disclose the limitation of claim 13.
Thorp et al. further disclose wherein the signal input is transmitted (see figure 1 and para.[0029]) before the integrated circuit loads fuse data (see para.[0022] discloses: [0022] The data array 104 and the configuration arrays 106, 108, 110 may each include any type of memory arrays including arrays comprising two-terminal memory cells, three dimensional (3D) memory (e.g., any memory that includes two or more active memory elements vertically arranged), antifuse based memory cells, fuse based memory cells)
Regarding independent claim 20, Thorp et al. disclose method comprising: transmitting, from a source logic unit (MAJARITY VOTING LOGIC, figure 1, also see figure 2), a plurality of redundant copies of a signal input to a voting circuit that is configured to: receive the plurality of redundant copies of the signal input; and remedy electrical faults in a transmission pathway of the signal input by producing a signal output that reflects a majority among received versions of the plurality of redundant copies of the signal input (see rejection of claim 1); and receiving , at a destination logic unit (figure 1, also see ABTRACT, the last three lines), the signal output from the voting circuit (output signal figure 1 below).
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 3, 11, 12 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Thorp et al. (US 2008/0184057) in view of Ryu et al. (US 2017/0110206).
Regarding claim 3, Thorp et al. disclose the limitation of claim 2.
However, Thorp et al. are silent with respect to wherein the voting circuit is positioned adjacent to a through-silicon via (TSV) and remedies faults in the TSV.
Rye et al. disclose wherein the voting circuit is positioned adjacent to a through-silicon via (TSV) and remedies faults in the TSV (see figure 24, paragraphs [0117] and [0210] and para.[0248]).
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Since Thorp et al. and Ryu et al. are both from the same field of endeavor, the purpose disclosed by Ryu et al. would have been recognized in the pertinent art of Thorp et al.
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teaching of Thorp et al. to teaching of Ryu et al. for purpose of using TSV to transmit and receive signals therebetween through TSV and circuit layer.
15. The system of claim 14, wherein the voting circuit is positioned adjacent to a through-silicon via (TSV) and remedies faults in the TSV (see rejection of claim 3).
Regarding claim 11, Thorp et al. disclose the limitation of claim 1.
However, Thorp et al. are silent with respect to wherein the voting circuit repairs an open circuit fault in the transmission pathway of the signal input.
Ryu et al. disclose wherein the voting circuit repairs an open circuit fault in the transmission pathway of the signal input (see para. [0210] below).
[0210] The encoded fail addresses CTI1˜CTI3 redundantly stored in the second region RG12 are provided to a majority voting circuit 680. The majority voting circuit 680 performs a majority voting on the encoded fail addresses CTI1˜CTI3, selects one of the encoded fail addresses CTI1˜CTI3, which indicates majority (that is, which receives a majority vote), and provides the encoded fail address which is selected to the error correction circuit 610. The error correction circuit 610 decodes the encoded fail address and provides the decoded fail address to the test/repair manage circuit 650. The test/repair manage circuit 650 provides the fail address FL_ADDR to the anti-fuse box 670 and the anti-fuse box 670 programs the fail address FL_ADDR in the anti-fuse array 671.
Since Thorp et al. and Ryu et al. are both from the same field of endeavor, the purpose disclosed by Ryu et al. would have been recognized in the pertinent art of Thorp et al.
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teaching of Thorp et al. to teaching of Ryu et al. for purpose of using the voting circuit to repair the fuse.
Regarding claim 12, Thorp et al. disclose the limitation of claim 1.
However, Thorp et al. are silent with respect to wherein the voting circuit repairs a short-circuit fault in the transmission pathway of the signal input
Ryu et al. disclose wherein the voting circuit repairs a short-circuit fault in the transmission pathway of the signal input (see para.[0210] below).
[0210] The encoded fail addresses CTI1˜CTI3 redundantly stored in the second region RG12 are provided to a majority voting circuit 680. The majority voting circuit 680 performs a majority voting on the encoded fail addresses CTI1˜CTI3, selects one of the encoded fail addresses CTI1˜CTI3, which indicates majority (that is, which receives a majority vote), and provides the encoded fail address which is selected to the error correction circuit 610. The error correction circuit 610 decodes the encoded fail address and provides the decoded fail address to the test/repair manage circuit 650. The test/repair manage circuit 650 provides the fail address FL_ADDR to the anti-fuse box 670 and the anti-fuse box 670 programs the fail address FL_ADDR in the anti-fuse array 671.
Since Thorp et al. and Ryu et al. are both from the same field of endeavor, the purpose disclosed by Ryu et al. would have been recognized in the pertinent art of Thorp et al.
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teaching of Thorp et al. to teaching of Ryu et al. for purpose of using the voting circuit to repair the fuse.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Thorp et al. (US 2008/0184057) in view of Colombo et al. (US 2022/0308892).
Regarding claim 10, Thorp et al. disclose the limitation of claim 8.
However, Thorp et al. are silent with respect to wherein the signal input comprises at least one of: a system reset signal; a power-on/reset signal; or a JTAG signal.
Colombo et al. disclose wherein the signal input comprises at least one of: a system reset signal; a power-on/reset signal; or a JTAG signal (see para.[0283] discloses: Generally, even in a software implementation a dedicated voting circuit 1052 may be used because the signal LCFA_REQ′ may be used to signal the reset request to the reset module 116 (i.e., the reset circuit 116 may be configured to start the functional reset in response to the signal LCFA_REQ′ (rather than the signal LCFA_REQ)).
Since Thorp et al. and Colombo et al. are both from the same field of endeavor, the purpose disclosed by Colombo et al. would have been recognized in the pertinent art of Thorp et al.
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teaching of Thorp et al. to teaching of Colombo et al. for purpose of using signal the reset request to the reset module.
Allowable Subject Matter
Claims 4, 5,7 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 4, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach the claimed limitation of the three-dimensional integrated circuit comprises a first substrate and a second substrate, the second substrate being disposed atop the first substrate; the second substrate comprises a plurality of through-silicon vias (TSVs) that are configured to transmit signals through the second substrate; the three-dimensional integrated circuit further comprises a first logic processor disposed on the first substrate, and a second logic processor disposed on the second substrate, the first logic processor being configured to transmit signals to the voting circuit by the plurality of TSVs; and the voting circuit is disposed on the second substrate and is configured to: receive signals from the first logic processor by the plurality of TSVs; and transmit the signal output to the second logic processor in combination with the other limitations thereof as is recited in the claim.
Regarding claim 5, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach the claimed limitation of wherein the voting circuit is positioned adjacent to a cross- layer connection between adjacent layers of the three-dimensional integrated circuit and remedies faults in the cross-layer connection in combination with the other limitations thereof as is recited in the claim. Claim 7 depend on claim 5.
Regarding claim 18, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach the claimed limitation of wherein the voting circuit comprises: a first layer comprising three NAND gates that receive sub-combinations of the three redundant copies of the signal input as inputs according to an AB, BC, AC scheme; a second layer comprising one NAND gate that receives the outputs of the first layer as an input; and an output that outputs a result of the voting circuit in combination with the other limitations thereof as is recite in the claim.
Conclusion
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/MINH D DINH/Examiner, Art Unit 2827 /AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827