CTNF 18/611,657 CTNF 81182 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15-aia AIA Claim(s) 1, 3-5, 9-13 and 15-16 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Cui et al. (USPAPN 2022/0021363) . With respect to claim 1, Cui et al. discloses, in Figs. 2(a) and 2(b), a radio frequency (RF) variable gain amplifier (VGA) (one of Fig. 2(a) and Fig. 2(b)) comprising: a first transistor (left side M2) comprising a first gate (gate of left side M2), a first source (source of left side M2), and a first drain (drain of left side M2), wherein the first gate is coupled to a control input (common gate bias voltage, note M2 is a common gate transistor and must have a bias voltage common to its gate, see para 0053), and wherein the first drain is coupled to a first terminal of an output (output at drain); a second transistor (right side M2) comprising a second gate (gate of right side M2), a second source (source of right side M2), and a second drain (drain of right side M2), wherein the second gate is coupled to the control input (common gate bias voltage of the common gate transistor of the right side M2), and wherein the second drain is coupled to a second terminal of the output (output at drain); a third transistor (left side M3 of Fig. 2(a); left side M1 of Fig. 2(b)) comprising a third gate (gate of left side M3 of Fig. 2(a); gate of left side M1 of Fig. 2(b)), a third source (source of left side M3 of Fig. 2(a); source of left side M3 of Fig. 2(b)), and a third drain (drain of left side M3 of Fig. 2(a); drain of left side M1 of Fig. 2(b)), wherein the third drain is coupled to the first source (respective drain and source are connected as claimed), and wherein the third gate is coupled to a first terminal of an input (Vin+); and a fourth transistor (right side M3 of Fig. 2(a); right side M1 of Fig. 2(b)) comprising a fourth gate (gate of right side M3 of Fig. 2(a); gate of right side M1 of Fig. 2(b)), a fourth source (source of right side M3 of Fig. 2(a); source of right side M1 of Fig. 2(b)), and a fourth drain (drain of right side M3 of Fig. 2(a); drain of right side M1 of Fig. 2(b)), wherein the fourth drain is coupled to the second source (respective drain and source are connected as claimed), and wherein the fourth gate is coupled to a second terminal of the input (Vin-); wherein the first source is not connected to the second drain via one or more transistors (the first and second sources are not connected), and wherein the second source is not connected to the second drain via one or more transistors (the second source is not connected to the second drain via one or more transistors. It is understood/interpreted that “one or more transistors” is in addition to the second transistor). With respect to claim 3, the RFVGA of claim 1, further comprising a transformer (transformer connected to Vout and each left side and right side M2) comprising a first input (at the drain of the left side M2), a second input (at the drain of the right side M2), a first output (one of the output terminals of the Vout side of the transformer) and a second output (other one of the output terminals of the Vout side of the transformer), wherein the first input is coupled to the first terminal of the output, wherein the second input is coupled to the second terminal of the output (the transformer and output terminals are connected as claimed). With respect to claim 4, the RFVGA of claim 1, wherein the third source and the fourth source are coupled to a reference voltage node (ground). With respect to claim 5, the RFVGA of claim 1, further comprising: a fifth transistor (left side M1 of Fig. 2(a)) comprising a fifth source (source of left side M1 of Fig. 2(a)), a fifth drain (drain of left side M1 of Fig. 2(a)), and a fifth gate (gate of left side M1 of Fig. 2(a)), wherein the fifth source is coupled to the first source (sources of left side M1 and M2 are connected), wherein the fifth gate is coupled to a second control input (control circuit signal that activates/deactivates M1, see paras 0053 063), and wherein the fifth drain is coupled to a voltage power node (voltage connected to drain of M1, e.g., upper rail voltage); and a sixth transistor (right side M1 of Fig. 2(a)) comprising a sixth source (source of right side M1 of Fig. 2(a)), a sixth drain (drain of right side M1 of Fig. 2(a)), and a sixth gate (gate of right side M1 of Fig. 2(a)), wherein the sixth source is coupled to the second source (sources of right side M1 and M2 are connected), wherein the sixth gate is coupled to the second control input (control signal for turning on and off M1 see paras 0053 and 0063), and wherein the sixth drain is coupled to the voltage power node (power supply at drain, e.g., upper rail voltage). With respect to claim 9, the RFVGA of claim 1, wherein the first terminal of the input is coupled to a first bias node via a first resistive element (Vbias of Fig. 2(b) to the AC component of Vin+ via the resistor and capacitor connected to Vin+), and wherein the second terminal of the input is coupled to a second bias node via a second resistive element (Vbias of Fig. 2(b) to the AC component of Vin- via the resistor and capacitor connected to Vin-),. With respect to claim 10, the RFVGA of claim 1, wherein the RFVGA is configured in a first path of a split transmission path of a phased array transmission system (Figs. 2(a) and 2(b) comprise a VGA of one of the transmission paths of split between the multiple transmit channels of a phased array antenna, see paragraphs 0002, 0004 and 0058). With respect to claim 11, the RFVGA of claim 1, wherein the first transistor and the second transistor are not connected via cross coupled most significant bit (MSB) switches (The first and second transistors are not connected via any resistor and thus not connected via cross coupled MSB switches). With respect to claim 12, a wireless communication apparatus (phased array transceiver which the circuitry of Figs. 2(a)-2(d) are used within, see paragraphs 0002, 0004 and 0058) comprising: a phased array transmission circuit comprising a plurality of split signal paths (Figs. 2(a) and 2(b) comprise a VGA of one of the transmission paths of split between the multiple transmit channels of a phased array antenna, see paragraphs 0002, 0004 and 0058), wherein a first path of the plurality of split signal paths comprises a first radio frequency (RF) variable gain amplifier (VGA) (one of the VGAs of Figs. 2(a) and 2(b)), the first RFVGA comprising: a first transistor (left side M2) comprising a first gate (gate of left side M2), a first source (source of left side M2), and a first drain (drain of left side M2), wherein the first gate is coupled to a control input (common gate bias voltage, note M2 is a common gate transistor and must have a bias voltage common to its gate, see para 0053), and wherein the first drain is coupled to a first terminal of an output (output at drain); a second transistor (right side M2) comprising a second gate (gate of right side M2), a second source (source of right side M2), and a second drain (drain of right side M2), wherein the second gate is coupled to the control input (common gate bias voltage of the common gate transistor of the right side M2), and wherein the second drain is coupled to a second terminal of the output (output at drain); a third transistor (left side M3 of Fig. 2(a); left side M1 of Fig. 2(b)) comprising a third gate (gate of left side M3 of Fig. 2(a); gate of left side M1 of Fig. 2(b)), a third source (source of left side M3 of Fig. 2(a); source of left side M3 of Fig. 2(b)), and a third drain (drain of left side M3 of Fig. 2(a); drain of left side M1 of Fig. 2(b)), wherein the third drain is coupled to the first source (respective drain and source are connected as claimed), and wherein the third gate is coupled to a first terminal of an input (Vin+); and a fourth transistor (right side M3 of Fig. 2(a); right side M1 of Fig. 2(b)) comprising a fourth gate (gate of right side M3 of Fig. 2(a); gate of right side M1 of Fig. 2(b)), a fourth source (source of right side M3 of Fig. 2(a); source of right side M1 of Fig. 2(b)), and a fourth drain (drain of right side M3 of Fig. 2(a); drain of right side M1 of Fig. 2(b)), wherein the fourth drain is coupled to the second source (respective drain and source are connected as claimed), and wherein the fourth gate is coupled to a second terminal of the input (Vin-); wherein the first source is not connected to the second drain via one or more transistors (the first and second sources are not connected), and wherein the second source is not connected to the second drain via one or more transistors (the second source is not connected to the second drain via one or more transistors. It is understood/interpreted that “one or more transistors” is in addition to the second transistor). With respect to claim 13, the wireless communication apparatus of claim 12, further comprising: transceiver circuitry coupled to the first terminal of the input and the second terminal of the input (transceiver circuit operative with the VGA, e.g., LNAS, phase shifter, etc. see paragraph 0058); and an antenna element coupled to the first terminal of the output and the second terminal of the output (antenna connected to the VGA of the transmitter channel of the phased array antenna, see paragraph 0058). With respect to claim 15, the wireless communication apparatus of claim 12, wherein the third source and the fourth source are coupled to a reference voltage node (ground). With respect to claim 16, the wireless communication apparatus of claim 12, further comprising: a fifth transistor (left side M1 of Fig. 2(a)) comprising a fifth source (source of left side M1 of Fig. 2(a)), a fifth drain (drain of left side M1 of Fig. 2(a)), and a fifth gate (gate of left side M1 of Fig. 2(a)), wherein the fifth source is coupled to the first source (sources of left side M1 and M2 are connected), wherein the fifth gate is coupled to a second control input (control circuit signal that activates/deactivates M1, see paras 0053 063), and wherein the fifth drain is coupled to a voltage power node (voltage connected to drain of M1, e.g., upper rail voltage); and a sixth transistor (right side M1 of Fig. 2(a)) comprising a sixth source (source of right side M1 of Fig. 2(a)), a sixth drain (drain of right side M1 of Fig. 2(a)), and a sixth gate (gate of right side M1 of Fig. 2(a)), wherein the sixth source is coupled to the second source (sources of right side M1 and M2 are connected), wherein the sixth gate is coupled to the second control input (control signal for turning on and off M1 see paras 0053 and 0063), and wherein the sixth drain is coupled to the voltage power node (power supply at drain, e.g., upper rail voltage) . 07-15-aia AIA Claim(s) 1 and 6 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Lee et al. (USPAPN 2023/0188103) . With respect to claim 1, Lee et al. discloses, in Figs. 2-4, a radio frequency (RF) variable gain amplifier (VGA) (Fig. 3 construction details of 110-1 to 110-n and 130-1 to 130-m disclose in Fig. 4) comprising: a first transistor (i.e., left most transistor of 110-1 of Fig. 2 that has a drain directly connected to 180) comprising a first gate (gate of the first transistor), a first source (source of the first transistor), and a first drain (drain of the first transistor), wherein the first gate is coupled to a control input (output of 290 directly connected to the gate of the first transistor), and wherein the first drain is coupled to a first terminal of an output (at 180); a second transistor (i.e., right most transistor of 110-1 of Fig. 2 that has a drain connected directly to 180) comprising a second gate (gate of second transistor), a second source (source of second transistor), and a second drain (drain of second transistor), wherein the second gate is coupled to the control input (the first and second transistors have a gate connected to the same output signal of 290), and wherein the second drain is coupled to a second terminal of the output (other terminal/line of 180 directly connected to the drain of second transistor); a third transistor (left most transistor of 110-1 having a gate directly connected to 170 and a drain directly connected to the source of the first transistor) comprising a third gate (gate of the third transistor), a third source (source of the third transistor), and a third drain (drain of the third transistor), wherein the third drain is coupled to the first source (the drain and source are connected as claimed), and wherein the third gate is coupled to a first terminal of an input (output of 170 directly connected to the gate of the third transistor); and a fourth transistor (right most transistor of 110-1 having a gate directly connected to 170 and a drain directly connected to the source of the second transistor) comprising a fourth gate (gate of the fourth transistor), a fourth source (source of the fourth transistor), and a fourth drain (drain of the fourth transistor), wherein the fourth drain is coupled to the second source (the drain and source are connected as claimed), and wherein the fourth gate is coupled to a second terminal of the input (gate of the fourth transistor directly connected to the other output of 170); wherein the first source is not connected to the second drain via one or more transistors (the first source and second drain are not connected via any device including a transistor), and wherein the second source is not connected to the second drain via one or more transistors (the second source is not connected to the second drain via an additional transistor that is different from the second transistor). With respect to claim 6, the RFVGA of claim 1, further comprising a plurality of parallel VGA amplifier units (110-2 and 110-n of Fig. 2), wherein a first unit of the plurality of parallel VGA amplifier units comprises the first transistor, the second transistor, the third transistor, and the fourth transistor (i.e., transistors of the above VGA amplifier units that are essentially duplicates of the transistors of 110-1) . 07-15-03-aia AIA Claim(s) 18-19 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Bourque et al. (USPAPN 2024/0022213) With respect to claim 18, Bourque et al. discloses, in Fig. 3, radio frequency (RF) (radio frequency is merely intended use which Bourque et al. is capable of providing) variable gain amplifier (VGA) (variable under the control of VS) comprising an RFVGA unit in a folded configuration (folded cascode), the RFVGA unit comprising: a first transistor (MP_CAS2) comprising a first gate (gate), a first source (source), and a first drain (drain), wherein the first gate is coupled to a control input (VCASP), wherein the first source is coupled to a first terminal of an output (output current of MP_CAS2 to MN_CAS2, i.e., drain current output. The source terminal of MP_CAS2 is coupled to its drain terminal via the source to drain conduction path of MP_CAS2), and wherein the first drain is coupled to a voltage source via a first resistive element (VDD via R4, the source to drain conduction path of MP_ISCR2 and the source to drain conduction path of MP_CAS2); a second transistor (MP_CAS) comprising a second gate (gate), a second source (source), and a second drain (drain), wherein the second gate is coupled to the control input (MP_CAS), wherein the second source is coupled to a second terminal of the output (B_P node where in source is connected to B_P via the source to drain conduction path of MP_CAS) and wherein the second drain is coupled to the voltage source via a second resistive element (VDD via R2, the source to drain conduction path of MP_IRSC and the source to drain conduction path of MP_CAS); a third transistor (MN1) comprising a third gate (gate), a third source (source), and a third drain (drain), wherein the third drain is coupled to the first drain (drain of MN1 is coupled to the drain of MP_CAS2 via the source to drain conduction path of MP_CAS2), and wherein the third gate is coupled to a first terminal of an input (IN-); and a fourth transistor (MN2) comprising a fourth gate (gate), a fourth source (source), and a fourth drain (drain), wherein the fourth drain is coupled to the second drain (via the source to drain conduction path of MP_CAS), and wherein the fourth gate is coupled to a second terminal of the input (IN+). With respect to claim 19, the RFVGA of claim 18, wherein the third source is coupled to a reference voltage (ground via INN), and wherein the fourth source is coupled to the reference voltage (ground via INN) . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 2, 7-8, 14, 17 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thomas J. Hiltunen whose telephone number is (571)272-5525. The examiner can normally be reached 9:00AM-5:30PM EST M-F. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at (571)270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /THOMAS J. HILTUNEN/Primary Examiner, Art Unit 2836 Application/Control Number: 18/611,657 Page 2 Art Unit: 2836 Application/Control Number: 18/611,657 Page 3 Art Unit: 2836 Application/Control Number: 18/611,657 Page 4 Art Unit: 2836 Application/Control Number: 18/611,657 Page 5 Art Unit: 2836 Application/Control Number: 18/611,657 Page 6 Art Unit: 2836 Application/Control Number: 18/611,657 Page 7 Art Unit: 2836 Application/Control Number: 18/611,657 Page 8 Art Unit: 2836 Application/Control Number: 18/611,657 Page 9 Art Unit: 2836 Application/Control Number: 18/611,657 Page 10 Art Unit: 2836 Application/Control Number: 18/611,657 Page 11 Art Unit: 2836 Application/Control Number: 18/611,657 Page 12 Art Unit: 2836
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