DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 7, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (U.S. 2015/0324447), and in view of Prohofsky et al (U.S. 10,176,212).
Regarding claim 1:
A data processing method performed by a processor in a hybrid memory system comprising different types of memory media including a first memory medium and a second memory medium, the method comprising: obtaining data distribution of data in the different types of memory media in the hybrid memory system, the data distribution being determined based on hot and cold degrees of the data and at least one of a latency, costs, a capacity, and a service life; Kim, Fig. 1, a hybrid memory system (DBMS) comprises memory 122, and disk 125. Fig. 1, logical storages 132 and 134 may include a memory partition 132 that stores the hot data and a disk partition 134 that stores the cold data. The logical table mapping unit 130 may store the cold data and the hot data, respectively, in the disk partition 134 and the memory partition 132 among the partitions constituting the partitioned table. The hot data may represent data that satisfies a preset condition, and the cold data may represent data that does not satisfy the preset condition. Fig. 2, the hybrid DBMS 200 may divide data constituting the partitioned table into partitions in the hybrid partitioned table 230, classify data of the partitions into hot data and cold data, and store the hot data and the cold data in different logical storages 260 and 270, that is, a memory partition 260 and a disk partition 270. The hot data may be stored in the memory partition 260 and the cold data may be stored in the disk partition 270. Thus, the data distribution is also determined based on latency of the medium where data is stored.
The hybrid DBMS of Kim can classify hot data or cold data into corresponding partition. Thus, the hybrid DBMS is capable of obtaining or managing data distribution in first memory medium (memory 122), second memory medium (disk 125), and the data distribution is determined based on hot and cold degrees of the data and the latency of the memory mediums (hot data is stored in memory 122, which has lower latency than disk 125). One ordinary skill in the art would able to derive from Kim the idea of obtaining data distribution of data in the different types of memory media in the hybrid memory system. However, to advance prosecution, Prohofsky reference discloses data migration may include maintaining a heat map for data stored to one or more storage devices of a tiered storage system. A heat map may include a log of a quantity or frequency of data accesses to data files, map units, or other data “chunks” on the memory. Frequently accessed data may be considered “hot,” while infrequently accessed data may be considered “cold.” It may be advantageous to maintain hot data on higher storage tiers with rapid data access rates in order to quickly respond to host requests for commonly accessed data. In order to maximize an amount of hot data available on higher tiers, cold data may be moved to a lower tier (Prohofsky, 11:50-60, Fig. 6, 13:15-40). Frequently accessed data may be stored to the faster memory, and less frequently accessed data may be stored to the slower memory. Data may be migrated between the different tiers of memory storage based on an access history of the data. In some embodiments, memories may be selected for caching or tiering based on characteristics besides random access speeds, such as storage reliability, sequential access speed, cost, or other factors (Prohofsky 2:45-55).
One of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to incorporate the teaching of Prohofsky into the teaching of Kim to obtain the idea of obtaining data distribution of data in the different types of memory media in the hybrid system of Kim, and the data distribution is also determined based on the tier storage or latency and cost corresponding to the tier storage. The motivation for doing so is to apply a known technique to the apparatus/method, ready for improvement of Kim, to yield predictable results.
determining a data migration manner based on the data distribution, wherein the data migration manner is for implementing migration processing on a migration data set to be migrated between the first memory medium and the second memory medium based on the data distribution; and performing migration processing on the migration data set based on the migration manner. Kim, classifying data constituting tables with respect to each of partitions; classifying the data constituting the partitions into hot data and cold data, based on data attribute, with respect to each of the partitions; storing the hot data and the cold data in different logical storage spaces; checking data attributes of the hot data and the cold data at preset periods and reclassifying the hot data and the cold data based on the checked data attributes; and updating logical storage spaces of the reclassified hot data and the reclassified cold data, ¶0014-0015), and Fig. 6, ¶0059, data from physical storage space from memory tablespace is moved to the disk table space, Fig. 8, classifying data into hot or cold data based on usage frequency. Prohofsky also teaches a process for data migration or promotion from a second storage tier to a first storage tier (Fig. 6, 13:15-40).
Regarding claim 7:
The method according to claim 1, wherein the migration data set comprises a first data set, the first data set comprises at least one piece of hot data, and the hot data has a quantity of times of being read and written in a unit periodicity greater than the first threshold. Kim, hot data or cold data is classified based on usage or access frequency of the data versus a threshold (¶0063).
Regarding claim 12:
The method according to claim 1, wherein the first memory medium is a dynamic random access memory DRAM, the second memory medium is a storage-class memory SCM comprising a phase-change memory PCM, a magnetoresistive random-access memory MRAM, a resistive random access memory RRAM, a ferroelectric random access memory FRAM, a fast NAND, or a nano-RAM NRAM. Prohofsky, First tier DSD 104 and second tier DSD 106 may include any types of devices used to store or retrieve data, such as SSDs, HDDs, hybrid hard drives (HHDs), other memories, or any combination thereof. While a single first tier DSD 104 and second tier DSD 106 are depicted, each tier may include multiple storage devices. In some embodiments, multiple storage mediums and multiple memory tiers may be included in a single storage device. In some embodiments, a given tier may include different types of storage devices (3:55-65).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (U.S. 2015/0324447), and in view of Prohofsky et al (U.S. 10,176,212), and further in view of Davies et al (U.S. 2011/0252210).
Regarding claim 2:
The method according to claim 1, wherein the processor is associated with a least recently used (LRU) linked list, wherein the LRU linked list is used to record a cold and hot degree of stored data in a memory resource allocated to the processor, and comprises an active list and an inactive list, the active list identifies information about a memory page on which hot data associated with the processor is located, and the inactive list identifies information about a memory page on which cold data associated with the processor is located. Lepak teaches profile list comprises hot memory pages list 455, cold memory pages list 456 (Fig. 4, ¶0077-0079); each list comprises a plurality of entries, which includes address/location of corresponding page (Fig. 4, ¶0078).
However, Lepak does not teach using LRU linked list to record cold and hot degree of stored data. In an analogous art of storage management, Davies teaches the use of linked lists, which is ordered according to hot and cold pages, and includes an identifier for each page (¶0007, ¶0039, Fig. 4a and corresponding text).
One of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to incorporate the teaching of Davies into the teaching of Lepak to implement linked list for recording cold and hot pages in storage device. The motivation for doing so is to apply a known technique, taught by Davies, into a known method/apparatus of Lepak, ready for improvement to yield predicable results, which improving storage utilization by rebalancing allocated storage pages among storage tier (Davies, ¶007).
Claims 3, 6 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (U.S. 2015/0324447), and in view of Prohofsky et al (U.S. 10,176,212), and in view of Davies et al (U.S. 2011/0252210), and further in view of Kim et al (U.S. 2019/0189193).
Regarding claim 3:
The combination of Lepak does not teach the method according to claim 2, further comprising: obtaining a scanning request; traversing, based on the scanning request, data distribution of memory pages in the first memory medium and the second memory medium that are associated with a first processor in the hybrid memory system, wherein the data distribution comprises statuses of the memory pages in the first memory medium and the second memory medium, and the status of the memory page comprises a hot page, a cold page, or a free page. In an analogous art of data storage operation, Kim teaches storage controller (Fig. 1, 220) performs scan operation in response to receiving a scan command from a host, and checks a read count, erase count for each memory blocks in a storage device (¶0029). Fig. 1, nonvolatile memory device 10 comprises a plurality of blocks, each block further comprises a plurality of pages including free pages (¶0035, ¶0037).
One of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to incorporate the teaching of Kim into the teaching of Lepak to receive a scanning request, obtain access count of memory blocks in storage system. The motivation for doing so is to apply a known technique, taught by Kim, into a known method/apparatus of Lepak, ready for improvement to yield predicable results, which improves operation performance (Kim, ¶0005).
Regarding claim 6:
The method according to claim 3, wherein prior to the step of obtaining the scanning request, the method further comprises: collecting statistics, at a unit periodicity, on a quantity of times that data in a first memory page is read; and increasing a popularity value of the first memory page by one each time a read operation is performed on the data in the first memory page, wherein the popularity value indicates a cold and hot degree in which the data in the first memory page is accessed in the unit periodicity. Kim, Fig. 2, storage device carries out process to check read count or erase count of each memory block in the storage device (Fig. 2, S215, and corresponding text). The controller continuously check read count and erase count (¶0054). Davies also teaches using an I/O counter to track I/O access for each memory page in a storage device (Davies, ¶0043-¶0044). I/O counter is increase for each I/O to corresponding memory page.
Claims 4 are rejected under 35 U.S.C. 103 as being unpatentable Kim et al (U.S. 2015/0324447), and in view of Prohofsky et al (U.S. 10,176,212), and in view of Davies et al (U.S. 2011/0252210), and further in view of Kim et al (U.S. 2019/0189193), and further in view of Cascaval et al (U.S. 2007/0180215).
Regarding claim 4:
The method according to claim 3, wherein the first memory medium comprises a first huge-page memory pool, the second memory medium comprises a second huge-page memory pool, and sizes of memory pages in the first huge-page memory pool and the second huge-page memory pool are greater than a first threshold. The combination of Lepak does not teach the claimed limitations above. However, in an analogous art of storage access, Cascaval teaches most hardware and operating systems support multiple memory page sizes, such as large page and small page. Memory maybe partitioned into small-page and large-page pools (¶0005-¶0006).
One of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to incorporate the teaching of Cascaval into the combination of Lepak to have a first memory comprises a first huge-page pool, and second memory comprises a second huge-page pool, which sizes are greater than a threshold. The motivation for doing so is to apply a known technique, taught by Cascaval, into a known method/apparatus of Lepak, ready for improvement to yield predictable results, which optimize performance, and large page utilization (Cascaval, ¶0015).
Claim 5 rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (U.S. 2015/0324447), and in view of Prohofsky et al (U.S. 10,176,212), and in view of Davies et al (U.S. 2011/0252210), and further in view of Kim et al (U.S. 2019/0189193), and further in view of Tati et al (U.S. 9,063,866).
Regarding claim 5:
The method according to claim 3, wherein the step of obtaining the scanning request comprises: obtaining the scanning request on a periodic basis, wherein the scanning request for periodically collecting statistics on the cold and hot degrees of the memory pages in the first memory medium and the second memory medium. Lepak does not teach the claimed limitations above. However, in an analogous art of storage management, Tati teaches the idea of periodically scanning management table, to determine whether memory pages have been accessed or not, and for each memory page, determining an activity level of the memory page based on whether the memory page has been accessed or not since a prior scan and storing the activity level of the memory page (Tati, 1:55-65). One of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to incorporate the teaching of Tati into the combination of Lepak to consider receiving/obtaining the scanning request on a periodic basis. The motivation for doing so is to apply a known technique, taught by Cascaval, into a known method/apparatus of Lepak, ready for improvement to yield predictable results, which improving system efficiency by training activity level of memory pages (Tati, abstract).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (U.S. 2015/0324447), and in view of Prohofsky et al (U.S. 10,176,212), and further in view of Kolvick et al (U.S. 2015/0121024).
Regarding claim 8:
The combination of Lepak does not teach the method according to claim 1, wherein the step of determining the data migration manner based on the data distribution comprises: determining a hierarchical memory mechanism in the hybrid memory system, wherein the hierarchical memory mechanism indicates levels of the multiple different types of memory media in the hybrid memory system, the hybrid memory system comprises multiple levels, and the multiple levels comprise a first level and a second level; and determining the data migration manner based on the data distribution and the hierarchical memory mechanism.
In an analogous art of data management based on frequency access, Kolvick teaches in Figs. 1-5, and corresponding text, determining a hierarchical memory mechanism in the hybrid memory system, wherein the hierarchical memory mechanism indicates levels of the multiple different types of memory media in the hybrid memory system; a storage controller (Fig. 1, 100) identifying a plurality of memory tiers (¶0017
the hybrid memory system comprises multiple levels, and the multiple levels comprise a first level and a second level; and determining the data migration manner based on the data distribution and the hierarchical memory mechanism; memory modules (110, 112, 114, 116) that include identical operational characteristics may be grouped into the same memory tier (136, 138, 140), ¶0017; the controller migrates data from first tier to second tier, based on characteristic of memory tier, and data characteristics of data block in the plurality of memory tiers (Fig. 1, 108, ¶0021-¶0023).
One of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to incorporate the teaching of Kolvick into the teaching combination of Lepak to determine configuration of the memory system in order to perform data migration. The motivation for doing so is to apply a known technique, taught by Kolvick, into a known method/apparatus of Lepak, ready for improvement to yield predicable results.
Claims 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (U.S. 2015/0324447), and in view of Prohofsky et al (U.S. 10,176,212), and in view of Davies et al (U.S. 2011/0252210), and further in view of Kolvick et al (U.S. 2015/0121024), and further in view of Cascaval et al (U.S. 2007/0180215).
Regarding claim 9:
The method according to claim 8, wherein the first memory medium belongs to the first level, and the second memory medium belongs to the second level, and wherein the step of determining the data migration manner based on the data distribution and the hierarchical memory mechanism comprises: selecting one or more free memory pages from a first huge-page memory pool, and migrating the first data set comprising data of a hot page in the second memory medium to the one or more free memory pages in the first huge-page memory pool. Lepak, the memory controller identifies hot memory pages on a slow-tiered memory and, either automatically or under command, moves or copies such hot memory pages to a fast-tiered memory page (¶0013, ¶0019-0020). Kolvick also suggests migrate data into spare (free) block, (¶006, ¶0019). However, the combination of Lepak and Kolvick does not teach first memory medium or second memory medium comprises huge-page memory pool. In an analogous art of storage access, Cascaval teaches most hardware and operating systems support multiple memory page sizes, such as large page and small page. Memory maybe partitioned into small-page and large-page pools (¶0005-¶0006).
One of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to incorporate the teaching of Cascaval into the combination of Lepak to have a first memory comprises a first huge-page pool, and second memory comprises a second huge-page pool, which sizes are greater than a threshold. The motivation for doing so is to apply a known technique, taught by Cascaval, into a known method/apparatus of Lepak, ready for improvement to yield predictable results, which optimize performance, and large page utilization (Cascaval, ¶0015).
Regarding claim 10:
The method according to claim 8, wherein the first memory medium belongs to the first level, and the second memory medium belongs to the second level, wherein the migration data set further comprises a second data set comprising at least one piece of cold data having a quantity of times of being read and written in a unit periodicity less than or equal to a second threshold, and wherein the step of determining the data migration manner based on the data distribution and the hierarchical memory mechanism comprises: selecting one or more free memory pages from a second huge-page memory pool, and migrating the second data set comprising data of a cold page in the first memory medium to the one or more free memory pages in the second huge-page memory pool. Kolvick suggests the idea of migrate data from a memory block of a first tier to a spare block of a second tier, based on characteristics of data in the memory block (Fig. 1, 106, 108, Fig. 2, 102-210 and corresponding text), where data characteristics include hot and cold data (¶0027). Kolvick also suggests migrate data into spare (free) block, (¶006, ¶0019). Lepak, the memory controller identifies hot memory pages on a slow-tiered memory and, either automatically or under command, moves or copies such hot memory pages to a fast-tiered memory page (¶0013, ¶0019-0020). However, the combination of Lepak and Kolvick does not teach first memory medium or second memory medium comprises huge-page memory pool. In an analogous art of storage access, Cascaval teaches most hardware and operating systems support multiple memory page sizes, such as large page and small page. Memory maybe partitioned into small-page and large-page pools (¶0005-¶0006).
One of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to incorporate the teaching of Cascaval into the combination of Lepak to have a first memory comprises a first huge-page pool, and second memory comprises a second huge-page pool, which sizes are greater than a threshold. The motivation for doing so is to apply a known technique, taught by Cascaval, into a known method/apparatus of Lepak, ready for improvement to yield predictable results, which optimize performance, and large page utilization (Cascaval, ¶0015).
Regarding claim 11:
The method according to claim 10, further comprising: migrating the first data set comprising data of a hot page in the second memory medium to one or more free memory pages in a first huge-page memory pool. Lepak, the memory controller identifies hot memory pages on a slow-tiered memory and, either automatically or under command, moves or copies such hot memory pages to a fast-tiered memory page (¶0013, ¶0019-0020). Kolvick also suggests migrate data into spare (free) block, (¶006, ¶0019). However, the combination of Lepak and Kolvick does not teach first memory medium or second memory medium comprises huge-page memory pool. In an analogous art of storage access, Cascaval teaches most hardware and operating systems support multiple memory page sizes, such as large page and small page. Memory maybe partitioned into small-page and large-page pools (¶0005-¶0006).
One of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to incorporate the teaching of Cascaval into the combination of Lepak to have a first memory comprises a first huge-page pool, and second memory comprises a second huge-page pool, which sizes are greater than a threshold. The motivation for doing so is to apply a known technique, taught by Cascaval, into a known method/apparatus of Lepak, ready for improvement to yield predictable results, which optimize performance, and large page utilization (Cascaval, ¶0015).
Claims 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (U.S. 2015/0324447), and in view of Prohofsky et al (U.S. 10,176,212), and in view of over Lepak et al (U.S. 2022/0317925).
Regarding claim 13:
The method according to claim 1, wherein the processor is connected to the multiple different types of memory media through an interface supporting memory semantics, and the interface supports a compute express link CXL, a cache coherent interconnect for accelerators CCIX, or a unified bus UB. The combination of Kim does not teach the claimed limitations above, but in an analogous art of storage management, Lepak suggests using memory interface including JEDEC NVDIMM-P standard and compute express link (CXL) standard, to communicate with CPU (¶0014, ¶0016). One of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to incorporate the teaching of Lepak with Kim and Prohofsky to have a processor capable of communicates with different type of memory via CXL link. The motivation for doing so is to apply a known technique of Lepak to a known device/method of Kim ready for improvement, to yield predictable results.
Claims 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (U.S. 2015/0324447), and in view of Prohofsky et al (U.S. 10,176,212), and in view of over Lepak et al (U.S. 2022/0317925).
Regarding claim 14:
A processor comprising: an interface; and an integrated circuit connected to multiple different types of memory media via the interface, wherein the integrated circuit is configured to cause the processor to: obtain data distribution of data in the different types of memory media in the hybrid memory system, wherein the data distribution being determined based on hot and cold degrees of the data and physical attributes of memory mediums, and the physical attributes comprise at least one of a latency, costs, a capacity, and a service life; determine a data migration manner based on the data distribution, wherein the data migration manner is for implementing migration processing on a migration data set between the first memory medium and the second memory medium based on the data distribution; and perform migration processing on the migration data set based on the migration manner. Claim 14 recites similar limitations cited in claim 1 but the “a processor comprising: an interface; and an integrated circuit connected to multiple different types of memory media via the interface, wherein the integrated circuit is configured to cause the processor to” limitations. In an analogous of storage management, Lepak discloses a processor comprises a controller 135 (Fig .1), Lepak suggests using memory interface including JEDEC NVDIMM-P standard and compute express link (CXL) standard, to communicate with CPU (¶0014, ¶0016). Fig. 1, process, 110 comprises integrated microcontroller 135. Lepak also discloses a technique to migrate host memory page in a second-tier memory to a first-tier memory (¶0020). One of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to incorporate the teaching of Lepak with Kim and Prohofsky to have a processor capable of performing data migration on hot and cold data as cited above. The motivation for doing so is to apply a known technique of Lepak to a known device/method of Kim ready for improvement, to yield predictable results.
Claim 15 recites similar limitations of claim 14, and is rejected under same rationale cited in claim 14.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (U.S. 2015/0324447), and in view of Prohofsky et al (U.S. 10,176,212), and in view of over Lepak et al (U.S. 2022/0317925), and in view of Davies et al (U.S. 2011/0252210).
Regarding claim 16:
The hybrid memory system according to claim 15, wherein the processor is associated with a least recently used (LRU) linked list used to record a cold and hot degree of stored data in a memory resource allocated to the processor, the LRU linked list comprises an active list and an inactive list, the active list identifies information about a memory page on which hot data associated with the processor is located, and the inactive list identifies information about a memory page on which cold data associated with the processor is located. Lepak teaches profile list comprises hot memory pages list 455, cold memory pages list 456 (Fig. 4, ¶0077-0079); each list comprises a plurality of entries, which includes address/location of corresponding page (Fig. 4, ¶0078).
However, Lepak does not teach using LRU linked list to record cold and hot degree of stored data. In an analogous art of storage management, Davies teaches the use of linked lists, which is ordered according to hot and cold pages, and includes an identifier for each page (¶0007, ¶0039, Fig. 4a and corresponding text).
One of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to incorporate the teaching of Davies into the teaching of Lepak to implement linked list for recording cold and hot pages in storage device. The motivation for doing so is to apply a known technique, taught by Davies, into a known method/apparatus of Lepak, ready for improvement to yield predicable results, which improving storage utilization by rebalancing allocated storage pages among storage tier (Davies, ¶007).
Claims 17, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (U.S. 2015/0324447), and in view of Prohofsky et al (U.S. 10,176,212), and in view of over Lepak et al (U.S. 2022/0317925), and in view of Davies et al (U.S. 2011/0252210), and further in view of Kim et al (U.S. 2019/0189193).
Regarding claim 17:
The combination of Lepak does not teach the hybrid memory system according to claim 16, wherein the processor is further configured to perform operations of: obtaining a scanning request; traversing, based on the scanning request, data distribution of memory pages in the first memory medium and the second memory medium that are associated with a first processor in the hybrid memory system, wherein the data distribution comprises statuses of the memory pages in the first memory medium and the second memory medium, and the status of the memory page comprises a hot page, a cold page, or a free page. In an analogous art of data storage operation, Kim teaches storage controller (Fig. 1, 220) performs scan operation in response to receiving a scan command from a host, and checks a read count, erase count for each memory blocks in a storage device (¶0029). Fig. 1, nonvolatile memory device 10 comprises a plurality of blocks, each block further comprises a plurality of pages including free pages (¶0035, ¶0037).
One of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to incorporate the teaching of Kim into the teaching of Lepak to receive a scanning request, obtain access count of memory blocks in storage system. The motivation for doing so is to apply a known technique, taught by Kim, into a known method/apparatus of Lepak, ready for improvement to yield predicable results, which improves operation performance (Kim, ¶0005).
Regarding claim 20:
The hybrid memory system according to claim 17, wherein prior to obtaining the scanning request, the processor is further configured to perform operations of: collecting statistics, at a unit periodicity, on a quantity of times that data in a first memory page is read; and increasing a popularity value of the first memory page by one each time a read operation is performed on the data in the first memory page, wherein the popularity value indicates a cold and hot degree in which the data in the first memory page is accessed in the unit periodicity. Kim, Fig. 2, storage device carries out process to check read count or erase count of each memory block in the storage device (Fig. 2, S215, and corresponding text). The controller continuously check read count and erase count (¶0054). Davies also teaches using an I/O counter to track I/O access for each memory page in a storage device (Davies, ¶0043-¶0044).
Claims 18 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (U.S. 2015/0324447), and in view of Prohofsky et al (U.S. 10,176,212), and in view of over Lepak et al (U.S. 2022/0317925), and in view of Davies et al (U.S. 2011/0252210), and further in view of Kim et al (U.S. 2019/0189193), and further in view of Cascaval et al (U.S. 2007/0180215).
Regarding claim 18:
The hybrid memory system according to claim 17, wherein the first memory medium comprises a first huge-page memory pool, the second memory medium comprises a second huge-page memory pool, and sizes of memory pages in the first huge-page memory pool and the second huge-page memory pool are greater than a first threshold. The combination of Lepak does not teach the claimed limitations above. However, in an analogous art of storage access, Cascaval teaches most hardware and operating systems support multiple memory page sizes, such as large page and small page. Memory maybe partitioned into small-page and large-page pools (¶0005-¶0006).
One of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to incorporate the teaching of Cascaval into the combination of Lepak to have a first memory comprises a first huge-page pool, and second memory comprises a second huge-page pool, which sizes are greater than a threshold. The motivation for doing so is to apply a known technique, taught by Cascaval, into a known method/apparatus of Lepak, ready for improvement to yield predictable results, which optimize performance, and large page utilization (Cascaval, ¶0015).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (U.S. 2015/0324447), and in view of Prohofsky et al (U.S. 10,176,212), and in view of over Lepak et al (U.S. 2022/0317925), and in view of Davies et al (U.S. 2011/0252210), and further in view of Kim et al (U.S. 2019/0189193), and further in view of Tati et al (U.S. 9,063,866).
Regarding claim 19:
The hybrid memory system according to claim 17, wherein the operation of obtaining the scanning request comprises: obtaining the scanning request on a periodic basis, wherein the scanning request is for periodically collecting statistics on the cold and hot degrees of the memory pages in the first memory medium and the second memory medium. Kim, Fig. 2, storage device carries out process to check read count or erase count of each memory block in the storage device (Fig. 2, S215, and corresponding text). The controller continuously check read count and erase count (¶0054). Davies also teaches using an I/O counter to track I/O access for each memory page in a storage device (Davies, ¶0043-¶0044). Lepak does not teach the claimed limitations above. However, in an analogous art of storage management, Tati teaches the idea of periodically scanning management table, to determine whether memory pages have been accessed or not, and for each memory page, determining an activity level of the memory page based on whether the memory page has been accessed or not since a prior scan and storing the activity level of the memory page (Tati, 1:55-65). One of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to incorporate the teaching of Tati into the combination of Lepak to consider receiving/obtaining the scanning request on a periodic basis. The motivation for doing so is to apply a known technique, taught by Cascaval, into a known method/apparatus of Lepak, ready for improvement to yield predictable results, which improving system efficiency by training activity level of memory pages (Tati, abstract).
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot in light of new rejection(s) presented supra.
The examiner respectfully notes, under Broadest Reasonable Interpretation, exemplary independent claim 1, has been interpreted as a method of operating a hybrid memory system, hot and cold data stored in different memory types, or memory tiers are managed and track via either mapping table, heat map, or other mechanism in the art. Since it is obvious and known in the art that hot data or frequently accessed data is stored in fast memory, or performance tier, an ordinary skill in the art would use a table, or heat map to access, promote or demote data based on the hotness or access count of the data and the memory medium where the data is stored. In other words, one ordinary skill in the art would need obtain a map or distribution of hot and cold data in different memories having different latency or cost, etc., in order to access and manage the system. Thus, the managing, tracking, or knowing where or when to access, reclassify, promote, demote, or migrate data between different memory types, as disclosed by Kim and Prohofsky, reads on the idea of obtaining data distribution of data in the different types of memory media in the hybrid memory system, wherein the data distribution being determined based on hot and cold degrees of the data and physical attributes of memory mediums, and the physical attributes comprise at least one of a latency, costs, a capacity, and a service life, and migrating the data according to the data distribution.
Conclusion
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/KHOA D DOAN/Primary Examiner, Art Unit 2133
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