DETAILED ACTION
Re Application No. 18/611674, this action responds to the amended claims dated 06/19/2026.
At this point, claims 1, 11, and 18 have been amended. Claims 3, 13, and 20 have been cancelled. Claims 1-2, 4-12, and 14-19 are pending.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-2, 4-12, and 14-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention, as follows:
Claims 1, 11, and 18:
Language “the DRAM and SCM” (e.g. claim 1, line 11). This limitation contains ambiguous antecedent basis, as there is support for the generic “a DRAM and SCM” as well as a specific “a second DRAM and SCM”, which makes it unclear whether “the DRAM and SCM” is specifically referring to the generic “a DRAM and SCM”. This could be corrected by, for example, providing specifying a “first DRAM and first SCM” and a “second DRAM and second SCM”;
Language “the allocation policy […] based on physical attributes […] one of the physical attributes being a memory capacity, an access latency, a cost, or a service life, the allocation policy further […] based on an access latency of the first processor accessing memory media” (e.g. claim 1, lines 10-14). The first limitation, that the allocation policy is based on physical attributes including memory capacity, access latency, cost, or service life implies that the allocation policy may be based on one or more of these attributes, and the attribute(s) chosen do not need to include access latency, as it is merely one of the enumerated options. However, the second, newly added limitation suggests that the allocation policy must be based on an access latency. If the allocation policy must be based on access latency, then the first limitation is rendered entirely redundant, as one of the options (access latency) is unequivocally true, and thus the remainder of the options are irrelevant, as only one of the options needs to be present;
Language “the allocation policy further indicating that the memory resource is determined, based on an access latency of the first processor accessing memory media, from the DRAM associated with the first processor in preference to the second DRAM associated with the second processor, and from the DRAM in preference to the SCM” (e.g. claim 1, lines 12-16). This limitation is indefinite. It is unclear what the relationship, if any, is between “and access latency” and the various “preference” of one component or another. It could mean that 1) the “preference” is for the component with the lower latency, and thus the first processor DRAM has lower latency than the second processor DRAM, and the DRAM has lower latency than the SCM, or 2) the access latency is an independent variable from the predefined preferences. As examiner is unable to determine the intended meaning, the limitation is indefinite.
Claims 2, 4-10, 12, 14-17, and 19, the claims are rejected as being dependent on one of claims 1, 11, and 18 above, respectively.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-7, 11-12, 14-15, and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Taylor et al (US 9189387 B1) in view of Satoyama et al (US 20120166748 A1).
Re claim 1, Taylor discloses the following:
A memory management method performed in a hybrid memory system comprising multiple processors and multiple different types of memory media (Figs 4-5 and 10, processing devices 1002-1:1002-K). The processing platform 1000 includes multiple processors (Fig. 10, processing devices 1002-1:1002-K) and multiple types of memory (Figs 4-5);
the multiple processors comprising a first processor associated with a dynamic random access memory (DRAM) and a storage-class-memory (SCM), and a second processor adjacent to the first processor and associated with a second DRAM and a second SCM, the method being performed by the first processor and comprising (Fig. 10; col. 1, lines 13-31; col. 5, lines 52-62; col. 11, lines 37-59). The storage system contains a DRAM tier as well as a SCM tier (col. 5, lines 52-62). Each of the hosts may be implemented as a processing device with a respective processor (first processor, second processor (Fig. 10, processing devices 1001-1:1002-K). Applicant has not explicitly defined what makes the processors “adjacent”. Accordingly, Examiner interprets the processing devices, which are connected to each other through the network, to be “adjacent”. Each processing device contains a respective memory (DRAM) (Fig. 10), as well as one of the storage arrays (SCM) (col. 1, lines 13-31). The processors of the processing platform collectively execute instructions implementing the method (col. 11, lines 37-59);
obtaining a memory allocation request, wherein the memory allocation request is generated for an application process running on the first processor (claim 8; col. 5, lines 19-31). The application program requests storage resources (memory allocation request), which are dynamically allocated (claim 8). The memory is implemented as a virtual (logical) address space, and is accessed using a virtual (logical) address (col. 5, lines 19-31).
in response to the memory allocation request, determining a memory resource from the DRAM and SCM based on an allocation policy, the allocation policy indicating the memory resource be determined based on physical attributes of the DRAM and SCM, one of the physical attributes being a memory capacity, an access latency, a cost, or a service life (col. 1, lines 13-41; col. 4, line 46 to col. 5, line 18). Memory is allocated to storage tiers based on requirements such as bandwidth/throughput and response time (access latency) and capacity requirements, relative to performance characteristics of the tiers;
the allocation policy further indicating that the memory resource is determined, based on an access policy of the first processor accessing memory media, from the DRAM associated with the first processor in preference to the second DRAM associated with the second processor, and from the DRAM in preference to the SCM; and (Figs. 4 and 8; col. 5, line 63 to col. 6, line 17). This limitation is indefinite, as noted above. Examiner interprets it to mean that allocation is based on access latency, and a processor’s local DRAM is preferred over both an SCM and another processor’s DRAM. The host prefers to access resources cached in the DRAM/virtual memory (DRAM) over an I/O access to the SCM, which is more expensive from a response time (access latency) perspective (col. 5, line 63 to col. 6, line 17). Furthermore, the first and second host/array pairs (first and second processors) communicate with each other over the array, which utilizes I/O semantics (Fig. 8), which, as noted above, are disfavored over local access to the DRAM (col. 5, line 63 to col. 6, line 17). Accordingly, accessing over a local DRAM (DRAM) is preferred over accessing data from a remote host/array (and thus the remote host/array’s DRAM (second DRAM));
allocating the memory resource to […] based on the allocation policy (col. 1, lines 13-41; col. 4, line 46 to col. 5, line 18). Memory is allocated to one of the tiers based on the allocation policy.
Taylor discloses allocating memory resources; furthermore, it discloses that memory is allocated in a virtual address space (Fig. 3); however, it does not explicitly use the word “logical address”. Accordingly, in the interest of furthering compact prosecution, Examiner has provided Satoyama.
Satoyama discloses the following:
the memory allocation request […] comprises a logical address […] allocating the memory resource to the logical address (¶ 131). The I/O command, which may cause allocation of a memory resource, is associated with a logical block address.
the allocation policy further indicating that the memory resource is determined, based on an access latency (¶ 14). The memory resources are classified (allocated) based on response time (access latency).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to integrate the logical addressing of Satoyama into the memory allocation of Taylor, because it would be applying a known technique to improve a similar device in the same way. Taylor disclose memory resource allocation. Satoyama also discloses memory resource allocation, which has been improved in a similar way to the claimed invention, to utilize logical addressing. It would have been obvious to use the logical addressing of Satoyama in the memory allocation of Taylor, because it would yield the predictable improvement of allowing resources to be flexibly mapped between logical addresses and underlying physical resources.
Re claim 2, Taylor and Satoyama disclose the method of claim 1, and Taylor further discloses that the step of determining the to-be-allocated memory resource comprises: determining the memory resource from the DRAM and SCM based on a memory medium type and the physical attributes of the DRAM and SCM (col. 1, lines 13-41; col. 4, line 46 to col. 5, line 18). The storage tiers comprise DRAM and SCM with different physical attributes.
Re claim 4, Taylor and Satoyama disclose the method of claim 2, and Taylor further discloses the following:
the step of determining the memory resource from the DRAM and SCM comprises: determining the DRAM as the memory resource; and (col. 1, lines 13-41; col. 4, line 46 to col. 5, line 18). See claim 1 above. DRAM is one of the resources in the tiers that may be selected.
determining third memory media associated with a second processor adjacent to the first processor (Fig. 10; col. 4, lines 20-31). There are a plurality of processors on the storage system; Applicant has not explicitly defined what it means for a processor to be “adjacent”; accordingly, Examiner interprets the plurality of processors to be adjacent to one another (Fig. 10; col. 4, lines 20-31). There are at least 3 tiers, a top tier, a bottom tier, and a middle tier.
Satoyama further discloses that when a remaining memory resource of the [memory] does not satisfy a memory resource requirement of the memory allocation request, determining third memory media […] as the memory resource (¶ 335). It is noted that this is a contingent limitation in a method claim; as such, it is considered to be not required, as the condition need not actually occur (MPEP § 2111.04(II)). Nonetheless, Satoyama discloses that when there is insufficient space (remaining memory resource does not satisfy a memory resource requirement), space is instead allocated on another tier (third memory media).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to integrate the logical addressing of Satoyama into the memory allocation of Taylor, because it would be applying a known technique to improve a similar device in the same way. Taylor disclose memory resource allocation. Satoyama also discloses memory resource allocation, which has been improved in a similar way to the claimed invention, to allocate to a different tier if one tier is full. It would have been obvious to modify the memory allocation of Taylor to utilize a different tier if one tier is full, as in Satoyama, because it would yield the predictable improvement preventing one resource from being overused.
Re claim 5, Taylor and Satoyama disclose the method of claim 2, and Taylor further discloses that the step of determining the memory resource from the DRAM and SCM comprises: […] determining the memory resource from the SCM (col. 1, lines 13-41; col. 4, line 46 to col. 5, line 18). It is noted that this is a contingent limitation in a method claim; as such, it is considered to be not required (MPEP § 2111.04(II)), for the reasons noted in claim 4 above. Nonetheless, Taylor discloses selecting from the available tiers, one of which is an SCM.
Satoyama discloses when a remaining storage space of the [first memory] associated with the multiple processors is less than a preset memory allocation granularity, determining the memory resource from [second memory] (¶ 335). It is noted that this is a contingent limitation in a method claim; as such, it is considered to be not required, (MPEP § 2111.04(II)). Nonetheless, Satoyama discloses that when there is insufficient space (remaining storage space is less than a preset memory allocation granularity), space is instead allocated on another tier (second memory).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to combine Taylor and Satoyama, for the reasons noted in claim 4 above.
Re claim 6, Taylor and Satoyama disclose the method of claim 5, and Taylor further discloses that the step of determining the memory resource from the SCM comprises: determining the SCM as the memory resource; and […] determining a second SCM associated with a second processor adjacent to the first processor as the memory resource (Fig. 10; col. 4, lines 20-31). There are a plurality of processors on the storage system; Applicant has not explicitly defined what it means for a processor to be “adjacent”; accordingly, Examiner interprets the plurality of processors to be adjacent to one another (Fig. 10; col. 4, lines 20-31). There are at least 3 tiers, a top tier, a bottom tier, and a middle tier.
Satoyama discloses when a remaining memory resource of the [second memory] associated with the first processor does not satisfy the memory resource requirement of the memory allocation request, determining a [second memory] associated with a second processor (¶ 335). It is noted that this is a contingent limitation in a method claim; as such, it is considered to be not required (MPEP § 2111.04(II)), for the reasons noted in claim 4 above. Nonetheless, Satoyama discloses that when there is insufficient space (remaining memory resource of the memory allocation request), space is instead allocated on another tier (second memory media).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to combine Taylor and Satoyama, for the reasons noted in claim 4 above.
Re claim 7, Taylor and Satoyama disclose the method of claim 1 above, and Taylor further discloses that the SCM comprises: a phase-change memory (PCM), a magnetoresistive random access memory (MRAM), a resistive random access memory (RRAM), a ferroelectric random access memory (FRAM), a fast NAND, or a nano-ranodm access memory (NRAM) (col. 4, lines 20-31). The SCM tier may include a NAND. It is noted that Applicant has not provided a specific definition of what qualifies as “fast” NAND; accordingly, Examiner interprets the NAND of Taylor to be “fast” in that it is faster than slow forms of persistent storage such as hard drives and tape storage.
Re claims 11-12 and 14-15, respectively, Taylor and Satoyama disclose the methods of claims 1-2, 5, and 7 above, respectively; accordingly, they also disclose apparatuses implementing those methods, as in claims 11-12 and 14-15, respectively (See Taylor, abstract).
Re claims 18-19, respectively, Taylor and Satoyama disclose the methods of claims 1-2 above, respectively; accordingly, they also disclose computer systems implementing those methods, as in claims 18-19, respectively (See Taylor, claim 19). Furthermore, Taylor discloses that each processor of the multiple processors is associated with at least two different types of memory media (Fig. 10; col. 4, lines 20-31).
Claims 8-9 and 16-17 are rejected under 35 U.S.C. 103 as unpatentable over Taylor in view of Satoyama, further in view of Johnson (US 2010/0306451 AA1).
Re claim 8, Taylor and Satoyama disclose the method of claim 1, but do not specifically disclose allocating resources based on granularity larger than a page.
Johnson discloses that the step of allocating the memory resource to the logical address based on the allocation policy comprises: allocating the memory resource corresponding to the logical address based on the preset memory allocation granularity, wherein the preset memory allocation granularity is greater than a page size of a memory medium (¶ 22 and 29). The memory resources can be allocated in units of blocks (¶ 29), which are larger than pages (¶ 22).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the memory allocation of Taylor (combined with Satoyama) to allocate memory in block units, as in Johnson, because it would be applying a known technique to improve a similar method in the same way. Taylor (combined with Satoyama) discloses allocating memory. Johnson also discloses allocating memory, and has been improved in a similar way to the claimed invention, to allocate memory in a granularity larger than a page (such as a block). It would have been obvious to modify the granularity of Taylor (combined with Satoyama) to be larger than a page, because it would yield the predictable improvement of allowing data to be allocated and deallocated (i.e. erased) at the same data granularity, as flash memory can only be erased at the block level.
Re claim 9, Taylor and Satoyama disclose the method of claim 1, but do not specifically disclose releasing memory resources.
Johnson discloses releasing the memory resource at the preset memory allocation granularity in response to a release instruction instructing to release the memory resource (¶ 28-29). The memory can be deleted (released) at the block (memory allocation granularity) level based on a delete request (release instruction).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to combine Taylor, Satoyama, and Johnson, for the reasons noted in claim 8 above.
Re claims 16-17, respectively, Taylor, Satoyama, and Johnson disclose the methods of claims 8-9, respectively; accordingly, they also disclose apparatuses implementing those methods, as in claims 16-17, respectively (See Taylor, abstract).
Claim 10 is rejected under 35 U.S.C. 103 as unpatentable over Taylor in view of Satoyama, further in view of Lepak (US 2022/0317925 A1).
Re claim 10, Taylor and Satoyama disclose the method of claim 1, and Taylor further discloses that the first processor is connected to the DRAM and SCM through interfaces supporting memory semantics (Fig. 10). The processors are connected to the memory types over interfaces, which support memory semantics, as they are connected to memory.
Taylor and Satoyama do not disclose the specific interfaces listed in the claim.
Lepak discloses that the first processor is connected to the [memories] through interfaces supporting memory semantics, and the interfaces comprise an interface supporting memory semantics, and the interfaces comprise an interface supporting a compute express link (CXL), a cache coherent interconnect for accelerators (CCIX) protocol, or a unified bus (UB) (¶ 16). The processors are connected to various memory tiers by interfaces such as CXL.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to utilize a CSX interface such as the one of Lepak in the memory interfaces of Taylor (combined with Satoyama), because Lepak suggests that connecting memory devices over CXL would yield the improvement of allowing memory devices to be attached using a differential serializer/deserialize (SerDes) link (¶ 14).
ACKNOWLEDGEMENT OF ISSUES RAISED BY THE APPLICANT
Response to Amendment
Applicant’s arguments with respect to claims 1-2, 4-12, and 14-19 filed 06/19/2026 have been fully considered, but are either not deemed persuasive, or are rendered moot in view of new grounds for rejection.
As required by M.P.E.P. § 707.07(f), a response to these arguments appears below.
ARGUMENTS CONCERNING PRIOR ART REJECTIONS
Re claims 1, 11, and 18, Applicant argues that Taylor and Satoyama do not disclose the claimed invention, for 5 reasons.
First, Applicant argues that Taylor discloses tiers that are user specified, as opposed to “automatic, latency-based selection performed by a processor among memory media distinguished by their physical association with particular processors”. In response, Applicant’s first argument has been fully considered, but is not deemed persuasive, for 3 reasons. First, it is noted that several of the newly amended limitations are indefinite, for the reasons noted above. Second, it is noted that the claims do not actually require the selection to be “automatic”; moreover, this would be obvious as a mere automating of a manual activity (MPEP § 2144.04(III)). Additionally, Taylor actually does disclose “automatic” tier management (Abstract). Third, Taylor discloses allocating storage resources in the DRAM for the most recently used data based on a desire to access it quickly, and avoid a relatively costly (from a response time/access latency perspective) I/O access from the SCM (col. 5, line 63 to col. 6, line 17). In doing so, it prefers to utilize the local DRAM of the requesting host (and its processor) over I/O based access to a SCM, or the memory of another host (second DRAM).
Second, Applicant alleges that Taylor does not disclose memory media associated with a first processor as distinct from memory media associated with a second, adjacent processor. In response, Applicant’s second argument has been fully considered, but is not deemed persuasive. Taylor describes respective processing devices, which may be implemented using hosts, and each of which has a respective memory (Fig. 10 and associated text). It further discloses that each host may be associated with a respective one of the storage arrays (SCMs) (Fig. 8; col. 1, lines 13-31). Since these processing devices are connected to each other over a network, they can be considered “adjacent”.
Third, Applicant argues that Satayoma does not cure the alleged deficiencies of Taylor, and further argues that Satoyama does not disclose allocation based on latency. In response, Applicant’s third argument has been fully considered, but is not deemed persuasive. Satoyama has been cited both for the recited logical addressing (¶ 131) as well as classifying (allocating) storage based on response time (access latency) (¶ 14).
Fourth, Applicant argues that patentability of the amended claims does not turn on the scope of “adjacent”, and that the meaning of the term “adjacent does not affect analysis of the claims”. In response, Applicant’s fourth argument has been fully considered, and in response, Examiner agrees that the meaning of the term “adjacent” does not represent a patentable distinction, and thus does not affect analysis of the claims.
Fifth, Applicant argues that “there is no teaching, suggestion, or motivation to introduce such processor-locality-aware, access-latency-based selection, and the only roadmap for arriving at it is Applicant’s own specification”. In response, Applicant’s fifth argument has been fully considered, but is not deemed persuasive, as it is not Examiner’s position that such functionality is missing from Taylor. Examiner has provided an obviousness rationale for combining Taylor and Satoyama (see above).
Re claims 4-6, Applicant argues that Taylor and Satoyama do not disclose the particular determinations being performed “when the memory media associated with the first processor is insufficient”. As previously noted, the limitation “when the memory media associated with the first processor is insufficient” is a contingent limitation in a method claim, and thus is interpreted as being not required to occur (MPEP § 2111.04(II)). Nevertheless, Examiner has cited specific portions of Taylor and Satoyama as teaching these contingent limitations, for the reasons noted in claims 4-6 above.
Re claims 2, 4-10, 12, 14-17, and 19, Applicant argues that the claims are allowable by virtue of their dependence upon one of claims 1, 11, and 18; as this is the sole argument for allowability, Applicant is directed to Examiner’s rejections of claims 1, 11, and 18 above, respectively.
All arguments by the Applicant are believed to be covered in the body of the office action; thus, this action constitutes a complete response to the issues raised in the remarks dated 06/19/2026.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Per the instant office action, claims 1-2, 4-12, and 14-19 have received an action on the merits and are subject to a final rejection.
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/CRAIG S GOLDSCHMIDT/Primary Examiner, Art Unit 2132
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