DETAILED ACTION
Re Application No. 18/611674, this action responds to the RCE dated 03/03/2026.
At this point, claims 1, 11, and 18 have been amended. Claims 3, 13, and 20 have been cancelled. Claims 1-2, 4-12, and 14-19 are pending.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03/03/2026 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-7, 11-12, 14-15, and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Taylor et al (US 9189387 B1) in view of Satoyama et al (US 20120166748 A1).
Re claim 1, Taylor discloses the following:
A memory management method performed in a hybrid memory system comprising multiple processors and multiple different types of memory media (Figs 4-5 and 10, processing devices 1002-1:1002-K). The processing platform 1000 includes multiple processors (Fig. 10, processing devices 1002-1:1002-K) and multiple types of memory (Figs 4-5);
the multiple processors comprising a first processor associated with a dynamic random access memory (DRAM) and a storage-class-memory (SCM), the method being performed by the first processor and comprising (col. 5, lines 52-62; col. 11, lines 37-59). The storage system contains a DRAM tier as well as a SCM tier (col. 5, lines 52-62). The processors of the processing platform collectively execute instructions implementing the method (col. 11, lines 37-59);
obtaining a memory allocation request, wherein the memory allocation request is generated for an application process running on the first processor (claim 8; col. 5, lines 19-31). The application program requests storage resources (memory allocation request), which are dynamically allocated (claim 8). The memory is implemented as a virtual (logical) address space, and is accessed using a virtual (logical) address (col. 5, lines 19-31).
in response to the memory allocation request, determining a memory resource from the DRAM and SCM based on an allocation policy, the allocation policy indicating the memory resource be determined based on physical attributes of the DRAM and SCM, one of the physical attributes being a memory capacity, an access latency, a cost, or a service life; and (col. 1, lines 13-41; col. 4, line 46 to col. 5, line 18). Memory is allocated to storage tiers based on requirements such as bandwidth/throughput (access latency) and capacity requirements, relative to performance characteristics of the tiers;
allocating the memory resource to […] based on the allocation policy (col. 1, lines 13-41; col. 4, line 46 to col. 5, line 18). Memory is allocated to one of the tiers based on the allocation policy.
Taylor discloses allocating memory resources; furthermore, it discloses that memory is allocated in a virtual address space (Fig. 3); however, it does not explicitly use the word “logical address”. Accordingly, in the interest of furthering compact prosecution, Examiner has provided Satoyama.
Satoyama discloses that the memory allocation request comprises a logical address […] allocating the memory resource to the logical address (¶ 131). The I/O command, which may cause allocation of a memory resource, is associated with a logical block address.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to integrate the logical addressing of Satoyama into the memory allocation of Taylor, because it would be applying a known technique to improve a similar device in the same way. Taylor disclose memory resource allocation. Satoyama also discloses memory resource allocation, which has been improved in a similar way to the claimed invention, to utilize logical addressing. It would have been obvious to use the logical addressing of Satoyama in the memory allocation of Taylor, because it would yield the predictable improvement of allowing resources to be flexibly mapped between logical addresses and underlying physical resources.
Re claim 2, Taylor and Satoyama disclose the method of claim 1, and Taylor further discloses that the step of determining the to-be-allocated memory resource comprises: determining the memory resource from the DRAM and SCM based on a memory medium type and the physical attributes of the DRAM and SCM (col. 1, lines 13-41; col. 4, line 46 to col. 5, line 18). The storage tiers comprise DRAM and SCM with different physical attributes.
Re claim 4, Taylor and Satoyama disclose the method of claim 2, and Taylor further discloses the following:
the step of determining the memory resource from the DRAM and SCM comprises: determining the DRAM as the memory resource; and (col. 1, lines 13-41; col. 4, line 46 to col. 5, line 18). See claim 1 above. DRAM is one of the resources in the tiers that may be selected.
determining third memory media associated with a second processor adjacent to the first processor (Fig. 10; col. 4, lines 20-31). There are a plurality of processors on the storage system; Applicant has not explicitly defined what it means for a processor to be “adjacent”; accordingly, Examiner interprets the plurality of processors to be adjacent to one another (Fig. 10; col. 4, lines 20-31). There are at least 3 tiers, a top tier, a bottom tier, and a middle tier.
Satoyama further discloses that when a remaining memory resource of the [memory] does not satisfy a memory resource requirement of the memory allocation request, determining third memory media […] as the memory resource (¶ 335). It is noted that this is a conditional limitation in a method claim; as such, it is interpreted under Ex Parte Schulhauser (No. 2013-007847 (P.T.A.B. April 29, 2016), and is considered to be optional, as the condition need not actually occur. Nonetheless, Satoyama discloses that when there is insufficient space (remaining memory resource does not satisfy a memory resource requirement), space is instead allocated on another tier (third memory media).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to integrate the logical addressing of Satoyama into the memory allocation of Taylor, because it would be applying a known technique to improve a similar device in the same way. Taylor disclose memory resource allocation. Satoyama also discloses memory resource allocation, which has been improved in a similar way to the claimed invention, to allocate to a different tier if one tier is full. It would have been obvious to modify the memory allocation of Taylor to utilize a different tier if one tier is full, as in Satoyama, because it would yield the predictable improvement preventing one resource from being overused.
Re claim 5, Taylor and Satoyama disclose the method of claim 2, and Taylor further discloses that the step of determining the memory resource from the DRAM and SCM comprises: […] determining the memory resource from the SCM (col. 1, lines 13-41; col. 4, line 46 to col. 5, line 18). This limitation is a conditional limitation, and is accordingly interpreted as being optional under Ex Parte Schulhauser, for the reasons noted in claim 4 above. Nonetheless, Taylor discloses selecting from the available tiers, one of which is an SCM.
Satoyama discloses when a remaining storage space of the [first memory] associated with the multiple processors is less than a preset memory allocation granularity, determining the memory resource from [second memory] (¶ 335). It is noted that this is a conditional limitation in a method claim; as such, it is interpreted under Ex Parte Schulhauser (No. 2013-007847 (P.T.A.B. April 29, 2016), and is considered to be optional, as the condition need not actually occur. Nonetheless, Satoyama discloses that when there is insufficient space (remaining storage space is less than a preset memory allocation granularity), space is instead allocated on another tier (second memory).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to combine Taylor and Satoyama, for the reasons noted in claim 4 above.
Re claim 6, Taylor and Satoyama disclose the method of claim 5, and Taylor further discloses that the step of determining the memory resource from the SCM comprises: determining the SCM as the memory resource; and […] determining a second SCM associated with a second processor adjacent to the first processor as the memory resource (Fig. 10; col. 4, lines 20-31). There are a plurality of processors on the storage system; Applicant has not explicitly defined what it means for a processor to be “adjacent”; accordingly, Examiner interprets the plurality of processors to be adjacent to one another (Fig. 10; col. 4, lines 20-31). There are at least 3 tiers, a top tier, a bottom tier, and a middle tier.
Satoyama discloses when a remaining memory resource of the [second memory] associated with the first processor does not satisfy the memory resource requirement of the memory allocation request, determining a [second memory] associated with a second processor (¶ 335). It is noted that this is a conditional limitation in a method claim; as such, it is interpreted under Ex Parte Schulhauser (No. 2013-007847 (P.T.A.B. April 29, 2016), and is considered to be optional, as the condition need not actually occur. Nonetheless, Satoyama discloses that when there is insufficient space (remaining memory resource of the memory allocation request), space is instead allocated on another tier (second memory media).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to combine Taylor and Satoyama, for the reasons noted in claim 4 above.
Re claim 7, Taylor and Satoyama disclose the method of claim 1 above, and Taylor further discloses that the SCM comprises: a phase-change memory (PCM), a magnetoresistive random access memory (MRAM), a resistive random access memory (RRAM), a ferroelectric random access memory (FRAM), a fast NAND, or a nano-ranodm access memory (NRAM) (col. 4, lines 20-31). The SCM tier may include a NAND. It is noted that Applicant has not provided a specific definition of what qualifies as “fast” NAND; accordingly, Examiner interprets the NAND of Taylor to be “fast” in that it is faster than slow forms of persistent storage such as hard drives and tape storage.
Re claims 11-12 and 14-15, respectively, Taylor and Satoyama disclose the methods of claims 1-2, 5, and 7 above, respectively; accordingly, they also disclose apparatuses implementing those methods, as in claims 11-12 and 14-15, respectively (See Taylor, abstract).
Re claims 18-19, respectively, Taylor and Satoyama disclose the methods of claims 1-2 above, respectively; accordingly, they also disclose computer systems implementing those methods, as in claims 18-19, respectively (See Taylor, claim 19). Furthermore, Taylor discloses that each processor of the multiple processors is associated with at least two different types of memory media (Fig. 10; col. 4, lines 20-31).
Claims 8-9 and 16-17 are rejected under 35 U.S.C. 103 as unpatentable over Taylor in view of Satoyama, further in view of Johnson (US 2010/0306451 AA1).
Re claim 8, Taylor and Satoyama disclose the method of claim 1, but do not specifically disclose allocating resources based on granularity larger than a page.
Johnson discloses that the step of allocating the memory resource to the logical address based on the allocation policy comprises: allocating the memory resource corresponding to the logical address based on the preset memory allocation granularity, wherein the preset memory allocation granularity is greater than a page size of a memory medium (¶ 22 and 29). The memory resources can be allocated in units of blocks (¶ 29), which are larger than pages (¶ 22).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the memory allocation of Taylor (combined with Satoyama) to allocate memory in block units, as in Johnson, because it would be applying a known technique to improve a similar method in the same way. Taylor (combined with Satoyama) discloses allocating memory. Johnson also discloses allocating memory, and has been improved in a similar way to the claimed invention, to allocate memory in a granularity larger than a page (such as a block). It would have been obvious to modify the granularity of Taylor (combined with Satoyama) to be larger than a page, because it would yield the predictable improvement of allowing data to be allocated and deallocated (i.e. erased) at the same data granularity, as flash memory can only be erased at the block level.
Re claim 9, Taylor and Satoyama disclose the method of claim 1, but do not specifically disclose releasing memory resources.
Johnson discloses releasing the memory resource at the preset memory allocation granularity in response to a release instruction instructing to release the memory resource (¶ 28-29). The memory can be deleted (released) at the block (memory allocation granularity) level based on a delete request (release instruction).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to combine Taylor, Satoyama, and Johnson, for the reasons noted in claim 8 above.
Re claims 16-17, respectively, Taylor, Satoyama, and Johnson disclose the methods of claims 8-9, respectively; accordingly, they also disclose apparatuses implementing those methods, as in claims 16-17, respectively (See Taylor, abstract).
Claim 10 is rejected under 35 U.S.C. 103 as unpatentable over Taylor in view of Satoyama, further in view of Lepak (US 2022/0317925 A1).
Re claim 10, Taylor and Satoyama disclose the method of claim 1, and Taylor further discloses that the first processor is connected to the DRAM and SCM through interfaces supporting memory semantics (Fig. 10). The processors are connected to the memory types over interfaces, which support memory semantics, as they are connected to memory.
Taylor and Satoyama do not disclose the specific interfaces listed in the claim.
Lepak discloses that the first processor is connected to the [memories] through interfaces supporting memory semantics, and the interfaces comprise an interface supporting memory semantics, and the interfaces comprise an interface supporting a compute express link (CXL), a cache coherent interconnect for accelerators (CCIX) protocol, or a unified bus (UB) (¶ 16). The processors are connected to various memory tiers by interfaces such as CXL.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to utilize a CSX interface such as the one of Lepak in the memory interfaces of Taylor (combined with Satoyama), because Lepak suggests that connecting memory devices over CXL would yield the improvement of allowing memory devices to be attached using a differential serializer/deserialize (SerDes) link (¶ 14).
ACKNOWLEDGEMENT OF ISSUES RAISED BY THE APPLICANT
Response to Amendment
Applicant’s arguments with respect to claims 1-2, 4-12, and 14-19 filed 02/02/2026 have been fully considered, but are either not deemed persuasive, or are rendered moot in view of new grounds for rejection.
As required by M.P.E.P. § 707.07(f), a response to these arguments appears below.
ARGUMENTS CONCERNING PRIOR ART REJECTIONS
Re claims 1, 11, and 18, Applicant argues that Taylor and Satoyama do not disclose the claimed invention, for 2 reasons.
First, Applicant argues “A text search performed on Taylor for ‘policy’ or ‘polic’ produces seventeen (17) results” and “A text search performed on Taylor for ‘allocat’ produces seven (7) results”. In response, Applicant’s first argument has been fully considered, but is not deemed persuasive, for 2 reasons. First, as conceded by Applicant, the words “policy” and “allocate” do in fact appear in Taylor. Second, even assuming, arguendo, that this were not the case, Examiner is not limited to interpretations that are word-for-word identical to the language used by Applicant. For example, something may be a policy if there is some parameter which dictates how something is performed, such as selecting a tier based on capacity, even if this does not use the word “policy”.
Second, Applicant alleges that a variety of limitations are not taught by the combination of Taylor and Satoyama. In response, Applicant’s second argument has been fully considered, but is not deemed persuasive. Applicant’s arguments are mere bare recitations of claim limitations that are allegedly missing, and do not address the substance of either Examiner’s rejections or arguments in the final rejection dated 10/02/2025. Accordingly, Applicant is directed to Examiner’s rejection of claims 1, 11, and 18 above, as well as Examiner’s arguments from the previous final rejection.
Re claims 2, 4-10, 12, 14-17, and 19, Applicant argues that the claims are allowable by virtue of their dependence upon one of claims 1, 11, and 18; as this is the sole argument for allowability, Applicant is directed to Examiner’s rejections of claims 1, 11, and 18 above, respectively.
All arguments by the Applicant are believed to be covered in the body of the office action; thus, this action constitutes a complete response to the issues raised in the remarks dated 02/02/2026.
Conclusion
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/CRAIG S GOLDSCHMIDT/Primary Examiner, Art Unit 2132