DETAILED ACTION
This action is responsive to the communication filed on 12/5/2025. Claims 1-20 are pending and have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-6 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
With respect to claim 1, claim 1 recites a first super block corresponding to a first write request having a first type and a second super block corresponding to a second write request having a second type.
The claim as amended recites that, when the second write request is received from the host before the second super block is reallocated after having been deallocated, the write data corresponding to the second write request is to be stored in the first super block allocated to the first write request, without allocating any other super block.
The specification, however, does not appear to positively recite the requirement of abstaining from allocating any other super block when performing the operation of storing the write data for the second write request to the first super block. For example, while the pertinent paragraphs of the specification (specification: para. 7, 39-40, 56-58, 74, 86) appear to describe storing, in a super block, write data intended for a different super block responsive to the different super block not having been allocated, the specification, however, does not specifically recite a requirement for the storage process to include abstaining from allocating any other super block.
Claims 2-6 are rejected for being dependent on a rejected claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Byun (US 20210141722 A1) in view of Lee (US 20210011842 A1) in view of Kanno et al. (US 20230259453 A1) in view of Jia et al. (US 20170185318 A1).
As per claim 1,
A storage device comprising: a memory device including a plurality of super blocks, each including a plurality of memory blocks; and a controller configured to control the memory device in response to each request among a plurality of requests from a host, wherein the controller is further configured to: allocate a first super block among the plurality of super blocks to a first write request among the plurality of requests from the host, and allocate a second super block among the plurality of super blocks to a second write request among the plurality of requests from the host, the second super block being different from the first super block, the first write request being a request of a first type, the second write request being a request of a second type different from the first type, control the memory device to store in the first super block write data corresponding to the first write request, [Byun teaches a system comprising a host, memory controller, and memory device (para. 37-38, 48-49) where write data are stored onto a plurality of turbo write blocks or a plurality of normal write blocks based on write request indicating turbo write mode being set (first write request type) or reset (second write request type) (para. 67-69; claims 1, 3), where the turbo write blocks may comprise SLC blocks and normal write blocks may comprise QLC blocks (para. 115; fig. 5 and associated paragraphs)]
Where Byun does not explicitly recite the plurality of turbo write blocks or normal write blocks to comprise superblocks, Lee teaches a system comprising host, controller, and memory device (para. 24) where turbo write requests (first write request type) are directed to a superblock allocated as SLC memory blocks (first superblock) while normal write requests (second write request type) are directed to a superblock allocated as a multi-level memory block, such as a QLC block (second superblock) (para. 39-42, 30; fig. 1 and associated paragraph)]
Byun and Lee are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Byun and Lee, to modify the disclosures by Byun to include disclosures by Lee since they both teach data storage, wherein Lee is directed towards utilizing superblocks for exploiting spatial and temporal locality (para. 32). Therefore, it would be applying a known technique (allocating superblocks comprising SLC or multilevel blocks for respectively storing write data according to turbo and normal writes) to a known device (memory system directing write requests in turbo mode to a plurality of SLC blocks and directing writes not in turbo mode to a plurality of QLC blocks) ready for improvement to yield predictable results (memory system allocating superblock comprising SLC blocks for turbo writes and superblock comprising multi-level blocks for normal writes in order to provide for improved accommodation special/temporal locality in write data and greater flexibility in the storage scheme used in storing normal writes). MPEP 2143
Byun in view of Lee does not explicitly disclose, but Kanno discloses:
deallocate at least one of the first super block and the second super block, and when the second write request is received from the host before the second super block is reallocated after the deallocation of the second super block, control the memory device to store in the first super block allocated to the first write request, without allocating any other superblock, write data corresponding to the second write request. [Where Byun in view of Lee as shown above teaches SLC (first superblock) and multi-level superblocks (second superblock) corresponding to turbo and normal writes, Kanno discloses a memory device comprising SLC buffer and QLC superblocks, where, write data intended for a QLC superblock may instead be stored temporarily on the SLC buffer responsive to the QLC superblock being inactivated (deallocated) in order to rapidly release writer buffer space, where Kanno does not recite a requirement for opening other superblocks in storing the data onto the SLC buffer, and where the data is later moved from the SLC buffer to the QLC superblock responsive to the QLC superblock being reopened through, for example, a subsequent write request for the QLC superblock (para. 64, 87-92, 125-131, 232-233)]
Byun, Lee, and Kanno are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Byun in view of Lee and Kanno, to modify the disclosures by Byun in view of Lee to include disclosures by Kanno since they both teach data storage, wherein Kanno is directed towards more efficient usage of storage region (para. 6, 90). Therefore, it would be applying a known technique (using an SLC storage region to store data intended for a QLC superblock responsive to the QLC superblock being inactivated) to a known device (memory system directing write requests in turbo mode to a SLC superblock and directing writes not in turbo mode to a multilevel superblock) ready for improvement to yield predictable results (memory system allocating superblock comprising SLC blocks for turbo writes and superblock comprising multi-level blocks for normal writes, where data intended for a the multi-level superblock may be temporarily stored into the SLC superblock responsive to the multi-level superblock being inactivated in order to provide more efficient clearing of write buffer space by temporarily unloading the data into a region having faster write speed). MPEP 2143
Byun in view of Lee in view of Kanno does not explicitly disclose, but Jia discloses:
when the second write request is received from the host before the second super block is reallocated after the deallocation of the second super block [Byun in view of Lee in view of Kanno as shown above teaches temporarily storing data intended for a multi-level superblock onto an SLC superblock when the multi-level superblock is inactivated in order to rapidly release writer buffer space, and it and further teaches reopening the multi-level superblock and writing the data temporarily stored in the SLC superblock onto the multi-level superblock responsive to a subsequent write request directed to the multilevel superblock (see the rejection above); however, it does not explicitly disclose data for a write request, received subsequent to the multi-level superblock being inactivated, being written to the SLC superblock; however, Jia teaches, responsive to a write request being received and the block for the storage block being unavailable, storing the write data into a virtual block, where, once the intended block becomes available again, the data is copied from the virtual block to the storage block (para. 67, 41, 45)]
Byun, Lee, Kanno, and Jia are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Byun in view of Lee in view of Kanno and Jia, to modify the disclosures by Byun in view of Lee in view of Kanno to include disclosures by Jia since they both teach data storage, wherein Jia is directed towards optimizing data access and write operation performance in association with avoiding chained dependency of write commands in association with writing to a busy location (para 5, 41, 45). Therefore, it would be applying a known technique (responsive to receiving a write request and determining the target storage block is unavailable, temporarily storing write data into a virtual block until the target storage block becomes available) to a known device (memory system allocating superblock comprising SLC blocks for turbo writes and superblock comprising multi-level blocks for normal writes, where data intended for a the multi-level superblock may be temporarily stored into the SLC superblock responsive to the multi-level superblock being inactivated to provide for rapid release of write buffer space; reopening the multi-level superblock responsive to a subsequent write request) ready for improvement to yield predictable results (memory system allocating superblock comprising SLC blocks for turbo writes and superblock comprising multi-level blocks for normal writes, where, responsive to receiving a write request for the multi-level superblock and determining the multi-level superblock is inactivated, temporarily storing data intended for a the multi-level superblock in the SLC superblock while reopening the multi-level superblock in order to provide for improved write performance by processing the write request to the SLC superblock over waiting for the reopening of the multilevel superblock to be completed). MPEP 2143
As per claim 3, Byun in view of Lee in view of Kanno in view of Jia teaches claim 1 as shown above and further teaches:
The storage device according to claim 1, wherein the controller is further configured to reallocate the second super block in response to the second write request. [Byun in view of Lee in view of Kanno in view of Jia as shown above teaches a write request to an inactivated multilevel superblock reopening the superblock (see claim 1 above; Kanno: 131)]
Byun, Lee, and Kanno are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Byun in view of Lee and Kanno, to modify the disclosures by Byun in view of Lee to include disclosures by Kanno since they both teach data storage, wherein Kanno is directed towards more efficient usage of storage region (para. 6, 90). Therefore, it would be applying a known technique (using an SLC storage region to store data intended for a QLC superblock responsive to the QLC superblock being inactivated) to a known device (memory system directing write requests in turbo mode to a SLC superblock and directing writes not in turbo mode to a multilevel superblock) ready for improvement to yield predictable results (memory system allocating superblock comprising SLC blocks for turbo writes and superblock comprising multi-level blocks for normal writes, where data intended for a the multi-level superblock may be temporarily stored into the SLC superblock responsive to the multi-level superblock being inactivated in order to provide more efficient clearing of write buffer space by temporarily unloading the data into a region having faster write speed). MPEP 2143
Byun, Lee, Kanno, and Jia are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Byun in view of Lee in view of Kanno and Jia, to modify the disclosures by Byun in view of Lee in view of Kanno to include disclosures by Jia since they both teach data storage, wherein Jia is directed towards optimizing data access and write operation performance in association with avoiding chained dependency of write commands in association with writing to a busy location (para 5, 41, 45). Therefore, it would be applying a known technique (responsive to receiving a write request and determining the target storage block is unavailable, temporarily storing write data into a virtual block until the target storage block becomes available) to a known device (memory system allocating superblock comprising SLC blocks for turbo writes and superblock comprising multi-level blocks for normal writes, where data intended for a the multi-level superblock may be temporarily stored into the SLC superblock responsive to the multi-level superblock being inactivated to provide for rapid release of write buffer space; reopening the multi-level superblock responsive to a subsequent write request) ready for improvement to yield predictable results (memory system allocating superblock comprising SLC blocks for turbo writes and superblock comprising multi-level blocks for normal writes, where, responsive to receiving a write request for the multi-level superblock and determining the multi-level superblock is inactivated, temporarily storing data intended for a the multi-level superblock in the SLC superblock while reopening the multi-level superblock in order to provide for improved write performance by processing the write request to the SLC superblock over waiting for the reopening of the multilevel superblock to be completed). MPEP 2143
As per claim 4, Byun in view of Lee in view of Kanno in view of Jia teaches claim 1 as shown above and further teaches:
The storage device according to claim 1, wherein the controller is further configured to, when the second write request is received from the host after the second super block is reallocated, control the memory device to store in the second super block the write data corresponding to the second write request. [Where Byun in view of Kanno in view of Jia as shown above shows multilevel superblock being inactivated and reopened (claim 4), and Kanno discloses that a write for a QLC superblock in an open state is written to the QLC superblock and not to the SLC buffer (para. 147)]
Byun, Lee, and Kanno are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Byun in view of Lee and Kanno, to modify the disclosures by Byun in view of Lee to include disclosures by Kanno since they both teach data storage, wherein Kanno is directed towards more efficient usage of storage region (para. 6, 90). Therefore, it would be applying a known technique (using an SLC storage region to store data intended for a QLC superblock responsive to the QLC superblock being inactivated) to a known device (memory system directing write requests in turbo mode to a SLC superblock and directing writes not in turbo mode to a multilevel superblock) ready for improvement to yield predictable results (memory system allocating superblock comprising SLC blocks for turbo writes and superblock comprising multi-level blocks for normal writes, where data intended for a the multi-level superblock may be temporarily stored into the SLC superblock responsive to the multi-level superblock being inactivated in order to provide more efficient clearing of write buffer space by temporarily unloading the data into a region having faster write speed). MPEP 2143
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Byun (US 20210141722 A1) in view of Lee (US 20210011842 A1) in view of Kanno et al. (US 20230259453 A1) in view of Jia et al. (US 20170185318 A1) in view of Doni et al. (US 20230152995 A1).
As per claim 2, Byun in view of Lee in view of Kanno in view of Jia does not explicitly disclose, but Doni discloses:
The storage device according to claim 1, wherein the first write request includes one of a sequential write request and a random write request. [Where Byun in view of Lee in view of Kanno in view of Jia discloses SLC superblock for turbo writes and MLC superblock for normal writes as shown above (see claim 1), it does not explicitly state the writes to the SLC superblock comprising a sequential or random write request; Doni teaches selecting metablocks such as SLC or TLC metablock for storing host data, where a host write request may comprise either a sequential pattern or a random pattern (para. 30)]
Byun, Lee, Kanno, Jia, and Doni are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Byun in view of Lee in view of Kanno in view of Jia and Doni, to modify the disclosures by Byun in view of Lee in view of Kanno in view of Jia to include disclosures by Doni since they both teach data storage, wherein Doni is directed towards improvements in memory devices (para. 1). Therefore, it would be applying a known technique (servicing host writes to SLC or TLC metablocks, where the host writes may comprise random or sequential write pattern) to a known device (memory system storing turbo host writes to SLC superblock and normal host writes to multilevel superblock) ready for improvement to yield predictable results (memory system storing turbo host writes to SLC superblock and normal host writes to multilevel superblock, where the host writes may comprise one of random or sequential write pattern; such scheme accepting both types of write patterns for servicing would provide for more flexible data storage). MPEP 2143
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Byun (US 20210141722 A1) in view of Lee (US 20210011842 A1) in view of Kanno et al. (US 20230259453 A1) in view of Jia et al. (US 20170185318 A1) in view of Avudaiyappan et al. (US 20110153928 A1).
As per claim 5, Byun in view of Lee in view of Kanno in view of Jia teaches claim 1 as shown above. It does not explicitly disclose, but Avudaiyappan discloses:
The storage device according to claim 1, wherein the controller is further configured to count, as a first count, a number of times the first write request is received from the host and count, as a second count, a number of times the second write request is received from the host. [Where Byun in view of Lee in view of Kanno in view of Jia as shown above teaches storing data for an inactive multilevel superblock onto an SLC superblock while the multilevel superblock is being reopened pursuant to write request as shown above (see claim 1 above), it does not explicitly disclose counting the number of times write requests are received; however, Avudaiyappan discloses an access count maintained for each hardware memory segment, the access count being incremented for each memory access to the hardware memory segment (para. 25, 34, 22), where, based on the number of memory accesses in a time period being below a threshold value, the corresponding memory segment may be placed into a powerdown mode (para. 57, 39-41, 43-49; figs. 2-3 and associated paragraphs; see para. 56 indicating the memory segment in powerdown mode may still be written to upon the segment exiting the powerdown mode responsive to an access request)]
Byun, Lee, Kanno, Jia, and Avudaiyappan are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Byun in view of Lee in view of Kanno in view of Jia and Avudaiyappan, to modify the disclosures by Byun in view of Lee in view of Kanno in view of Jia to include disclosures by Avudaiyappan since they both teach data storage, wherein Avudaiyappan is directed towards improved memory power conservation (para. 3-4). Therefore, it would be applying a known technique (placing memory segments into powerdown mode responsive to the access counts of the respective segments being under a threshold) to a known device (memory system writing data for a multilevel superblock to a SLC superblock responsive to the multilevel superblock being closed) ready for improvement to yield predictable results (memory system writing data for a multilevel superblock to a SLC superblock responsive to the multilevel superblock being inactivated, wherein access count for each superblock is maintained for a time period, and the multilevel superblock may be inactivated responsive to the number of access requests to the multilevel superblock being under a threshold; doing so would provide for improved power conservation). MPEP 2143
As per claim 6, Byun in view of Lee in view of Kanno in view of Jia in view of Avudaiyappan teaches claim 5 as shown above and further discloses:
The storage device according to claim 5, wherein the controller is further configured to determine at least one of the first super block and the second super block, which is not used for a particular period, based on the first count and the second count, and to deallocate the determined super block. [As shown above (see claim 5), Avudaiyappan discloses an access count for each hardware memory segment, the access count being incremented for each memory access to the hardware memory segment (para. 25, 34, 22), where, based on the number of memory accesses in a time period being below a threshold value, the corresponding memory segment may be placed into a powerdown mode (para. 57, 39-41, 43-49; figs. 2-3 and associated paragraphs; see para. 56 indicating the memory segment in powerdown mode may still be written to upon the segment exiting the powerdown mode responsive to an access request)]
Byun, Lee, Kanno, Jia, and Avudaiyappan are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Byun in view of Lee in view of Kanno in view of Jia and Avudaiyappan, to modify the disclosures by Byun in view of Lee in view of Kanno in view of Jia to include disclosures by Avudaiyappan since they both teach data storage, wherein Avudaiyappan is directed towards improved memory power conservation (para. 3-4). Therefore, it would be applying a known technique (placing memory segments into powerdown mode responsive to the access counts of the respective segments being under a threshold) to a known device (memory system writing data for a multilevel superblock to a SLC superblock responsive to the multilevel superblock being closed) ready for improvement to yield predictable results (memory system writing data for a multilevel superblock to a SLC superblock responsive to the multilevel superblock being inactivated, wherein access count for each superblock is maintained for a time period in associating with placing a superblock into powerdown mode, and the multilevel superblock may be inactivated responsive to the number of access requests to the multilevel superblock being under a threshold; doing so would provide for improved power conservation). MPEP 2143
Allowable Subject Matter
Claims 7-20 are allowed.
With respect to claim 7, “… plurality of requests from a host, wherein the controller is further configured to: allocate a first super block among the plurality of super blocks in response to a first write request among the plurality of requests from the host, the first write request being a request of a first type, allocate a second super block among the plurality of super blocks in response to a second write request among the plurality of requests from the host, the second write request being a request of a second type different from the first type, count, as a first count, a number of times the first write request is received from the host and count, as a second count, a number of times the second write request is received from the host, and deallocate the first super block or the second super block based on the first count and the second count, wherein the controller is further configured to deallocate the second super block when the first count reaches a reference value and the second count is zero (0).” in conjunction with the other limitations of the claim, are not disclosed by the prior art of record.
The closest prior arts of record are Byun (US 20210141722 A1), Lee (US 20210011842 A1), Avudaiyappan et al. (US 20110153928 A1), Kanno et al. (US 20230259453 A1), Jia et al. (US 20170185318 A1). Ozturk (US 10860388 B1), Ji et al. (US 20190354311 A1), Lee (US 20130111114 A1, hereinafter Lee 2), Shrma et al. (US 12417053 B2), and Geukens et al. (US 20240134570 A1).
Byun teaches directing respective writes among turbo and normal writes to SLC or QLC blocks. Lee teaches SLC or multilevel superblock used for storing turbo and normal writes. Avudaiyappan teaches setting a memory segment to powerdown state responsive to a respective counter value. Kanno teaches temporarily storing data for QLC superblock on a SLC buffer. Jia teaches temporarily storing data for a block onto a virtual block. Ozturk teaches incrementing a write lock count for each write command directed to a die. Ji teaches initializing a plurality of counters for read accesses being initialized when any one of the counters reaches a threshold value. Lee teaches determining the size of data stored in a storage node according to number of times requests of sequential or random types were received. Sharma teaches determining how long each sequential write commands have been pending in a queue by counting the number of commands received after each sequential write commands were received. Geukens teaches receiving respective write commands for writing to a first page of a respective block of a plurality of blocks and pausing executing the commands until each of the respective blocks were written to.
However, the prior arts of record, neither individually nor in combination, teaches, in association with a plurality of superblocks in a memory and a plurality of requests from a host, allocating a first superblock among the plurality of superblocks in response to a first write request of a first type from the host, and allocating a second superblock among the plurality of superblocks in response to a second write request of a different, second type from the host, where a first and a second counts are maintained respectively for the number of times the respective first and second write requests are received from the host, where one of the first or the second superblock may be deallocated based on the first and the second count, with the second super block being deallocated when the first count for the first write request reaches a reference value and the second count for the second write request is zero.
Therefore, the prior arts of record, neither individually nor in combination disclose, in conjunction with the other limitations of the claim, the claim as a whole.
Claims 8-13 are allowed based at least on the virtues of their dependency from claim 7.
With respect to claim 14, “… allocating storage regions to write requests of different types among requests from a host; monitoring, as a first count, a number of times a write request of a first type among the write requests is received from the host, and, as a second count, a number of times a write request of a second type is received from the host, the second type being different from the first type; deallocating one of storage regions respectively corresponding to the write request of the first type and the write request of the second type, based on the first count and the second count; receiving, from the host, the write request of the first type; determining whether a deallocated storage region corresponds to the write request of the first type; and storing write data corresponding to the received write request of the first type in one of the storage regions respectively corresponding to the write request of the first type and the write request of the second type based on a result of the determination, wherein the deallocating comprises deallocating the storage region corresponding to the write request of the first type in response to a determination that the second count reaches a reference value and the first count is zero (0).” in conjunction with the other limitations of the claim, are not disclosed by the prior art of record.
The closest prior arts of record are Byun (US 20210141722 A1), Lee (US 20210011842 A1), Avudaiyappan et al. (US 20110153928 A1), Kanno et al. (US 20230259453 A1), Jia et al. (US 20170185318 A1). Ozturk (US 10860388 B1), Ji et al. (US 20190354311 A1), Lee (US 20130111114 A1, hereinafter Lee 2), Shrma et al. (US 12417053 B2), and Geukens et al. (US 20240134570 A1).
Byun teaches directing respective writes among turbo and normal writes to SLC or QLC blocks. Lee teaches SLC or multilevel superblock used for storing turbo and normal writes. Avudaiyappan teaches setting a memory segment to powerdown state responsive to a respective counter value. Kanno teaches temporarily storing data for QLC superblock on a SLC buffer. Jia teaches temporarily storing data for a block onto a virtual block. Ozturk teaches incrementing a write lock count for each write command directed to a die. Ji teaches initializing a plurality of counters for read accesses being initialized when any one of the counters reaches a threshold value. Lee teaches determining the size of data stored in a storage node according to number of times requests of sequential or random types were received. Sharma teaches determining how long each sequential write commands have been pending in a queue by counting the number of commands received after each sequential write commands were received. Geukens teaches receiving respective write commands for writing to a first page of a respective block of a plurality of blocks and pausing executing the commands until each of the respective blocks were written to.
However, the prior arts of record, neither individually nor in combination, teaches, in association with allocation of storage regions pertaining to write requests of different types among requests from a host, monitoring as a first count a number of times a write request of a first type is received from the host and monitoring as a second count a number of times a write request of a second, different type is received from the host, where one of the storage regions corresponding to the first type of write request or the second type of write request is deallocated based on the first and the second count, with the storage region corresponding to the first type of write request being deallocated in response to a determination that the second count reaches a reference value and the first count is zero, where, in response to receiving the write request of the first type from the host, determining whether the deallocated storage region corresponds to the storage region for the first type of write request and, based on the determination, storing the write data for the host-received write request in one of the storage region for the first type of write request or the storage region for the second type of write request.
Therefore, the prior arts of record, neither individually nor in combination disclose, in conjunction with the other limitations of the claim, the claim as a whole.
Claims 15-20 are allowed based at least on the virtues of their dependency from claim 14.
Response to Arguments
The claim objection(s) recited in the most recent previous office action is withdrawn in view of the amendments by the applicant.
Applicant’s arguments with respect to the rejection of claim 1 and claims depending therefrom under 35 USC 103 have been fully considered. With respect to the remarks stating that the combination of references relied upon fail to disclose storing data of a second write request in a first super block and fail to disclose doing so without allocating any other super block, the examiner respectfully disagrees.
In the rejection of claim 1 over Byun in view of Lee in view of Kanno in view of Jia as shown above, the combination of Byun and Lee were relied upon for disclosing respective SLC superblock (first super block) and multi-level superblock (second super block) corresponding to respective types of write requests (please see claim 1 above; Byun: para. 67-69, 115; Lee: para. 39-42), where Kanno was relied upon for a combination providing for storing data, intended for inactivated, multi-level superblock, to the SLC superblock (Kanno: 64, 87-92, 125-131, 232-233), and Jia was relied upon for the combination where the data for a write request received subsequent to the inactivation of multi-level superblock may be stored onto the SLC superblock (Jia: para. 67, 41, 45). In performing the operation of storing data to an alternate location, Kanno and Jia as cited above do not recite the operation to also require performing allocation of additional superblocks.
In response to applicant's arguments pertaining to the respective references, one cannot show nonobviousness by addressing the references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Relevant Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Rayney, III et al. (US 8458435 B1) teaches storing data on a limited number of threads, where each thread corresponds to an open superblock.
Jung et al. (US 20190324680 A1) teaches managing certain open superblocks as special superblocks and setting a limit to the number of special superblocks that may be maintained, where a write for a special superblock may be directed to a normal superblock if no more special superblocks may be allocated.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/E.Y.K./Examiner, Art Unit 2135
/JARED I RUTZ/Supervisory Patent Examiner, Art Unit 2135