Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-3, 5-12, 14-20 are presented for Examination.
DETAILED ACTION
Claim Objections
Claims 1, 10, 16 are objected to because of the following informalities:
Regarding Claims 1, 10, 16, the limitation “ each of the devices “ should be--“ each of the plurality of devices”--
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7, 15, 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claims 7, 15, 20 recites the limitation " the controller”, in line 4. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 5, 6, 10, 11, 14, 16, 17, 19 are rejected under 35 U.S.C. 103 as being unpatentable over Park et.al. (U.S Patent Application Publication 2016/0179164; hereinafter “Park”; ( Reference cited as prior art in previous office action)] in view of Lake (U.S Patent Application Publication 2021/0149472)
Regarding claims 1, 10, 16, Park discloses, an Information Handling System (IHS), comprising:
a heterogeneous computing platform comprising a plurality of devices [ “the power is sourced from a power supply 188 (such as a battery or an AC power source) and distributed by the PMIC 180 to the SoC 102 through a voltage regulator 189 and via a number of dedicated sets of power rails 190 (only one set being shown in FIG. 3). Notably, each of cores 0, 1, 2 and 3 of function block 1 (such as may be the case for a CPU 110 or GPU 182 (shown in FIG. 5 and discussed below) ..”, 0033; Fig.3]; and
an orchestrator comprising firmware that, upon execution by a processing core, causes the processing core to [0068; “managing peak dynamic power consumption to optimize user experience and QoS (as measured in terms of processing performance or throughput, for example), the startup logic 250 includes one or more executable instructions for selectively identifying, loading, and executing a select program for peak dynamic power management. A select program may be found in the program store 296 of the embedded file system 290 and is defined by a specific combination of a performance scaling algorithm 297 and a set of parameters 298. The select program, when executed by one or more of the core processors in the CPU 110, may operate in accordance with one or more signals provided by the monitor module 114 in combination with control signals provided by the one or more PDP module(s) 101 and DCVS module(s) 26..”, 0070; Fig.8; “dynamic power (“PDP”) management module(s) seek to monitor, analyze and manage a power supply in a PCD. A PDP module, perhaps in conjunction with a monitoring module, seeks to monitor and manage a peak dynamic current budget in view of real-time assessments of a power supply level, voltage level(s) and a leakage current level(s). ..”, 0023;” the PDP module 101 and/or monitor module 114 may include hardware and/or software interrupts handled by an interrupt service routine. That is, depending on the embodiment, a PDP module 101 and/or monitor module 114 may be implemented in hardware as a distinct system with control outputs, such as an interrupt controller circuit, or implemented in software, such as firmware integrated into a memory subsystem.”, 0036]
communicate with each of the plurality of devices to obtain a power consumption level for each of the devices[“the monitor module 114 monitors a signal from one or more temperature sensors 157A to track leakage power consumption levels of active components associated with the various rails. In addition to the temperature sensors 157A, monitor module 114 may also monitor sensors 157B (not shown) associated with the PMIC 180 to recognize parameters useful for determining an actual provided power supply level. The monitor module 114 may subsequently communicate with the PDP module 101 to relay the monitored data indicative of active leakage power consumption of functional blocks residing on the SoC 102 and actual power supply levels available from the PMIC 180…”, 0037] ; and
adjust a power limit value of the IHS according to a cumulative power consumption level of the devices[ “..the PDP module 101 may use the monitored data to determine an actual available power supply for allocation to dynamic power consumption by the various function blocks and then adjust a peak dynamic current threshold based on the determination. An adjusted peak dynamic current threshold may be used to trigger a dynamic control and voltage scaling (DCVS) module 26 to throttle the function blocks to optimal workload processing levels, as would be understood by one of ordinary skill in the art of dynamic control and voltage scaling of processing component..”, 0037; “FIG. 5 illustration includes three main components of the system 99—the PMIC 180, the PDP module 101 and a power domain (e.g. GPU 182). As described above, the PMIC 180 supplies power to the power domain which resides on the SoC 102. And, the PDP module 101 adjusts the peak current threshold for that power supply in order to optimize the amount of power allocated to the power domain for workload processing (i.e., to optimize the dynamic power budget)”, 0040;0044; Fig.5] However, Park does not disclose adjust the power limit value without any involvement by an Operating System (OS) configured in the IHS.
However, Park does not expressly disclose adjusting the power limit without any involvement by an Operating System (OS) configured in the IHS during a runtime of the OS. Specifically, Park discloses a PDP and / or a monitor module adjusting a power limit value of the IHS according to a cumulative power consumption level of the devices, but does not disclose the adjusting without the involvement of the OS during a runtime of the OS.
In the same field of endeavor (e.g. power management of integrated circuits based on latency reporting of end points such as the cores or processors to the power management controller ) Lake teaches , adjust the power limit value without any involvement by an Operating System (OS) configured in the IHS during a runtime of the OS [“the power management techniques described herein may be independent of and complementary to an operating system (OS)-based power management (OSPM) mechanism ..”, 0039; “a power control unit (PCU) 138, which may include hardware, software and/or firmware to perform power management operations with regard to processor 110. In an embodiment a PCU may be a dedicated microcontroller that runs dedicated embedded firmware and makes dynamic power management decisions based on various global inputs such as temperature, current, power, and workload types. PCU 138 may couple to a platform power management controller (PMC)”, 0034; “PCU 138 also provides control information to IVRs 125 via another digital interface to control the operating voltage generated (or to cause a corresponding IVR to be disabled in a low power mode) “, 0034; “ power management logic included in PCU 138 may be a dynamic current sharing control circuit that is configured to dynamically determine independent maximum current consumption values for each core 120 and/or additional processing circuits. As will be described further herein this control circuitry may provide a dynamically configurable maximum current consumption value to each of cores 120 to enable each core 120 to operate according to this constraint. As such, when PCU 138 identifies a condition that triggers a throttle event, a throttle signal may be sent to the cores 120. In turn, each core 120 may limit its operation to its dynamically identified maximum current consumption value. In this way, different cores may operate at asymmetric performance states, particularly when a throttle event is identified, such that a minimal impact to user-facing workloads occurs.”, 0037; “ a processing element, in one embodiment, refers to any hardware capable of being independently associated with code, such as a software thread, operating system, application ..”, 0049; (i.e the PCU component operates independently from the processor that is executing the operating system (‘OS’) to dynamically control the current limit of the cores and its operation to adjust / throttle the power of the system . Therefore, the PCU performs the adjustment without involving the OS and during the runtime of the OS) ].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Park with Lake. Lake’s teaching of a dedicated microcontroller that runs dedicated embedded firmware and makes dynamic power management decisions based on various global inputs will substantially improve Park’s system to provide fine-grained control of voltage and thus power and performance of each individual core. As such, each core can operate at an independent voltage and frequency, enabling great flexibility and affording wide opportunities for balancing power consumption with performance.
Regarding claims 2,11,17, Park discloses cause the processing core to adjust the power limit value by adjusting a clock speed of a processor configured in the IHS[ “A PDP module may also work with a dynamic control and voltage scaling (“DCVS”) system to modify a clock frequency or voltage level to one or more processing components such that an overall current demand is adjusted and the peak current level maintained within a dynamic current budget “ The operating frequency limiter 183 may adjust the maximum frequency and bin step up limits based on the estimated actual power supply level and indicate as much to the DCVS module 26. The DCVS module 26 may, in turn, modulate the frequency of the power domain. Moreover, in the event that the amount of workload of the power domain exceeds the dynamic power budget set by the PPD threshold controller 179, a trigger signal may be provided back to the DCVS module 26 to reduce voltage in addition to frequency. In doing so, the power domain may be able to operate at a lower voltage for a drastically reduced frequency.”, 0045; “..Using the remaining power budget, an optimum dynamic power budget threshold (“OT”) may be determined.”, 0047; “..the DCVS module 26 may modify frequency and/or voltage settings to the one or more function blocks based on the new OT power budget threshold..”, 0048].
Regarding claims 5,14,19, Park discloses cause the processing core to perform the acts of communicating with the devices and adjusting the power limit value in response to a trigger[0036; 0037; 0070].
Regarding claim 6, Lake wherein the trigger comprises at least one of a removable device connection or disconnection event, or a request from the Operating System (OS) [ 0039]
Claims 3,12,18 are rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Lake as applied to claims 1, 10, 16 further in view of Hsu (U.S Patent Application Publication 2012/0131363)
Regarding claims 3,12,18, Park discloses wherein the instructions further cause the processing core to adjust the power limit value [0037; 0040; 0070].
However, Park, Lake does not disclose adjusting a speed of a fan configured in the IHS.
In the same field of endeavor (e.g. controlling power consumption of a heat dissipating device), Hsu teaches adjusting a speed of a fan configured in the IHS [ “: judging whether the total power consumption of the host exceeds a threshold total power consumption; if the total power consumption of the host does not exceed the threshold total power consumption, adjusting the rotating speed of the fan according to the temperature inside the host; and if the total power consumption of the host exceeds the threshold total power consumption, lowering the rotating speed of the fan, so as to reduce the total power consumption of the host to the threshold total power consumption.”, 0014].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Park in view of Lake with Hsu. Hsu’s teaching of determining to control the rotating speed of the fan based on whether the total power consumption exceeding the threshold or not will substantially improve performance and control the power consumption of Park in view of Lake’s system more accurately, when the power supply may go out of order or be damaged (that is, the power supply fails to provide power for the main boards) [0006].
Claims 7, 8, 9, 15, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Park in view Lake as applied to claims 1, 10, 16 further in view of of Khatri et.al.(U.S Patent Application Publication 2017/0031431; hereinafter “Khatri”; (Reference cited as prior art in previous office action))
Regarding claims 7, 15, 20 Park teaches the limitations outlined in claims 7,15, 20.
However, Park, Lake does not expressly disclose wherein one of the devices comprises another memory coupled to another processor, the other memory having instructions stored thereon that, upon execution by the other processor, cause the other processor to: receive a directive from the controller; in response to the directive, obtain a power consumption level for the device; and send the obtained power consumption level to the controller.
In the same field of endeavor ( e.g. dynamically limits peak power consumption in processing nodes of an IHS), Khatri teaches,
wherein one of the devices comprises another memory coupled to another processor, the other memory having instructions stored thereon that, upon execution by the other processor, cause the other processor to: receive a directive from the controller; in response to the directive, obtain a power consumption level for the device; and send the obtained power consumption level to the controller. [ “As one aspect of power distribution within IHS 100, PMM 120 and micro-controller 122 can monitor (i) power consumption and workload data across the IHS 100 as well as (ii) the amount of available power provided by the PSUs 152, and PMM 120 can dynamically limit peak power consumption in the processing nodes 150A-D of the IHS based on power-usage and workload data. Micro-controller 122 can trigger changes in CPU operating frequency and power consumption at the individual processing nodes based on changes in the amount of available power, power consumption and workload data. In one embodiment, control of the power subsystem 125 can be provided by MC 110 instead of PMM 120. “, 0041; “each of the processing nodes 150A-D has a complex programmable logic device (CPLD) 152 and a board management controller (BMC) 154. CPLD 152 is coupled to PMM 120 via I2C bus 156. I2C bus 156 carries data and signals. BMC 154 is coupled to PMM 120 via an Ethernet cable 158. Ethernet cable 158 carries data and signals between PMM 120 and BMC 154. Specifically, according to at least one embodiment, PMM 120 provides certain control and/or management signals to the processing nodes 150A-D via I2C bus 156 and one or more select wires within Ethernet cable 158. In one embodiment, PMM 120 can send and receive data signals at a relatively fast rate via the dedicated I2C bus 156 or can send and receive data signals at a relatively slower rate via the Ethernet bus 158, depending on the desired data transfer rate.”, 0042; “FIGS. 3A, 3B and 3C illustrate further details of the contents of PMM memory 220, NC memory 164 and system memory 184. With specific reference to FIG. 3A, PMM memory 220 stores DPPLC firmware 222 which controls the operation of micro-controller 122 in controlling power management functions within IHS 100. PMM memory 220 can store node peak power limits or thresholds 230 and node average power limits or thresholds 240 for each of the processing nodes 150A-D. PMM memory 220 further contains the number of active PSUs 310, the output capacity of each PSU 312, and the total available system power 313 of the IHS, including a peak power output capacity 314 and a sustained output power capacity 316.”, 0056; “ PMM 120, executing DPPLC firmware 222, receives power-usage data 322 and workload data 330 from several node controllers 160. The received data 322/330 includes current node power consumption 324 and a current node workload 330 for each processing node 150A-D within the IHS. A total available system power 313 of the IR..”, 0061; ( i.e each of the nodes corresponds to a device ); “ The plurality of computing or processing nodes 150 are individually labeled as processing nodes A-D 150A-D. MC 110 includes a micro-controller 112 (also generally referred to as a processor), which is coupled via an internal bus 115 to memory 114, I/O interface controller 116, storage 118 and power management module (PMM) 120. Memory 114 can be flash or other form of memory.” 0039].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Park in view of Lake with Khatri. Khatri’s teaching of dynamically limits peak power consumption in processing nodes based on power-usage and workload data from several node controllers, will substantially improve performance of Park in view of Lake’s system by dynamically controlling the device peak power limit of a node based on the power usage and workload data of the respective nodes and the available total power.
Regarding Claim 8, Khatri teaches , wherein the one device comprises a device external to the IHS [.0039; Fig.1D]
Regarding claim 9, Khatri teaches the limitations outlined in cliams 7,8. However Khatri does not expressly teach wherein the at least one device comprises a docking station.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Khatri to implement a docking station as an external device since it has been held to be within the general skill of a worker in the art to select the component on the basis of its suitability for the intended use as a matter of design choice.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 10, 16 have been considered but are moot because the arguments do not apply to Park in view of Lake references being used in the current rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Berke et. al., U.S Patent Application Publication 2014/0067139, teaches dynamic power budget allocation when powering an information handling system.
Branover et. al., U.S Patent Application Publication 2013/9145180, teaches efficient management of operating modes within a system-on-a-chip (SOC) for optimal power and performance targets.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GAYATHRI SAMPATH whose telephone number is (571)272-5489. The examiner can normally be reached on Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jaweed Abbaszadeh can be reached on 5712701640. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/GAYATHRI SAMPATH/ Examiner, Art Unit 2176
/JAWEED A ABBASZADEH/ Supervisory Patent Examiner, Art Unit 2176