Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 06/02/2026 has been entered.
Claims 1-3, 5, 7-12, 14-23 are presented for Examination.
DETAILED ACTION
Claim Objections
Claims 1, 10, 16 are objected to because of the following informalities:
Regarding Claims 1, 10, 16, line 7, the limitation “ each of the devices “ should be--“ each of the plurality of devices”--
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 10, 11, 16, 17, 21-23, are rejected under 35 U.S.C. 103 as being unpatentable over Park et.al. (U.S Patent Application Publication 2016/0179164; hereinafter “Park”; ( Reference cited as prior art in previous office action)] in view of Shah et. al. (U.S Patent Application Publication 2024/0126354; hereinafter “Shah”)
Regarding claims 1, 10, 16, Park discloses, an Information Handling System (IHS), comprising:
a heterogeneous computing platform comprising a plurality of devices [ “the power is sourced from a power supply 188 (such as a battery or an AC power source) and distributed by the PMIC 180 to the SoC 102 through a voltage regulator 189 and via a number of dedicated sets of power rails 190 (only one set being shown in FIG. 3). Notably, each of cores 0, 1, 2 and 3 of function block 1 (such as may be the case for a CPU 110 or GPU 182 (shown in FIG. 5 and discussed below) ..”, 0033; Fig.3]; and
an orchestrator comprising firmware that, upon execution by a processing core, causes the processing core to [0068; “managing peak dynamic power consumption to optimize user experience and QoS (as measured in terms of processing performance or throughput, for example), the startup logic 250 includes one or more executable instructions for selectively identifying, loading, and executing a select program for peak dynamic power management. A select program may be found in the program store 296 of the embedded file system 290 and is defined by a specific combination of a performance scaling algorithm 297 and a set of parameters 298. The select program, when executed by one or more of the core processors in the CPU 110, may operate in accordance with one or more signals provided by the monitor module 114 in combination with control signals provided by the one or more PDP module(s) 101 and DCVS module(s) 26..”, 0070; Fig.8; “dynamic power (“PDP”) management module(s) seek to monitor, analyze and manage a power supply in a PCD. A PDP module, perhaps in conjunction with a monitoring module, seeks to monitor and manage a peak dynamic current budget in view of real-time assessments of a power supply level, voltage level(s) and a leakage current level(s). ..”, 0023;” the PDP module 101 and/or monitor module 114 may include hardware and/or software interrupts handled by an interrupt service routine. That is, depending on the embodiment, a PDP module 101 and/or monitor module 114 may be implemented in hardware as a distinct system with control outputs, such as an interrupt controller circuit, or implemented in software, such as firmware integrated into a memory subsystem.”, 0036];
communicate with each of the plurality of devices to obtain a power consumption level for each of the devices[“the monitor module 114 monitors a signal from one or more temperature sensors 157A to track leakage power consumption levels of active components associated with the various rails. In addition to the temperature sensors 157A, monitor module 114 may also monitor sensors 157B (not shown) associated with the PMIC 180 to recognize parameters useful for determining an actual provided power supply level. The monitor module 114 may subsequently communicate with the PDP module 101 to relay the monitored data indicative of active leakage power consumption of functional blocks residing on the SoC 102 and actual power supply levels available from the PMIC 180…”, 0037] ; and
adjust a power limit value of the IHS according to a cumulative power consumption level of the devices[ “..the PDP module 101 may use the monitored data to determine an actual available power supply for allocation to dynamic power consumption by the various function blocks and then adjust a peak dynamic current threshold based on the determination. An adjusted peak dynamic current threshold may be used to trigger a dynamic control and voltage scaling (DCVS) module 26 to throttle the function blocks to optimal workload processing levels, as would be understood by one of ordinary skill in the art of dynamic control and voltage scaling of processing component..”, 0037; “FIG. 5 illustration includes three main components of the system 99—the PMIC 180, the PDP module 101 and a power domain (e.g. GPU 182). As described above, the PMIC 180 supplies power to the power domain which resides on the SoC 102. And, the PDP module 101 adjusts the peak current threshold for that power supply in order to optimize the amount of power allocated to the power domain for workload processing (i.e., to optimize the dynamic power budget)”, 0040;0044; Fig.5] However, Park does not disclose adjust the power limit value without any involvement by an Operating System (OS) configured in the IHS.
However, Park does not expressly disclose causes the processing core to, in response to a trigger comprising at least one of a removable device connection or disconnection event; adjusting the power limit without any involvement by an Operating System (OS) configured in the IHS during a runtime of the OS.
Specifically, Park discloses a PDP and / or a monitor module adjusting a power limit value of the IHS according to a cumulative power consumption level of the devices, but does not disclose causes the processing core to, in response to a trigger comprising at least one of a removable device connection or disconnection event adjusting the power limit without the involvement of the OS during a runtime of the OS.
In the same field of endeavor (e.g. updating power budget of an electronic device based on detecting connection / disconnection of computer peripherals), Shah teaches,
causes the processing core to, in response to a trigger comprising at least one of a removable device connection or disconnection event: [“The electronic device 100 includes example power budget circuitry 200. The power budget circuitry 200 dynamically adjusts power allocation to components of the electronic device 100 and the computer peripherals 102, 104, 106, 108.”, 0017; “ The power budget circuitry 200 includes example peripheral detection circuitry 202, an example power delivery controller (PD) 204,..”, 0018; “ .. power budget circuitry 200 of FIG. 2, may be implemented by hardware alone or by hardware in combination with software and/or firmware…”, 0034; 0042; “If and/or when the EC 208 determines that the system is booted (block 425: YES), the peripheral detection circuitry 202 determines if a device (e.g., a computer peripheral such as a Type-C device) is coupled to a Type-C port (e.g., one of the connector ports 110) (block 430).”, 0043;” The PD 204 asserts an alert (e.g., AttachWait.SRC) to communicate to the EC 208 that one of the computer peripherals 102, 104, 106, 108 has been attached to the electronic device 100. ...Thus, in the example of FIG. 3, the EC 208 has 450 ms to write the power level offset.”, 0025; the EC 208 queries for the power contract of the computer peripheral 102, 104, 106, 108 so that the EC 208 can update a power level offset register, which indicates an amount of power that is offset from the CPU 214 and reserved for the computer peripherals 102, 104, 106, 108”, 0020; “When the connection is complete, and the PD 204 provides power to the computer peripherals 102, 104, 106, 108, the EC 208 further adjusts the power budgeting to the actual power contract of the computer peripherals 102, 104, 106, 108. In some examples, the EC 208 adjusts the power budgeting (i.e., updated the power level offset) within or after a time threshold … EC 208 nonetheless updates the power budget and power level offsets based on the actual contract so that the CPU 214 gains back the maximum power after adjusting for the power for the computer peripherals 102, 104, 106, 108 (e.g., Type-C power) “, 0027; ( i.e in response to an alert/ trigger that a port is connected with a peripheral device updating the power budget) ];
adjust a power limit value without any involvement by an Operating System (OS) configured in the IHS during a runtime of the OS.[0042-0043; “The peripheral detection circuitry 202 may detect an occupied port before and/or during boot up (e.g., from block 410) and/or after boot up (e.g., from block 430). Detection of which port is occupied enables the delivery and/or allocation of power to the occupied port(s) and not to all ports including empty ports. This enables the power budget circuitry 200 to reserve more power for the CPU 214 and avoid overbudgeting power to the ports 110…”, 0044; “a bootup device (such as boot from USB stick) is inserted into one of the Type-C ports. In such examples, the peripheral detection circuitry 202 detects which port is occupied, and the PD 204 selectively releases power to that port, which stalling power on all other ports until the operating system boot-up is successful.”, 0045; 0046; “.. the EC 208 queries for the power contract of the computer peripheral 102, 104, 106, 108 so that the EC 208 can update a power level offset register, which indicates an amount of power that is offset from the CPU 214 and reserved for the computer peripherals 102, 104, 106, 108”, 0020; ... For example, a high power level such as Intel's PL4 is a power level or power limit at which the electronic device 100 can operate without damaging the circuitry. The performance of the CPU 214 depends on the PL4 setting..”, 0021; “ When the computer peripheral 102, 104, 106, 108 is connected to the electronic device 100, the EC 208 takes time to determine the final power role of the computer peripheral 102, 104, 106, 108 before the PL4 offset register can be updated with the actual contracted power. ..EC 208 updates the PL4 offset register with the actual contracted power”, 0022; 0027( i.e. adjusting / reducing the PL4 limit based on the actual power contracted to the peripherals based on the actual power contracted to the peripherals as updated in the offset register. Therefore, the power budgeting circuitry adjusts the power limit of the electronic device based on the actual power contracted to the peripherals during boot up of the device and without the involvement of the OS)] .
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Park with Shah. Shah’s teaching of updating power budget of an electronic device based on detecting connection / disconnection of computer peripherals will substantially improve Park’s system to dynamically adjust power allocation to components of the electronic device and the actual power contracted to the computer peripherals to prevents loss of performance of the device during peak power usage[0015-0017] .
Regarding claims 2,11,17, Park discloses cause the processing core to adjust the power limit value by adjusting a clock speed of a processor configured in the IHS[ “A PDP module may also work with a dynamic control and voltage scaling (“DCVS”) system to modify a clock frequency or voltage level to one or more processing components such that an overall current demand is adjusted and the peak current level maintained within a dynamic current budget “ The operating frequency limiter 183 may adjust the maximum frequency and bin step up limits based on the estimated actual power supply level and indicate as much to the DCVS module 26. The DCVS module 26 may, in turn, modulate the frequency of the power domain. Moreover, in the event that the amount of workload of the power domain exceeds the dynamic power budget set by the PPD threshold controller 179, a trigger signal may be provided back to the DCVS module 26 to reduce voltage in addition to frequency. In doing so, the power domain may be able to operate at a lower voltage for a drastically reduced frequency.”, 0045; “..Using the remaining power budget, an optimum dynamic power budget threshold (“OT”) may be determined.”, 0047; “..the DCVS module 26 may modify frequency and/or voltage settings to the one or more function blocks based on the new OT power budget threshold..”, 0048].
Regarding claims 21, 22, 23, Shah teaches wherein the removable device connection or disconnection event is caused by at least one of a Universal Serial Bus (USB) device, an external display, a docking station, a hub, a network device, or a Network Interface Card (NIC) card. [“ USB Type-C standard ..”, 0013; 0027-0028]
Claims 3,12,18 are rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Shah as applied to claims 1, 10, 16 further in view of Hsu (U.S Patent Application Publication 2012/0131363)
Regarding claims 3,12,18, Park discloses wherein the instructions further cause the processing core to adjust the power limit value [0037; 0040; 0070].
However, Park, Lake does not disclose adjusting a speed of a fan configured in the IHS.
In the same field of endeavor (e.g. controlling power consumption of a heat dissipating device), Hsu teaches adjusting a speed of a fan configured in the IHS [ “: judging whether the total power consumption of the host exceeds a threshold total power consumption; if the total power consumption of the host does not exceed the threshold total power consumption, adjusting the rotating speed of the fan according to the temperature inside the host; and if the total power consumption of the host exceeds the threshold total power consumption, lowering the rotating speed of the fan, so as to reduce the total power consumption of the host to the threshold total power consumption.”, 0014].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Park in view of Shah with Hsu. Hsu’s teaching of determining to control the rotating speed of the fan based on whether the total power consumption exceeding the threshold or not will substantially improve performance and control the power consumption of Park in view of Shah’s system more accurately, when the power supply may go out of order or be damaged (that is, the power supply fails to provide power for the main boards) [0006].
Claims 5,14,19, are rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Shah as applied to claims 1, 10, 16 further in view of Umapathy et. al. (U.S Patent Application Publication 2021/0109578)
Regarding claims 5,14,19, Park discloses cause the processing core to perform the acts of communicating with the devices and adjusting the power limit value[0036; 0037; 0070].
Shah teaches the limitations outlined in Claims 1, 10, 16.
However, Park, Shah does not expressly disclose adjusting the power limit value in response to a request from the operating system.
In the same field of endeavor(e.g. adjusting the CPU peak power based on the USB TYPE-C device states), Umapathy teaches,
adjusting the power limit value in response to a request from the operating system[ “OS Peak Power Manager 104 writes Peak Power Offset “Ppk Offset” to the SoC (System on Chip) Power Control Unit 106 to request adjusting the SoC effective peak power “Effective Ppk” based on the change in the rest-of-platform power requirement…”, 0054; “use three components to adjust the peak power of SoC 5501 based on the states of a USB TYPE-C device 5529. These components include OS Peak Power Manager (part of OS 5552), USB TYPE-C Connector Manager (part of OS 5552), and USB TYPE-C Protocol Device Driver (e.g., one of drivers 5554a, 5554b, 5554c). In some embodiments, the USB TYPE-C Connector Manager sends a synchronous request to the OS Peak Power Manager when a USB TYPE-C power sink device is attached or detached from SoC 5501, and the USB TYPE-C Protocol Device Driver sends a synchronous request to the Peak Power Manager when the power sink transitions device state. In some embodiments, the Peak Power Manager takes power budget from the CPU when the USB TYPE-C connector is attached to a power sink and is active (e.g., high power device state). In some embodiments, the Peak Power Manager gives back the power budget to the CPU for performance when the USB TYPE-C connector is either detached or the attached and power sink device is idle (lowest device state).; 0152].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Park in view of Shah with Umapathy. Umapathy’s teaching of sending a synchronous request to the operating system (OS) peak power manager when a USB TYPE-C power sink device is attached or detached will substantially improve peak power performance of Park in view of Shah’s System by throttling an amount of power to the Soc that is proportional to a difference between a maximum power of the device and an actual power required by the device based on the USB device power state.
Claims 7, 8, 9, 15, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Park in view Shah as applied to claims 1, 10, 16 further in view of Khatri et.al.(U.S Patent Application Publication 2017/0031431; hereinafter “Khatri”; (Reference cited as prior art in previous office action))
Regarding claims 7, 15, 20 Park teaches the limitations outlined in claims 7,15, 20.
However, Park, Shah does not expressly disclose wherein one of the devices comprises another memory coupled to another processor, the other memory having instructions stored thereon that, upon execution by the other processor, cause the other processor to: receive a directive from the controller; in response to the directive, obtain a power consumption level for the device; and send the obtained power consumption level to the controller.
In the same field of endeavor ( e.g. dynamically limits peak power consumption in processing nodes of an IHS), Khatri teaches,
wherein one of the devices comprises another memory coupled to another processor, the other memory having instructions stored thereon that, upon execution by the other processor, cause the other processor to: receive a directive from the Orchestrator; in response to the directive, obtain a power consumption level for the device; and send the obtained power consumption level to the orchestrator. [ “As one aspect of power distribution within IHS 100, PMM 120 and micro-controller 122 can monitor (i) power consumption and workload data across the IHS 100 as well as (ii) the amount of available power provided by the PSUs 152, and PMM 120 can dynamically limit peak power consumption in the processing nodes 150A-D of the IHS based on power-usage and workload data. Micro-controller 122 can trigger changes in CPU operating frequency and power consumption at the individual processing nodes based on changes in the amount of available power, power consumption and workload data. In one embodiment, control of the power subsystem 125 can be provided by MC 110 instead of PMM 120. “, 0041; “each of the processing nodes 150A-D has a complex programmable logic device (CPLD) 152 and a board management controller (BMC) 154. CPLD 152 is coupled to PMM 120 via I2C bus 156. I2C bus 156 carries data and signals. BMC 154 is coupled to PMM 120 via an Ethernet cable 158. Ethernet cable 158 carries data and signals between PMM 120 and BMC 154. Specifically, according to at least one embodiment, PMM 120 provides certain control and/or management signals to the processing nodes 150A-D via I2C bus 156 and one or more select wires within Ethernet cable 158. In one embodiment, PMM 120 can send and receive data signals at a relatively fast rate via the dedicated I2C bus 156 or can send and receive data signals at a relatively slower rate via the Ethernet bus 158, depending on the desired data transfer rate.”, 0042; “FIGS. 3A, 3B and 3C illustrate further details of the contents of PMM memory 220, NC memory 164 and system memory 184. With specific reference to FIG. 3A, PMM memory 220 stores DPPLC firmware 222 which controls the operation of micro-controller 122 in controlling power management functions within IHS 100. PMM memory 220 can store node peak power limits or thresholds 230 and node average power limits or thresholds 240 for each of the processing nodes 150A-D. PMM memory 220 further contains the number of active PSUs 310, the output capacity of each PSU 312, and the total available system power 313 of the IHS, including a peak power output capacity 314 and a sustained output power capacity 316.”, 0056; “ PMM 120, executing DPPLC firmware 222, receives power-usage data 322 and workload data 330 from several node controllers 160. The received data 322/330 includes current node power consumption 324 and a current node workload 330 for each processing node 150A-D within the IHS. A total available system power 313 of the IR..”, 0061; ( i.e each of the nodes corresponds to a device ); “ The plurality of computing or processing nodes 150 are individually labeled as processing nodes A-D 150A-D. MC 110 includes a micro-controller 112 (also generally referred to as a processor), which is coupled via an internal bus 115 to memory 114, I/O interface controller 116, storage 118 and power management module (PMM) 120. Memory 114 can be flash or other form of memory.” 0039].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Park in view of Shah with Khatri. Khatri’s teaching of dynamically limits peak power consumption in processing nodes based on power-usage and workload data from several node controllers, will substantially improve performance of Park in view of Shah’s system by dynamically controlling the device peak power limit of a node based on the power usage and workload data of the respective nodes and the available total power.
Regarding Claim 8, Khatri teaches , wherein the one device comprises a device external to the IHS [.0039; Fig.1D]
Regarding claim 9, Khatri teaches the limitations outlined in cliams 7,8. However Khatri does not expressly teach wherein the at least one device comprises a docking station.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Khatri to implement a docking station as an external device since it has been held to be within the general skill of a worker in the art to select the component on the basis of its suitability for the intended use as a matter of design choice.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 10, 16 have been considered but are moot because the arguments do not apply to Park in view of Shah references being used in the current rejection.
The newly amended claims 21, 22, 23 are rejected as set forth in the above rejection
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Bhattacharjee et. al., U.S Patent Application Publication 2021/0208654, teaches dynamically share system power among charging ports of a multiport power delivery (PD) system is described. The master controller determines a power requirement of each of the devices. The master controller dynamically allocates a system power between each of the ports, independent of a connection sequence of the devices.
Tan et. al., U.S Patent Application Publication 2021/0103330, teaches device-dependent peak power throttling for battery-operated systems.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GAYATHRI SAMPATH whose telephone number is (571)272-5489. The examiner can normally be reached on Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jaweed Abbaszadeh can be reached on 5712701640. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/GAYATHRI SAMPATH/ Examiner, Art Unit 2176
/JAWEED A ABBASZADEH/ Supervisory Patent Examiner, Art Unit 2176
Prosecution Insights