DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 01/09/2026 has been entered.
Response to Amendment
This office action is in response to the amendment filed on 01/09/2026. Claims 1-20 are pending. Claims 1, 13, and 20 are amended.
Response to Arguments
Applicant's arguments filed 01/09/2026 have been fully considered but they are not persuasive.
On page 2 of the Remarks, Applicant submits:
Since the execution of the “vector permutation instruction” does not involve an “arithmetic logic unit” transforming the elements, and “single instruction” prevents the adding of another instruction to meet the requirement, the amendment overcomes the 102 rejection.
However, this argument is not persuasive because Moyer discloses using the execution unit 32 to execute the vector permutation instruction, see col 5 lines 51-56, and the execution unit of Moyer is an arithmetic logic unit as col 4 lines 1-2 discloses that the execution unit 32 can perform arithmetic operations.
As to the double patenting rejections, Applicant requested that the matter be held in abeyance. Applicant is reminded, however, that non-provisional double patenting is not a matter of form. See MPEP 804(I)(B)(1). Any response to this Office action needs to include either a terminal disclaimer or a showing that the claims subject to the double patenting rejections are patentably distinct from the reference applications’ claims.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-20 rejected on the ground of nonstatutory double patenting as being unpatentable over the claims of U.S. Patent No. 11,941,402 as follows.
The limitations of claim 1 of the instant application are taught by claim 1 of the reference patent as follows (the claim language from the reference patent is cited in parenthesis):
1. A processor (claim 1: a processor), comprising:
an arithmetic logic unit (claim 1: an arithmetic logic unit);
an operand vector register configured to store elements (claim 1: an operand vector register configured to store at least a plurality of elements); and
a vector index register configured to store a plurality of indices identifying respectively a plurality of elements from a list stored in the operand vector register (claim 1: a vector index register configured to store a plurality of indices identifying respectively the plurality of elements stored in the operand vector register);
wherein during a vector operation of executing a single instruction in the processor, the processor is configured to generate an output vector using an input vector and the arithmetic logic unit, the input vector having the plurality of elements identified by the vector index register (claim 1: wherein during a vector operation, the processor is configured to generate an output vector using an input vector and the arithmetic logic unit, the input vector having the plurality of elements identified by the plurality of indices stored in the vector index register; where any instruction corresponding to the vector operation is a single instruction executed in the processor).
The limitations of claim 1 of the instant application are taught by claims 1-2 of the reference patent as follows:
2. The processor of claim 1, wherein the vector operation includes a compress operation to store a subset of the plurality of elements loaded from the operand vector register into a first output vector register (claim 2: wherein the vector operation includes a compress operation to store, into the first output vector register and according to the plurality of indices stored in the vector index register, the plurality of elements in the operand vector register)
The limitations of claim 3 of the instant application are taught by claims 1-3 of the reference patent as follows:
3. The processor of claim 2, wherein the processor is further configured to perform an expand operation configured to store the subset of the plurality of elements from the first output vector register into a second output vector register (claim 3: wherein the processor is further configured to perform an expand operation configured to store elements from the first output vector register into a second output vector register)
The limitations of claim 4 of the instant application are taught by claims 1-2 of the reference patent as follows:
4. The processor of claim 2, further comprising a vector load-store unit configured to:
generate effective addresses of load and store operations of the processor; and for each respective index of the vector index register, add the respective index to an effective address for accessing a corresponding position in the operand vector register (claim 1: a vector load-store unit configured to generate effective addresses of load and store operations of the processor… wherein the vector load-store unit is further configured to, for each respective index stored in the vector index register, add the respective index to an effective address for accessing a corresponding position in the operand vector register)
The limitations of claim 5 of the instant application are taught by claims 1-2 and 8 of the reference patent as follows:
5. The processor of claim 4, wherein during the compress operation, the vector load- store unit is configured to: load, from the vector index register from a position corresponding to a count representative of an identification of an incremental position of the vector operation, a first index representative of a first position; load a first element from the operand vector register from the first position represented by the first index; and store the first element into the first output vector register at the position corresponding to the count (claim 8: wherein during the compress operation, the vector load-store unit is configured to: load, from the vector index register from a position corresponding to a count representative of an identification of an incremental position of the vector operation, a first index representative of a first position; load a first element from the operand vector register from the first position represented by the first index; and store the first element into the first output vector register at the position corresponding to the count).
The limitations of claim 6 of the instant application are taught by claims 1-4 of the reference patent as follows:
6. The processor of claim 3, wherein the processor is configured to: load the subset of the plurality of elements from the first output vector register; and iterate incremental positions of the expand operation over the subset of the plurality of elements from the first output vector register according to positions identified by the vector index register (claim 4: load elements from the first output vector register; and iterate incremental positions of the expand operation over elements from the first output vector register according to positions identified by the vector index register).
The limitations of claim 7 of the instant application are taught by claims 1-5 of the reference patent as follows:
7. The processor of claim 6, further comprising a vector load-store unit configured to: load a count representative of an identification of an incremental position of the vector operation; load, from the vector index register from a position corresponding to the count, a second index representative of a second position; load a second element from the first output vector register from the position corresponding to the count; and store the second element into the second output vector register at the second position represented by the second index (claim 5: wherein the vector load-store unit is further configured to: load a count representative of an identification of an incremental position of the vector operation; load, from the vector index register from a position corresponding to the count, a second index representative of a second position; load a second element from the first output vector register from the position corresponding to the count; and store the second element into the second output vector register at the second position represented by the second index)
The limitations of claim 8 of the instant application are taught by claims 1-3 and 6 of the reference patent as follows:
8. The processor of claim 3, wherein the expand operation is further configured to store a scalar into the second output vector register at positions of the second output vector register not identified by the vector index register (claim 6: wherein the expand operation is further configured to store a scalar into the second output vector register at positions of the second output vector register not identified by the vector index register).
The limitations of claim 9 of the instant application are taught by claims 1-3 and 7 of the reference patent as follows:
9. The processor of claim 3, wherein the compress operation is a first compress operation, and a vector load-store unit is configured to: iterate a second compress operation over elements of a second loaded operand vector according to loaded positions stored in a second vector index register; store the elements of the second loaded operand vector into the second output vector register that correspond to the loaded positions stored in the second vector index register; and perform one or more vector operations using elements from the first output vector register and the second output vector register (claim 7: wherein the compress operation is a first compress operation, and a vector load-store unit is configured to: iterate a second compress operation over elements of a second loaded operand vector according to loaded positions stored in a second vector index register; store the elements of the second loaded operand vector into the second output vector register that correspond to the loaded positions stored in the second vector index register; and perform one or more vector operations using elements from the first output vector register and the second output vector register).
The limitations of claim 10 of the instant application are taught by claims 1 and 9 of the reference patent as follows:
10. The processor of claim 1, further comprising: a counter configured to output a count representative of an identification of an incremental position of the vector operation; and a multiplexer configured to receive, as a first input, the identification and, as a second input, an index selected according to the identification from the vector index register and configured to provide an output according to a mode value (claim 9: a counter configured to output a count representative of an identification of an incremental position of the vector operation; and a multiplexer configured to receive, as a first input, the identification and, as a second input, an index selected according to the identification from the vector index register and configured to provide an output according to a mode value).
The limitations of claim 11 of the instant application are taught by claims 1 and 9-10 of the reference patent as follows:
11. The processor of claim 10, wherein the multiplexer is configured to receive, as a selection input, the mode value, the mode value being a value for selection of the count or a value for selection of an output from the vector index register (claim 10: wherein the multiplexer is configured to receive, as a selection input, the mode value, the mode value being a value for selection of the count or a value for selection of an output from the vector index register).
The limitations of claim 12 of the instant application are taught by claims 1 and 11 of the reference patent as follows:
12. The processor of claim 1, comprising a plurality of vector index registers that includes the vector index register (claim 11: a plurality of vector index registers that includes the vector index register).
The limitations of claim 13 of the instant application are taught by claim 12 of the reference patent as follows:
13. A method, comprising:
storing, in an operand vector register in a vector processor, a list of elements (claim 12: storing, in an operand vector register in a vector processor, a list of elements);
storing, in a vector index register in the vector processor, a plurality of indices identifying respectively a plurality of elements from the list stored in the operand vector register (claim 12: storing, in a vector index register in the vector processor, a plurality of indices identifying respectively a plurality of elements among the list of elements stored in the operand vector register); and
generating, during a vector operation of executing a single instruction in the processor, an output vector using an input vector and an arithmetic logic unit, the input vector having the plurality of elements identified by the vector index register (claim 12: during a vector operation: generating, with a vector load-store unit, effective addresses of load and store operations; where any instruction corresponding to the vector operation is a single instruction executed in the processor).
The limitations of claim 14 of the instant application are taught by claims 12-13 of the reference patent as follows:
14. The method of claim 13, further comprising performing, as part of the vector operation, a compress operation to store a subset of the plurality of elements loaded from the operand vector register into a first output vector register (claim 13: performing, as part of the vector operation, a compress operation to store, into a first output vector register and according to the plurality of indices stored in the vector index, the plurality of elements in the operand vector register).
The limitations of claim 15 of the instant application are taught by claim 12-14 of the reference patent as follows:
15. The method of claim 14, further comprising performing an expand operation configured to store the subset of the elements from the first output vector register into a second output vector register (claim 14: performing an expand operation configured to store elements from the first output vector register into a second output vector register).
The limitations of claim 16 of the instant application are taught by claims 12-13 of the reference patent as follows:
16. The method of claim 14, further comprising: generating, with a vector load-store unit, effective addresses of load and store operations; and for each respective index of the vector index register, adding the respective index to an effective address for accessing a corresponding position in the operand vector register (claim 12: generating, with a vector load-store unit, effective addresses of load and store operations; for each respective index of the vector index register, adding the respective index to an effective address for accessing a corresponding position in the operand vector register;).
The limitations of claim 17 of the instant application are taught by claims 12-13 and 16 of the reference patent as follows:
17. The method of claim 16, wherein during the compress operation, the method further comprises: loading, by the vector load-store unit from the vector index register from a position corresponding to a count representative of an identification of an incremental position of the vector operation, a first index representative of a first position; loading a first element from the operand vector register from the first position represented by the first index; and storing the first element into the first output vector register at the position corresponding to the count (claim 16: wherein during the compress operation, the method further comprises: loading, by the vector load-store unit from the vector index register from a position corresponding to a count representative of an identification of an incremental position of the vector operation, a first index representative of a first position; loading a first element from the operand vector register from the first position represented by the first index; and storing the first element into the first output vector register at the position corresponding to the count.).
The limitations of claim 18 of the instant application are taught by claims 12-15 of the reference patent as follows:
18. The method of claim 15, wherein the expand operation is further configured to store a scalar into the second output vector register at positions of the second output vector register not identified by the vector index register (claim 15: wherein the expand operation is further configured to store a scalar into the second output vector register at positions of the second output vector register not identified by the vector index register.).
The limitations of claim 19 of the instant application are taught by claims 12 and 17 of the reference patent as follows:
19. The method of claim 13, wherein a plurality of vector index registers includes the vector index register (claim 17: a plurality of vector index registers includes the vector index register.).
The limitations of claim 20 of the instant application are taught by claims 1-3 of the reference patent as follows:
20. A system, comprising:
a processor (claim 1: a processor);
an arithmetic logic unit (claim 1: an arithmetic logic unit);
an operand vector register configured to store elements (claim 1: an operand vector register configured to store at least a plurality of elements); and
a vector index register configured to store a plurality of indices identifying respectively a plurality of elements from the list stored in the operand vector register (claim 1: a vector index register configured to store a plurality of indices identifying respectively the plurality of elements stored in the operand vector register);
wherein during a first vector operation of executing a single instruction in the processor, the processor is configured to generate an output vector using an input vector and the arithmetic logic unit, the input vector having the plurality of elements identified by the vector index register (claim 1: wherein during a vector operation, the processor is configured to generate an output vector using an input vector and the arithmetic logic unit, the input vector having the plurality of elements identified by the plurality of indices stored in the vector index register; where any instruction corresponding to the vector operation is a single instruction executed in the processor);
wherein the processor is configured to perform, as part of the first vector operation, a compress operation to store a subset of the elements loaded from the operand vector register into a first output vector register (claim 2: wherein the vector operation includes a compress operation to store, into the first output vector register and according to the plurality of indices stored in the vector index register, the plurality of elements in the operand vector register.); and
wherein the processor is further configured to perform an expand operation configured to store the subset of elements from the first output vector register into a second output vector register (claim 3: wherein the processor is further configured to perform an expand operation configured to store elements from the first output vector register into a second output vector register).
Claims 1-20 rejected on the ground of nonstatutory double patenting as being unpatentable over the claims of U.S. Patent No. 11,340,904 as follows.
The limitations of claim 1 of the instant application are taught by claim 1 of the reference patent as follows (the claim language from the reference patent is cited in parenthesis):
1. A processor (claim 1: a vector processor), comprising:
an arithmetic logic unit (claim 1: an arithmetic logic unit);
an operand vector register configured to store elements (claim 1: an operand vector register, configured to store a list of elements); and
a vector index register configured to store a plurality of indices identifying respectively a plurality of elements from a list stored in the operand vector register (claim 1: a vector index register, configured to store a plurality of indices identifying respectively a plurality of elements from the list stored in the operand vector register);
wherein during a vector operation of executing a single instruction in the processor, the processor is configured to generate an output vector using an input vector and the arithmetic logic unit, the input vector having the plurality of elements identified by the vector index register (claim 1: a multiplexer configured to receive… as a second input, an index selected according to the identification from the vector index register and configured to provide an output… wherein during the vector operation, the operand vector register is configured to provide an element from the list as an input to the arithmetic logic unit according to the output from the multiplexer for the incremental position of the vector operation; where any instruction corresponding to the vector operation is a single instruction executed in the processor).
The limitations of claim 2 of the instant application are taught by claim 1 of the reference patent as follows:
2. The processor of claim 1, wherein the vector operation includes a compress operation to store a subset of the plurality of elements loaded from the operand vector register into a first output vector register (claim 1: wherein the vector processor is configured to perform a first vector operation that includes a compress operation to store a subset of the elements loaded from the operand vector register into the first output vector register)
The limitations of claim 3 of the instant application are taught by claim 1 of the reference patent as follows:
3. The processor of claim 2, wherein the processor is further configured to perform an expand operation configured to store the subset of the plurality of elements from the first output vector register into a second output vector register (claim 1: wherein the second vector operation includes an expand operation configured to store the subset of elements from the first output vector register into the second output vector register)
The limitations of claim 4 of the instant application are taught by claim 1 of the reference patent as follows:
4. The processor of claim 2, further comprising a vector load-store unit configured to:
generate effective addresses of load and store operations of the processor; and for each respective index of the vector index register, add the respective index to an effective address for accessing a corresponding position in the operand vector register (claim 1: a vector load-store unit configured to: generate effective addresses of load and store operations of the vector processor; and for each respective index of the vector index register, add the respective index an effective address for accessing a corresponding position in the operand vector register;).
The limitations of claim 5 of the instant application are taught by claim 1 of the reference patent as follows:
5. The processor of claim 4, wherein during the compress operation, the vector load- store unit is configured to: load, from the vector index register from a position corresponding to a count representative of an identification of an incremental position of the vector operation, a first index representative of a first position; load a first element from the operand vector register from the first position represented by the first index; and store the first element into the first output vector register at the position corresponding to the count (claim 1: wherein, during the compress operation, the vector load-store unit is configured to: load the count; load, from the vector index register from a position corresponding to the count, a first index representative of a first position; load a first element from the operand vector register from the first position represented by the first index; and store the first element into the first output vector register at the position corresponding to the count).
The limitations of claim 6 of the instant application are taught by claim 1 of the reference patent as follows:
6. The processor of claim 3, wherein the processor is configured to: load the subset of the plurality of elements from the first output vector register; and iterate incremental positions of the expand operation over the subset of the plurality of elements from the first output vector register according to positions identified by the vector index register (claim 1: wherein during a second vector operation, the vector processor is configured to: load the subset of elements from the first output vector register; and iterate incremental positions of the second vector operation over the subset of elements from the first output vector register according to positions identified by the vector index register).
The limitations of claim 7 of the instant application are taught by claim 1 of the reference patent as follows:
7. The processor of claim 6, further comprising a vector load-store unit configured to: load a count representative of an identification of an incremental position of the vector operation; load, from the vector index register from a position corresponding to the count, a second index representative of a second position; load a second element from the first output vector register from the position corresponding to the count; and store the second element into the second output vector register at the second position represented by the second index (claim 1: wherein, during the expand operation, the vector load-store unit is configured to: load the count; load, from the vector index register from the position corresponding to the count, a second index representative of a second position; load a second element from the first output vector register from the position corresponding to the count; and store the second element into the second output vector register at the second position represented by the second index)
The limitations of claim 8 of the instant application are taught by claims 1 and 5 of the reference patent as follows:
8. The processor of claim 3, wherein the expand operation is further configured to store a scalar into the second output vector register at positions of the second output vector register not identified by the vector index register (claim 5: wherein the expand operation is further configured to store a scalar into the second output vector register at positions of the second output vector register not identified by the vector index register).
The limitations of claim 9 of the instant application are taught by claims 1 and 6 of the reference patent as follows:
9. The processor of claim 3, wherein the compress operation is a first compress operation, and a vector load-store unit is configured to: iterate a second compress operation over elements of a second loaded operand vector according to loaded positions stored in a second vector index register; store the elements of the second loaded operand vector into the second output vector register that correspond to the loaded positions stored in the second vector index register; and perform one or more vector operations using elements from the first output vector register and the second output vector register (claim 6: wherein the vector load-store unit is configured to: iterate a second compress operation over elements of a second loaded operand vector according to loaded positions stored in a second vector index register; store the elements of the second loaded operand vector into the second output vector register that correspond to the loaded positions stored in the second vector index register; and perform one or more vector operations using the elements from the first output vector register and the second output vector register).
The limitations of claim 10 of the instant application are taught by claim 1 of the reference patent as follows:
10. The processor of claim 1, further comprising: a counter configured to output a count representative of an identification of an incremental position of the vector operation; and a multiplexer configured to receive, as a first input, the identification and, as a second input, an index selected according to the identification from the vector index register and configured to provide an output according to a mode value (claim 1: a counter configured to output a count representative of an identification of an incremental position of a vector operation; a multiplexer configured to receive, as a first input, the identification and, as a second input, an index selected according to the identification from the vector index register and configured to provide an output according to a mode value).
The limitations of claim 11 of the instant application are taught by claims 1 and 2 of the reference patent as follows:
11. The processor of claim 10, wherein the multiplexer is configured to receive, as a selection input, the mode value, the mode value being a value for selection of the count or a value for selection of an output from the vector index register (claim 2: wherein the multiplexer is configured to: receive, as a selection input, the mode value, the mode value being a value for selection of the count or a value for selection of the output from the vector index register).
The limitations of claim 12 of the instant application are taught by claims 1 and 3 of the reference patent as follows:
12. The processor of claim 1, comprising a plurality of vector index registers that includes the vector index register (claim 3: a plurality of vector index registers that includes the vector index register).
The limitations of claim 13 of the instant application are taught by claim 1 of the reference patent as follows:
13. A method, comprising:
storing, in an operand vector register in a vector processor, a list of elements (claim 1: an operand vector register, configured to store a list of elements);
storing, in a vector index register in the vector processor, a plurality of indices identifying respectively a plurality of elements from the list stored in the operand vector register (a vector index register, configured to store a plurality of indices identifying respectively a plurality of elements from the list stored in the operand vector register); and
generating, during a vector operation of executing a single instruction in the processor, an output vector using an input vector and an arithmetic logic unit, the input vector having the plurality of elements identified by the vector index register (claim 1: a multiplexer configured to receive… as a second input, an index selected according to the identification from the vector index register and configured to provide an output… wherein during the vector operation, the operand vector register is configured to provide an element from the list as an input to the arithmetic logic unit according to the output from the multiplexer for the incremental position of the vector operation; where any instruction corresponding to the vector operation is a single instruction executed in the processor).
The limitations of claim 14 of the instant application are taught by claim 1 of the reference patent as follows:
14. The method of claim 13, further comprising performing, as part of the vector operation, a compress operation to store a subset of the plurality of elements loaded from the operand vector register into a first output vector register (claim 1: wherein the vector processor is configured to perform a first vector operation that includes a compress operation to store a subset of the elements loaded from the operand vector register into the first output vector register).
The limitations of claim 15 of the instant application are taught by claim 1 of the reference patent as follows:
15. The method of claim 14, further comprising performing an expand operation configured to store the subset of the elements from the first output vector register into a second output vector register (claim 1: wherein the second vector operation includes an expand operation configured to store the subset of elements from the first output vector register into the second output vector register).
The limitations of claim 16 of the instant application are taught by claim 1 of the reference patent as follows:
16. The method of claim 14, further comprising: generating, with a vector load-store unit, effective addresses of load and store operations; and for each respective index of the vector index register, adding the respective index to an effective address for accessing a corresponding position in the operand vector register (claim 1: a vector load-store unit configured to: generate effective addresses of load and store operations of the vector processor; and for each respective index of the vector index register, add the respective index an effective address for accessing a corresponding position in the operand vector register).
The limitations of claim 17 of the instant application are taught by claim 1 of the reference patent as follows:
17. The method of claim 16, wherein during the compress operation, the method further comprises: loading, by the vector load-store unit from the vector index register from a position corresponding to a count representative of an identification of an incremental position of the vector operation, a first index representative of a first position; loading a first element from the operand vector register from the first position represented by the first index; and storing the first element into the first output vector register at the position corresponding to the count (claim 1: wherein, during the compress operation, the vector load-store unit is configured to: load the count; load, from the vector index register from a position corresponding to the count, a first index representative of a first position; load a first element from the operand vector register from the first position represented by the first index; and store the first element into the first output vector register at the position corresponding to the count).
The limitations of claim 18 of the instant application are taught by claims 1 and 5 of the reference patent as follows:
18. The method of claim 15, wherein the expand operation is further configured to store a scalar into the second output vector register at positions of the second output vector register not identified by the vector index register (claim 5: wherein the expand operation is further configured to store a scalar into the second output vector register at positions of the second output vector register not identified by the vector index register).
The limitations of claim 19 of the instant application are taught by claims 1 and 3 of the reference patent as follows:
19. The method of claim 13, wherein a plurality of vector index registers includes the vector index register (claim 3: a plurality of vector index registers that includes the vector index register).
The limitations of claim 20 of the instant application are taught by claim 1 of the reference patent as follows:
20. A system, comprising:
a processor (claim 1: a vector processor);
an arithmetic logic unit (claim 1: an arithmetic logic unit);
an operand vector register configured to store elements (claim 1: an operand vector register, configured to store a list of elements); and
a vector index register configured to store a plurality of indices identifying respectively a plurality of elements from the list stored in the operand vector register (claim 1: a vector index register, configured to store a plurality of indices identifying respectively a plurality of elements from the list stored in the operand vector register);
wherein during a first vector operation of executing a single instruction in the processor, the processor is configured to generate an output vector using an input vector and the arithmetic logic unit, the input vector having the plurality of elements identified by the vector index register (claim 1: a multiplexer configured to receive… as a second input, an index selected according to the identification from the vector index register and configured to provide an output… wherein during the vector operation, the operand vector register is configured to provide an element from the list as an input to the arithmetic logic unit according to the output from the multiplexer for the incremental position of the vector operation; where any instruction corresponding to the vector operation is a single instruction executed in the processor);
wherein the processor is configured to perform, as part of the first vector operation, a compress operation to store a subset of the elements loaded from the operand vector register into a first output vector register (claim 1: wherein the vector processor is configured to perform a first vector operation that includes a compress operation to store a subset of the elements loaded from the operand vector register into the first output vector register); and
wherein the processor is further configured to perform an expand operation configured to store the subset of elements from the first output vector register into a second output vector register (claim 1: wherein the second vector operation includes an expand operation configured to store the subset of elements from the first output vector register into the second output vector register).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3 ,8-9, 12-15, and 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Moyer (US 7,962,718).
Regarding claim 1, Moyer teaches:
1. A processor (Fig. 1, 14), comprising:
an arithmetic logic unit (Fig. 1, 32);
an operand vector register configured to store elements (Fig. 13, R112 stores a plurality of elements); and
a vector index register configured to store a plurality of indices identifying respectively a plurality of elements from the list stored in the operand vector register (col 12 line 61-col 13 line 12: the temporary register holding index values from register 115 is a vector index register, where the index values identify a plurality of elements stored in R112);
wherein during a vector operation of executing a single instruction in the processor, the processor is configured to generate an output vector using an input vector and the arithmetic logic unit, the input vector having the plurality of elements identified by the vector index register (col 12 line 61-col 13 line 12: during the vector permute instruction, see Fig. 13 instruction #14, values are selected from R112 and R113 and stored in R115, the values stored in R115 as a result of the permute instruction is an output vector which uses the input vector stored in R112, which includes the elements identified by the index values, to generate the values stored in R115; col 5 lines 51-56: the execution unit is also used to generate the output vector since the execution unit executes the vector permute instruction).
Regarding claim 2, Moyer teaches:
2. The processor of claim 1, wherein the vector operation includes a compress operation to store a subset of the elements loaded from the operand vector register into a first output vector register (col 12 line 61-col 13 line 12: the vector permute instruction stores the elements loaded from R112 into R115, i.e. a first output vector register, and the vector permute instruction is a compress operation since it only stores some of the elements from R112, i.e. a compressed version of R112, into R115).
Regarding claim 3, Moyer teaches:
3. The processor of claim 2, wherein the processor is further configured to perform an expand operation configured to store the subset of the elements from the first output vector register into a second output vector register (col 13 lines 36-53: the logical OR operation stores elements from R115 into R114, this is an expand operation since elements from R115 are stored/expanded into R114).
Regarding claim 8, Moyer teaches:
8. The processor of claim 3, wherein the expand operation is further configured to store a scalar into the second output vector register at positions of the second output vector register not identified by the vector index register (col 13 lines 17-18: a value of 0 is stored for out-of-range values at positions not identified by the vector index value, the value of 0 is then stored into R114 during the OR/expand operation, see R114 for instruction #15 in Fig. 13 storing 0 in the 6th and 8th positions).
Regarding claim 9, Moyer teaches:
9. The processor of claim 3, wherein the compress operation is a first compress operation, and a vector load-store unit (col 3 lines 54-60: control unit 28 is a vector load-store unit since it controls execution unit 32 for executing vector permute instructions, see col 5 lines 51-56, and since it controls load/store unit 38) is configured to:
iterate a second compress operation over elements of a second loaded operand vector according to loaded positions stored in a second vector index register (col 10 lines 30-45: a second permute instruction is performed/iterated in instruction #5 of Fig. 12 on elements of R113, i.e. a second loaded operand vector, according to positions stored in a temporary register, i.e. a second vector index register, holding index values from R114);
store the elements of the second loaded operand vector into the second output vector register that correspond to the loaded positions stored in the second vector index register (col 10 lines 30-40: the elements of R113 that correspond to the index values are stored into R114, i.e. the second output vector register); and
perform one or more vector operations using the elements from the first output vector register and the second output vector register (the OR operation performed at instruction #20 of Fig. 13 is performed using the elements from R114 and elements from R115 stored in R114).
Regarding claim 12, Moyer teaches:
12. The processor of claim 1, comprising a plurality of vector index registers that includes the vector index register (Fig. 12 R114 in instruction #2, R115 in instruction #11, and the temporary registers that hold the index values, see col 10 lines 40-45 and col 13 lines 3-7, are a plurality of vector index registers).
Regarding claim 13, Moyer teaches:
13. A method, comprising:
storing, in an operand vector register in a vector processor (Fig. 1, 14), a list of elements (Fig. 13, R112 stores a plurality of elements);
storing, in a vector index register in the vector processor, a plurality of indices identifying respectively a plurality of elements from the list stored in the operand vector register (col 12 line 61-col 13 line 12: the temporary register holding index values from register 115 is a vector index register, where the index values identify a plurality of elements stored in R112); and
generating, during a vector operation of executing a single instruction in the processor, an output vector using an input vector and an arithmetic logic unit, the input vector having the plurality of elements identified by the vector index register (col 12 line 61-col 13 line 12: during the vector permute instruction, see Fig. 13 instruction #14, values are selected from R112 and R113 and stored in R115, the values stored in R115 as a result of the permute instruction is an output vector which uses the input vector stored in R112, which includes the elements identified by the index values, to generate the values stored in R115; col 5 lines 51-56: the execution unit is also used to generate the output vector since the execution unit executes the vector permute instruction).
Regarding claim 14, Moyer teaches:
14. The method of claim 13, further comprising performing, as part of the vector operation, a compress operation to store a subset of the elements loaded from the operand vector register into a first output vector register (col 12 line 61-col 13 line 12: the vector permute instruction stores the elements loaded from R112 into R115, i.e. a first output vector register, and the vector permute instruction is a compress operation since it only stores some of the elements from R112, i.e. a compressed version of R112, into R115).
Regarding claim 15, Moyer teaches:
15. The method of claim 14, further comprising performing an expand operation configured to store the subset of the elements from the first output vector register into a second output vector register (col 13 lines 36-53: the logical OR operation stores elements from R115 into R114, this is an expand operation since elements from R115 are stored/expanded into R114).
Regarding claim 18, Moyer teaches:
18. The method of claim 15, wherein the expand operation is further configured to store a scalar into the second output vector register at positions of the second output vector register not identified by the vector index register (col 13 lines 17-18: a value of 0 is stored for out-of-range values at positions not identified by the vector index value, the value of 0 is then stored into R114 during the OR/expand operation, see R114 for instruction #15 in Fig. 13 storing 0 in the 6th and 8th positions).
Regarding claim 19, Moyer teaches:
19. The method of claim 13, wherein a plurality of vector index registers includes the vector index register (Fig. 12 R114 in instruction #2, R115 in instruction #11, and the temporary registers that hold the index values, see col 10 lines 40-45 and col 13 lines 3-7, are a plurality of vector index registers).
Regarding claim 20, Moyer teaches:
20. A system (Fig. 1, 10), comprising:
a processor (Fig. 1, 14);
an arithmetic logic unit (Fig. 1, 32);
an operand vector register configured to store elements (Fig. 13, R112 stores a plurality of elements); and
a vector index register configured to store a plurality of indices identifying respectively a plurality of elements from the list stored in the operand vector register (col 12 line 61-col 13 line 12: the temporary register holding index values from register 115 is a vector index register, where the index values identify a plurality of elements stored in R112);
wherein during a first vector operation of executing a single instruction in the processor, the processor is configured to generate an output vector using an input vector and the arithmetic logic unit, the input vector having the plurality of elements identified by the vector index register (col 12 line 61-col 13 line 12: during the vector permute instruction, see Fig. 13 instruction #14, values are selected from R112 and R113 and stored in R115, the values stored in R115 as a result of the permute instruction is an output vector which uses the input vector stored in R112, which includes the elements identified by the index values, to generate the values stored in R115; col 5 lines 51-56: the execution unit is also used to generate the output vector since the execution unit executes the vector permute instruction);
wherein the processor is configured to perform, as part of the first vector operation, a compress operation to store a subset of the elements loaded from the operand vector register into a first output vector register (col 12 line 61-col 13 line 12: the vector permute instruction stores the elements loaded from R112 into R115, i.e. a first output vector register, and the vector permute instruction is a compress operation since it only stores some of the elements from R112, i.e. a compressed version of R112, into R115); and
wherein the processor is further configured to perform an expand operation configured to store the subset of elements from the first output vector register into a second output vector register (col 13 lines 36-53: the logical OR operation stores elements from R115 into R114, this is an expand operation since elements from R115 are stored/expanded into R114).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Moyer (US 7,962,718) in view of Hall (US 5,226,171) and Buchty (US 2004/0153623).
Regarding claim 10, Moyer teaches:
10. The processor of claim 1,
Moyer does not teach:
a counter configured to output a count representative of an identification of an incremental position of the vector operation; and
a multiplexer configured to receive, as a first input, the identification and, as a second input, an index selected according to the identification from the vector index register and configured to provide an output according to a mode value.
However, Hall teaches:
a counter (col 6 lines 43-47: index counter 92) configured to output a count representative of an identification of an incremental position of a vector operation (col 7 lines 3-10: the counter is set to a starting index and is auto-incremented to provide successive addresses for vector registers during operation of the arithmetic unit, i.e. the count is representative of an identification of an incremental position of a vector operation); and
to receive, as a first input, the identification and, as a second input, an index selected from a vector index register (col 7 lines 53-57: the vector registers are addressed either from an incremented address from the counter or by a memory address register/vector index register).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the execution unit of Moyer to use a counter to access successive locations in its vector registers as taught by Hall. In this combination, Moyer will use a counter to access successive locations in the vector index registers and in the input vector registers (i.e. R112/R113 in Figs. 12 and 13) such that the input vector registers are addressed either directly using the counter or indirectly using index values selected by the counter. One of ordinary skill in the art would have been motivated to make this modification because using a counter is a known technique on the known device of a computer processor for generating values and would yield the predictable result of reducing hardware costs, for example, by freeing up registers that would otherwise be used to hold index values when the counter may be used instead to access a vector register.
The combination of Moyer and Hall does not teach:
a multiplexer configured to receive a first input and a second input and configured to provide an output according to a mode value.
Further, Buchty teaches selecting between addressing modes using multiplexers (Abstract). In
particular, Buchty teaches:
a multiplexer ([0031]: multiplexer 612) configured to receive a first input and a second input, an configured to provide an output according to a mode value ([0031]: multiplexer 612 receives mode select signal 616 as a selecting input to select one of the two inputs to use as an index).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the execution unit of Moyer in view of Hall to use the multiplexer of Buchty for selecting between its counter and vector index registers for accessing an input vector based on a mode value. One of ordinary skill in the art would have been motivated to make this modification
because multiplexing is a known technique on the known device of a computer processor for selecting
between inputs and would yield the predictable result of efficiently implementing selection logic.
Regarding claim 11, Moyer in view of Hall and Buchty teaches:
11. The processor of claim 10, wherein the multiplexer is configured to receive, as a selection input, the mode value, the mode value being a value for selection of the count or a value for selection of the output from the vector index register (Buchty [0031]: the multiplexer receives a mode select signal as a selection input and, in the combination, the multiplexer selects the counter or the output of the vector index register based on the mode select signal).
Prior Art Considerations
While no prior art reject has been given for claims 4-7 and 16-17, these claims are currently rejected under double patenting and are thus not allowable at the current point. The prior art considerations for these claims are the same as the prior art considerations given on pages 33-34 of the Non-Final Rejection dated 06/18/2025.
Conclusion
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/KASIM ALLI/Examiner, Art Unit 2182
/JYOTI MEHTA/Supervisory Patent Examiner, Art Unit 2183