DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Terminal Disclaimer
The terminal disclaimer filed on 05/06/2026 disclaiming the terminal portion of any patent granted on this application which would extend beyond the expiration date of 11,941,402 and 11,340,904 has been reviewed and is accepted. The terminal disclaimer has been recorded. The previously presented double patenting rejections have been withdrawn.
Response to Amendment
This office action is in response to the amendment filed on 05/06/2026. Claims 1-20 are pending. Claims 1-2, 4-5, 13, and 20 are amended.
Response to Arguments
Applicant's arguments filed 05/06/2026, with respect to the rejections under 102 and 103, have been fully considered but they are not persuasive.
The arguments filed on pages 1-2 of the Remarks are not persuasive because they do not include any discussion of the references in view of the claims or the amendments to the claims. Specifically, Applicant's arguments fail to comply with 37 CFR 1.111(b) because they amount to a general allegation that the claims define a patentable invention without specifically pointing out how the language of the claims patentably distinguishes them from the references. Further, Applicant's arguments do not comply with 37 CFR 1.111(c) because they do not show how the amendments avoid the cited references.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7 and 9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 7 recites “a vector load-store unit” in lines 1-2. It is unclear whether this is the same as the vector load-store unit introduced in claim 4 or if they are different. For purposes of examination, they will be interpreted as the same.
Claim 9 recites “a vector load-store unit” in line 2. It is unclear whether this is the same as the vector load-store unit introduced in claim 4 or if they are different. For purposes of examination, they will be interpreted as the same.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 12-15, and 18-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Moyer (US 7,962,718).
Regarding claim 1, Moyer teaches:
1. A processor (Fig. 1, 14), comprising:
an arithmetic logic unit (Fig. 1, 32);
an operand vector register configured to store elements (Fig. 13, R112 stores a plurality of elements); and
a vector index register configured to store a plurality of indices identifying respectively a plurality of elements from the list stored in the operand vector register (col 12 line 61-col 13 line 12: the temporary register holding index values from register 115 is a vector index register, where the index values identify a plurality of elements stored in R112);
wherein during a vector operation of executing a single instruction in the processor, the processor is configured to generate an output vector using an input vector and the arithmetic logic unit, the input vector having the plurality of elements identified by the vector index register and the output vector having a plurality of results corresponding respectively to the plurality of elements (col 12 line 61-col 13 line 12: during the vector permute instruction, see Fig. 13 instruction #14, values are selected from R112 and R113 and stored in R115, the values stored in R115 as a result of the permute instruction is an output vector which uses the input vector stored in R112, which includes the elements identified by the index values, to generate the values stored in R115 (i.e., the output vector has a plurality of result elements that correspond respectively to the plurality of elements in the input vector that the index vector identifies); col 5 lines 51-56: the execution unit is also used to generate the output vector since the execution unit executes the vector permute instruction).
Regarding claim 12, Moyer teaches:
12. The processor of claim 1, comprising a plurality of vector index registers that includes the vector index register (Fig. 12 R114 in instruction #2, R115 in instruction #11, and the temporary registers that hold the index values, see col 10 lines 40-45 and col 13 lines 3-7, are a plurality of vector index registers).
Regarding claim 13, Moyer teaches:
13. A method, comprising:
storing, in an operand vector register in a vector processor (Fig. 1, 14), a list of elements (Fig. 13, R112 stores a plurality of elements);
storing, in a vector index register in the vector processor, a plurality of indices identifying respectively a plurality of elements from the list stored in the operand vector register (col 12 line 61-col 13 line 12: the temporary register holding index values from register 115 is a vector index register, where the index values identify a plurality of elements stored in R112); and
generating, during a vector operation of executing a single instruction in the processor, an output vector using an input vector and an arithmetic logic unit, the input vector having the plurality of elements identified by the vector index register, the output vector having a plurality of results generated respectively from the plurality of elements using the arithmetic logic unit (col 12 line 61-col 13 line 12: during the vector permute instruction, see Fig. 13 instruction #14, values are selected from R112 and R113 and stored in R115, the values stored in R115 as a result of the permute instruction is an output vector which uses the input vector stored in R112, which includes the elements identified by the index values, to generate the values stored in R115 (i.e., the output vector has a plurality of result elements that are generated respectively from the plurality of elements in the input vector that the index vector identifies); col 5 lines 51-56: the execution unit/arithmetic logic unit is also used to generate the output vector since the execution unit executes the vector permute instruction).
Regarding claim 14, Moyer teaches:
14. The method of claim 13, further comprising performing, as part of the vector operation, a compress operation to store a subset of the elements loaded from the operand vector register into a first output vector register (col 12 line 61-col 13 line 12: the vector permute instruction stores the elements loaded from R112 into R115, i.e. a first output vector register, and the vector permute instruction is a compress operation since it only stores some of the elements from R112, i.e. a compressed version of R112, into R115).
Regarding claim 15, Moyer teaches:
15. The method of claim 14, further comprising performing an expand operation configured to store the subset of the elements from the first output vector register into a second output vector register (col 13 lines 36-53: the logical OR operation stores elements from R115 into R114, this is an expand operation since elements from R115 are stored/expanded into R114).
Regarding claim 18, Moyer teaches:
18. The method of claim 15, wherein the expand operation is further configured to store a scalar into the second output vector register at positions of the second output vector register not identified by the vector index register (col 13 lines 17-18: a value of 0 is stored for out-of-range values at positions not identified by the vector index value, the value of 0 is then stored into R114 during the OR/expand operation, see R114 for instruction #15 in Fig. 13 storing 0 in the 6th and 8th positions).
Regarding claim 19, Moyer teaches:
19. The method of claim 13, wherein a plurality of vector index registers includes the vector index register (Fig. 12 R114 in instruction #2, R115 in instruction #11, and the temporary registers that hold the index values, see col 10 lines 40-45 and col 13 lines 3-7, are a plurality of vector index registers).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Moyer (US 7,962,718) in view of Hall (US 5,226,171) and Buchty (US 2004/0153623).
Regarding claim 10, Moyer teaches:
10. The processor of claim 1,
Moyer does not teach:
a counter configured to output a count representative of an identification of an incremental position of the vector operation; and
a multiplexer configured to receive, as a first input, the identification and, as a second input, an index selected according to the identification from the vector index register and configured to provide an output according to a mode value.
However, Hall teaches:
a counter (col 6 lines 43-47: index counter 92) configured to output a count representative of an identification of an incremental position of a vector operation (col 7 lines 3-10: the counter is set to a starting index and is auto-incremented to provide successive addresses for vector registers during operation of the arithmetic unit, i.e. the count is representative of an identification of an incremental position of a vector operation); and
to receive, as a first input, the identification and, as a second input, an index selected from a vector index register (col 7 lines 53-57: the vector registers are addressed either from an incremented address from the counter or by a memory address register/vector index register).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the execution unit of Moyer to use a counter to access successive locations in its vector registers as taught by Hall. In this combination, Moyer will use a counter to access successive locations in the vector index registers and in the input vector registers (i.e. R112/R113 in Figs. 12 and 13) such that the input vector registers are addressed either directly using the counter or indirectly using index values selected by the counter. One of ordinary skill in the art would have been motivated to make this modification because using a counter is a known technique on the known device of a computer processor for generating values and would yield the predictable result of reducing hardware costs, for example, by freeing up registers that would otherwise be used to hold index values when the counter may be used instead to access a vector register.
The combination of Moyer and Hall does not teach:
a multiplexer configured to receive a first input and a second input and configured to provide an output according to a mode value.
Further, Buchty teaches selecting between addressing modes using multiplexers (Abstract). In
particular, Buchty teaches:
a multiplexer ([0031]: multiplexer 612) configured to receive a first input and a second input, an configured to provide an output according to a mode value ([0031]: multiplexer 612 receives mode select signal 616 as a selecting input to select one of the two inputs to use as an index).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the execution unit of Moyer in view of Hall to use the multiplexer of Buchty for selecting between its counter and vector index registers for accessing an input vector based on a mode value. One of ordinary skill in the art would have been motivated to make this modification
because multiplexing is a known technique on the known device of a computer processor for selecting
between inputs and would yield the predictable result of efficiently implementing selection logic.
Regarding claim 11, Moyer in view of Hall and Buchty teaches:
11. The processor of claim 10, wherein the multiplexer is configured to receive, as a selection input, the mode value, the mode value being a value for selection of the count or a value for selection of the output from the vector index register (Buchty [0031]: the multiplexer receives a mode select signal as a selection input and, in the combination, the multiplexer selects the counter or the output of the vector index register based on the mode select signal).
Allowable Subject Matter
Claims 2-6, 8, and 16-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The reasons for the indication of allowable subject matter of claim 4 and 16-17 are the same as the reasons given in the Prior Art Considerations section on pages 33-34 of the Non-Final Rejection dated 06/18/2025. Claims 2-3, 5-6, and 8 have been amended to depend from claim 4 and would be allowable for the same reasons.
While no prior art rejection is given for claims 7 and 9, these claims are currently rejected under 112(b) and are thus not allowable at the current point. The prior art considerations for claims 7 and 9 are the same as the prior art considerations for claim 4 as claims 7 and 9 depend from claim 4.
Claim 20 is allowed. The reasons for allowance of claim 20 are the same as the reasons given in the Prior Art Considerations section on pages 33-34 of the Non-Final Rejection dated 06/18/2025 with respect to claim 6 as claim 20 has been amended to include the allowable subject matter of claim 6.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/KASIM ALLI/Examiner, Art Unit 2182 /JYOTI MEHTA/Supervisory Patent Examiner, Art Unit 2183
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