DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 4, 6-13, 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Darrington et al (U.S. U.S. 9,052,835), and further in view of Nemawarkar et al (U.S. 9,996,262), and further in view of Zia et al (U.S. 2017/0199667).
Regarding claim 1:
A memory controller, comprising:
a host interface circuit configured to:
obtain commands from a host; Darrington teaches in FIG. 1 is a block diagram of computer system 10 including host 12 connected to storage device 14. Communication between host 12 and SSD 14 is via data bus 16 (e.g., peripheral component interconnect express (PCIe) bus), and operates within the framework of the non-volatile memory express (NVMe) communication interface. Fig. 1, SSD controller 40 connects to host 12 via PCIe Bus (e.g. interface).
and queue the commands in a buffer; Fig. 2, at step 52, SSD controller 40 fetches the I/O command from I/O submission queue 30. At step 54, SSD controller 40 stores the fetched command in one of the internal queues 40a-40n.
and a processor coupled to the host interface circuit and configured to:
detect whether there is an abort command in the commands, wherein the abort command is to instruct to abort a target command in the commands; and abort the target command in response to execution of the abort command. Fig. 2 and corresponding text, at step 60, an administrative abort command is generated by first partition 24 with respect to an I/O command placed on I/O submission queue 30 (shown at step 50). At step 64, SSD controller 40 fetches the administrative abort command from administration submission queue 20. At step 66, SSD controller 40 checks internal queues 40a-40n for the I/O command to be aborted. If the I/O command is located within one of the internal queues 40a-40n, SSD controller 40 determines whether it is practical to stop execution of the command. SSD controller 40 may determine that the command may be safely aborted, at which point the command is removed from the respective internal queue. If the abort is successful, SSD controller 40 places a result into the I/O completion queue that indicates the command was aborted (Darrington, 4:20-5:25, 5:40-50).
It is noted that Darrington does not teach the host interface circuit or a processor. However, one ordinary skill in the art would appreciate that a SSD controller, which is capable of communicate with a host via PCIe bus (Darrington, Fig. 1), would include the functions of the host interface circuit, or a processor. In this context, one skill artisan would be able to modify the controller of Darrington to include the host interface circuit, or a processor (mutatis mutandis) and expect predictable results.
However, to promote compact prosecution, a prior art such as Nemawarkar reference teaches a receiving unit 108 may be configured to receive commands from the host 102, and determine how or where to direct the command within the storage controller 104. For example, commands received by the receiving unit 108 may be directed to a buffer memory or other command queue, directed to the CPU 112. The CPU may implement procedures to locate and abort the selected command based on the abort command (Fig. 1, 3:45-55). The receiving unit 108 and CPU 112 are part of a storage controller 104 (3:30-45). The receiving unit 108 and CPU 112 include integrated circuit. The CPU 112 is able to perform processing for received commands, control operation of components of the storage controller 104 (4:4:15-25).
One of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to incorporate the teaching of Nemawarkar into the teaching of Darrington to have a interface circuit queues a command in a queue. The motivation for doing so is applying a known technique to a known device (method, or product) ready for improvement to yield predictable results, which avoids overloading storage system processing speed.
Nemawarkar further discloses abort command placed in administrative queue (“admin queue”) is given priority over I/O command (4:35-45). However, Darrington does not teach “in response to detecting the existence of the abort command in the commands: prioritize execution of the abort command above other commands in the commands; and after execution of the abort command to abort execution of the target command, resume execution of remaining commands in the commands in sequence in an original order of the commands”.
In an analogous art of memory command management, Singh discloses, in Fig. 2A-2F, a technique to abort a command in a command queue currently holding a plurality of commands (Fig. 2A, I/O queue 125 of SSD 121 is holding command 1 to command 7 (Cmd1 – Cmd7). A host issues an abort command to abort a target command (Cmd6, ¶0025, Figs. 2B-2C). The SSD 121 places the abort command in admin queue 127 (Figs. 2A-2F). After the abort command is executed on priority, the SSD 121 continues with the execution of commands Cmd2 to Cmd5 and then Cmd7 (¶0026, Figs. 2D-2F). Thus, Singh discloses the idea detecting an abort command in a command queue, prioritizing execution of the abort command, and resume execution of remaining commands in the command queue in sequence of original order after the abort command is completed.
Both of Singh and Darrington disclosures are directed to manage abort command technique as shown above. Thus, one of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to incorporate the teaching of Singh into the teaching of Darrington to obtain the claimed limitations above. The motivation for doing so is applying a known technique of Singh to a known device (method, or product) of Darrington ready for improvement to yield predictable results, which avoids delaying abort command (Singh, ¶0022).
Claims 10, and 19 recites a method and system similar to claim 1, and are rejected under same ground of rejection presented supra.
Regarding claim 2:
The memory controller according to claim 1, wherein the commands comprise at least one admin command, the processor is configured to:
detect whether there is a first sub-abort command in the admin command queue, wherein the abort command comprises the first sub-abort command, the first sub-abort command is to instruct to abort a target admin command in the admin command queue, and the target command comprises the target admin command; and abort the target admin command in response to the first sub-abort command. Nemawarkar teaches the idea of abort a selected command based on an admin command placed in an admin SQ, wherein the selected command is an another admin command (Nemawarkar, abort commands may include admin commands placed into the admin SQ 332. Abort commands may identify another selected command which is to be aborted. The selected command may be an I/O command, or another admin command. In addition to its own command ID, SQ ID, and other information identifying the abort command itself, the abort command may also include a command ID, an SQ ID, or other information identifying the selected command to abort, 9:55-10:-25).
Claims 11, and 20 recite a method similar to functions performed by the device in claim 2, and is rejected under same rationale cited in claim 2.
Regarding claim 3:
The memory controller according to claim 2, wherein the commands further comprise at least one I/O command, and the processor is configured to: detect whether there is a second sub-abort command in the admin command queue, wherein the abort command comprises the second sub-abort command, the second sub-abort command is to instruct to abort a target I/O command in the I/O command queue, and the target command comprises the target I/O command; and abort the target I/O command in response to the second sub-abort command. Nemawarkar teaches the idea of abort a selected I/O command (Nemawarkar, abort commands may include admin commands placed into the admin SQ 332. Abort commands may identify another selected command which is to be aborted. The selected command may be an I/O command, or another admin command. In addition to its own command ID, SQ ID, and other information identifying the abort command itself, the abort command may also include a command ID, an SQ ID, or other information identifying the selected command to abort, 9:55-10:-25). Darrington also teaches abort I/O command (Fig. 2, Fig. 3, and corresponding text).
Claim 12 recites a method similar to functions performed by the device in claim 3, and is rejected under same rationale cited in claim 3.
Regarding claim 4:
The memory controller according to claim 1, wherein each of the commands has a command identifier, the command identifiers of any two of the commands are different, and the abort command comprises a target command identifier of the target command, and the processor is further configured to: Nemawarkar, an abort command may include its own command ID and SQ ID, and may also include the command ID and SQ ID for the selected command to be aborted (9:20-35).
determine the target command identifier of the target command in response to the abort command; and match the command identifiers of the commands with the target command identifier to determine the target command. Nemawarkar, command ID is compared to determine selected command to be abort, and is aborted. (Nemawarkar, 10:5-60).
Claim 13 recites a method similar to functions performed by the device in claim 4, and is rejected under same rationale cited in claim 4.
Regarding claim 6:
The memory controller according to claim 4, wherein the commands comprise at least one I/O command, and the processor is configured to: determine the target command identifier of a target I/O command in response to a second sub-abort command, wherein the abort command comprises the second sub-abort command, the second sub-abort command is to instruct to abort the target I/O command, and the target command comprises the target I/O command; and match the command identifiers of the I/O commands in the I/O command queue with the target command identifier one by one to determine the target I/O command.
Nemawarkar teaches the idea of abort a selected I/O command (Nemawarkar, abort commands may include admin commands placed into the admin SQ 332. Abort commands may identify another selected command which is to be aborted. The selected command may be an I/O command, or another admin command. In addition to its own command ID, SQ ID, and other information identifying the abort command itself, the abort command may also include a command ID, an SQ ID, or other information identifying the selected command to abort, 9:55-10:-25). Darrington also teaches abort I/O command (Fig. 2, Fig. 3, and corresponding text).
Claim 15 recites a method similar to functions performed by the device in claim 6, and is rejected under same rationale cited in claim 6.
Regarding claim 7:
The memory controller according to claim 6, wherein the host interface circuit is configured to: obtain the I/O commands one by one from the host; Darrington, Fig. 2, at step 50, the I/O operation between host 12 and SSD 14 is initiated by placing an I/O command on I/O submission queue 30. For example, the command may be a read command or a write command, and may specify the memory location associated with SSD 14 to be read or written to. In addition, at this step device driver 28 provides an indication to SSD controller 40 that I/O submission queue 30 has a command ready to be fetched (referred to as a "doorbell ringer"). In one embodiment, I/O submission queue 30 is a circular buffer maintained by a head pointer and a tail pointer (neither of which is shown). Commands fetched from I/O submission queue 30 are fetched in the order they are placed in the queue. However, SSD controller 40 may change the order in which the commands are executed. At step 52, SSD controller 40 fetches the I/O command from I/O submission queue 30. At step 54, SSD controller 40 stores the fetched command in one of the internal queues 40a-40n. At step 56, SSD controller 40 executes the I/O command from one of the stored internal queues 40a-40n. At step 57, having completed execution of the I/O command, SSD controller 40 returns a result to I/O completion queue 32. For example, the result may indicate whether the command was executed successfully or not. At step 58, first partition 24 fetches the result from I/O completion queue 32 and reads the results.
and the processor is configured to: each time one of the I/O commands is obtained, match the command identifier of the obtained one of the I/O commands with the target command identifier to determine the target I/O command. Nemawarkar, the host 102 may issue an abort command, directing the storage controller 104 to abort execution of a previous command from the host 102. The abort command may include information identifying the command selected for aborting, such as a command ID, a host submission queue (e.g. a submission queue ID, or SQ ID) into which the selected command was placed for retrieval by the storage controller 104, or other information. The abort command may be received at the receiving unit 108, which may direct the abort command to the CPU 112. The CPU may implement procedures to locate and abort the selected command based on the abort command (4:25-35).
Claim 16 recites a method similar to functions performed by the device in claim 7, and is rejected under same rationale cited in claim 7.
Regarding claim 8:
The memory controller according to claim 7, wherein the processor is configured to: obtain a number of the I/O commands to be sent at a preset moment in the host; Nemawarkar, the receiving unit may determine the number of incoming commands to check against the abort registers 322 based on a number of commands in a submission queue (SQ) when the abort command is received. For example, the abort command may identify a submission queue ID (SQ ID) for the selected command to be aborted, indicating the SQ into which the selected command was placed by the host 102 (11:20-35).
and each time one of the I/O commands for the preset moment is obtained, match the command identifier of the obtained one of the I/O commands for the preset moment with the target command identifier to determine the target I/O command. Nemawarkar, Fig. 4, the receiving unit may compare the command ID and SQ ID of received commands against the command ID and SQ ID stored in an abort register of the receiving unit. The method 400 may include determining if the selected command has been received at the receiving unit, at 408. For example, if the command ID and SQ ID of a received command matches the command ID and SQ ID of the selected command, a match may be determined (12:20-60).
Claim 17 recites a method similar to functions performed by the device in claim 8, and is rejected under same rationale cited in claim 8.
Regarding claim 9:
The memory controller according to claim 8, wherein the processor is further configured to: in response to I/O commands updated after the preset moment are obtained, the matching of the command identifiers of the updated I/O commands with the target command identifier is no longer performed. Nemawarkar also teaches that after an I/O operation correspond to a command is successfully complete, the completion unit notifies the host that the command (via command ID) was completed. Nemawarkar teaches the receiving unit 108 may initially receive every command from the host 102 to the storage controller 106, and may therefore act as a first “gatekeeper” for received commands, the completion unit 110 may receive a notification from other components of the storage controller 104 for most or every completed command which was received from the host 102, and may thereby act as a final “gatekeeper” for every completed host command (3:45-4:20). Thus, it has been understood that after an I/O command is completed, the host queue commands are updated with new or pending commands. Thus, the matching command ID of abort target command is unnecessary.
Claim 18 recites a method similar to functions performed by the device in claim 9, and is rejected under same rationale cited in claim 9.
Claims 5, 14 are rejected under 35 U.S.C. 103 as being unpatentable over Darrington et al (U.S. U.S. 9,052,835), in view of Nemawarkar et al (U.S. 9,996,262), further in view of Singh et al (U.S. 2023/0176785), and further in view of Stone et al (U.S. 10,282,103).
Regarding claim 5:
The memory controller according to claim 4, wherein the host interface circuit is further configured to: obtain a command sets from the host, wherein each of the command set has a command set identifier, command set identifiers of any two command sets are different, and the abort command further comprises a target set identifier of the target command set where the target command is located; and the processor is further configured to: determine the target command set identifier of the target command set in response to the abort command; and match the command set identifiers of the command sets with the target command set identifier to determine the target command set in the command.
It is noted that the examiner has use broadest reasonable interpretation (BRI) to interpret a command is considered a set itself, based on mathematical definition of a set. Each command is associated with a command identifier (command ID), and a queue including queue identifier (ID). The processor is configured to determine the target command based on the target command ID, and its associated queue via the queue ID. Nemawarkar teaches the host 102 may issue an abort command, directing the storage controller 104 to abort execution of a previous command from the host 102. The abort command may include information identifying the command selected for aborting, such as a command ID, a host submission queue (e.g. a submission queue ID, or SQ ID) into which the selected command was placed for retrieval by the storage controller 104, or other information. The abort command may be received at the receiving unit 108, which may direct the abort command to the CPU 112. The CPU may implement procedures to locate and abort the selected command based on the abort command (3:40-65,4:25-35). Nemawarkar, Fig. 4, the receiving unit may compare the command ID and SQ ID of received commands against the command ID and SQ ID stored in an abort register of the receiving unit. The method 400 may include determining if the selected command has been received at the receiving unit, at 408. For example, if the command ID and SQ ID of a received command matches the command ID and SQ ID of the selected command, a match may be determined (12:20-60). It would have been obvious to one skilled artisan to derive and understand from the teaching of Nemawarkar to determine location of the target command to be abort, based on the command set ID.
However, to promote compact prosecution, in an analogous art of command aborting, Stone teaches an idea that a storage control circuit is configured to receive a queue deletion command from a host device, the queue deletion command including a queue identifier for a selected command queue to be deleted. The storage control circuit may abort each command associated with the selected command queue and pending at the apparatus based on the queue identifier, and send a completion indicator to notify the host device that the selected command queue is deleted after each command associated with the selected command queue is aborted (1:25-40). It is noted that, based on Stone’s reference, there are multiple commands held in a queue, thus, the queue deletion command is considered command set abort command.
One of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to incorporate the teaching of Stone into the teaching of Darrington to obtain the claimed limitations above. The motivation for doing so is to apply a known technique, into the device of Darrington ready for improvement, to yield predictable results, which aborting a plurality of command within a queue with a single command.
Claim 14 recites a method similar to functions performed by the device in claim 5, and is rejected under same rationale cited in claim 5.
Response to Arguments
Applicant’s arguments with respect to claims 1-20, especially independent claims 1, 10have been considered but are in light of new grounds of rejection presented supra.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Zia et al (U.S. 2017/0199667) discloses processing of abort commands is prioritized such that abort commands are processed before all I/O commands received before the abort commands are processed.
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/KHOA D DOAN/ Primary Examiner, Art Unit 2133