DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the features drawn to the claimed limitations “the first bit line metal line and the second bit line metal line are respectively connected to sense amplifiers of a same column of the plurality of columns” and “the first memory cell includes a second direct backside contact between an upper surface of a second complementary bit line metal line and a lower surface of a source/drain metal of the complementary bit line transistor of the second memory cell to electrically connect the second complementary bit line metal line with the source/drain metal of the complementary bit line transistor of the second memory cell” must be shown or the features canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4, 6-8, and 14-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 4, the limitations “a first sub-group of the plurality of sub-groups is electrically connected to a sense amplifier after the first memory cell is disposed” and “a second sub-group of the plurality of sub-groups is electrically connected to the sense amplifier after the second memory cell is disposed in the first direction in at least one of second column and then the second memory cell is disposed” use the terms “after” and “and then” to limit the claim. However, those terms appear to pertain to process-steps, which render the device claim unclear in its intended scope to a person of ordinary skill in the art. Additionally, it appears that the limitation “a second sub-group of the plurality of sub-groups is electrically connected to the sense amplifier after the second memory cell is disposed in the first direction in at least one of second column and then the second memory cell is disposed” is logically inconsistent because the phrase “after the second memory cell is disposed” is followed by “and then the second memory cell is disposed”, implying that the second memory cell can be disposed after it had already been disposed, a logical contradiction. For purposes of examination on the merits these process limitations will be understood to convey that the memory cells are at some point disposed in the device, regardless of the exact order of process steps involved.
Additionally, the phrases “at least one of first column” and “at least one of second column” are unclear as to the intended meaning: it is unclear how “at least one of” first and second columns relate to the previously recited “plurality of columns”, and the intended scope of a first column or second column is ambiguous due to them being introduced alongside the phrase “at least one of”, seemingly implying that each of the first and second columns are perhaps distinct types of column-structures which may be repeated within the “plurality of columns”, but the current claim-language appears to the Examiner to be inconclusive. For purposes of examination on the merits these features will be understood to convey that each of the first and second columns may be distinct types of column-structures which may be repeated within the “plurality of columns”.
As a further consideration of a related point, claim 4 recites “a first sub-group of the plurality of sub-groups is electrically connected to a sense amplifier”, “a second sub-group of the plurality of sub-groups is electrically connected to the sense amplifier”, and “the first column of the first sub-group and the second column of the second sub-group are alternately disposed in a second direction intersecting the first direction”. However, claim 1 already recited “including first and second memory cells in a same column and different rows”. It is unclear to the Examiner how two sub-groups are to be alternately disposed in the claimed second direction in two separately identified “first and second” columns when the first and second memory cells must be in the same column, and also when the first and second sub-groups are evidently connected to the same instance of a sense amplifier. For purposes of examination on the merits, it will be understood that the first and second sub-groups of the claim may be located in separate columns.
Due to their dependence on claim 4, claims 6-7 are also rejected on this basis.
Regarding claim 8, the limitation “the first bit line metal line and the second bit line metal line are respectively connected to sense amplifiers of a same column of the plurality of columns” is recited. It is unclear to the Examiner how multiple sense amplifiers are present in a same column when Applicant’s disclosure consistently illustrates and discusses a single sense amplifier in a given column (sense amplifier SA of FIG. 4, ¶ [0007, 0051-0054] of specification).
For purposes of examination on the merits, the plural instance of “sense amplifiers” is understood to imply that since there is a plurality of columns, each column of that plurality includes a sense amplifier, so there are multiple sense amplifiers in the device.
Regarding claim 14, the limitations “the first memory cell includes a second direct backside contact between an upper surface of a second complementary bit line metal line and a lower surface of a source/drain metal of the complementary bit line transistor of the second memory cell to electrically connect the second complementary bit line metal line with the source/drain metal of the complementary bit line transistor of the second memory cell” are recited. The direct backside contacts DBC are illustrated in FIGS. 6-8 and discussed in ¶ [0071-0072] of the present specification. ¶ [0080] also teaches that no direct backside contacts are present in the second memory cell to allow for independent operations, and this appears to be corroborated by the figures (e.g. FIG. 12 which illustrates the first and second cells side by side, and only the first cell includes the direct backside contacts). Therefore, it is unclear to the Examiner how a second direct backside contact electrically connects a second complementary bit line metal line with a bit line transistor in the second memory cell.
For purposes of examination on the merits, mentions of the “second memory cell” in this claim will be interpreted to be also applicable to the “first memory cell”.
Claim 15 recites the limitation "the pair of first power supply metal lines" in lines 10-11 of the claim. There is insufficient antecedent basis for this limitation in the claim, because only a singular instance of a first power supply metal line was given antecedent basis in line 8 of the claim.
Claim 15 also recites “a pair of second bit line metal lines between each of the pair of second power supply metal lines and the first power supply metal line at the first upper metal level and extending in the first direction”. It is unclear to the Examiner how to best interpret this limitation as it appears to claim that one entity (a pair of second bit line metal lines) is between three separate entities (each of the pair of second power supply metal lines and the first power supply metal line). As it is best understood for purposes of examination on the merits, it will suffice that both of the “pair of second bit line metal lines” are located between any two of the various “power supply metal lines”.
Due to their dependence on claim 15, claims 16-20 are also rejected on these bases.
Claim 19 is further rejected due to it reciting the limitation “a pair of first lower word line metal lines” when claim 17, upon which it depends, already recited the same limitation. It is unclear whether the instance of the limitation “a pair of first lower word line metal lines” introduced in claim 19 is to the same feature with the same name from claim 17, or if it is a new pair. For purposes of examination on the merits, it will be assumed that the instance of “a pair of first lower word line metal lines” in claim 19 reiterates the pair that was introduced in claim 17. Under this interpretation, it is held that “a pair of first lower word line metal lines” may be simultaneously “electrically connected to” a first memory cell (claim 17) and included in the same first memory cell (claim 19).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3 and 5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US patent publication US 20210343332 (Chiu et al hereinafter Chiu).
Regarding claim 1, Chiu discloses a memory device (the device of FIGS. 1-2, 9A-9B ¶ [0004-0005, 0013-0014, 0047-0048]), comprising: a memory cell array (FIG. 1, array 102 of memory cells 104 ¶ [0028]) including a plurality of memory cells (FIGS. 1-2, memory cells 104 ¶ [0028]) arranged in a plurality of columns and rows (FIG. 1, rows and columns of memory cells are arranged along X and Y directions ¶ [0028]) and including first and second memory cells (FIGS. 9A-9B, memory cells 104A and 104B are respectively first and second memory cells in a same column and different rows ¶ [0047-0048]) in a same column and different rows, the plurality of columns intersecting the plurality of rows in a plan view (FIG. 9A is a plan/top view ¶ [0047]); a first bit line transistor (FIG. 9A, bit cell 104B may have a circuit according to cell 104 of FIG. 2 which includes transistor PG-1 ¶ [0030, 0049]) electrically connected between the first memory cell and a first bit line metal line (FIG. 2, bit-line BL is located on a side of transistor PG-1 away from the rest of the memory cell ¶ [0032]); and a second bit line transistor (FIG. 9A, bit cell 104A may have a circuit according to cell 104 of FIG. 2 which includes transistor PG-1 ¶ [0030, 0048]) electrically connected between the second memory cell and a second bit line metal line (FIG. 2, bit-line BL is located on a side of transistor PG-1 away from the rest of the memory cell), wherein the first bit line metal line is on an upper surface of the memory cell array (FIG. 9B, memory cell 104B has bit-line BL on an upper surface of its device portion along the Z direction ¶ [0049]), and the second bit line metal line is on a lower surface of the memory cell array (FIG. 9B, memory cell 104A has bit-line BL on a lower surface of its device portion along the Z direction ¶ [0048], opposite the bit-line of cell 104B) opposite the upper surface of the memory cell array.
Regarding claim 2, Chiu discloses the limitations of claim 1 as detailed above and further discloses that each of the first and second memory cells is a static random access memory cell (FIGS. 1-2, 9A-9B, memory cells 104A and 104B are part of an SRAM device and are SRAM cells ¶ [0004-0005, 0013-0014]).
Regarding claim 3, Chiu discloses the limitations of claim 2 as detailed above and further discloses that each of the first and second memory cells includes a bit line transistor (FIG. 2, pass gate PG-1 functions as a bit line transistor in each memory cell ¶ [0030]), a complementary bit line transistor (FIG. 2, pass gate PG-2 functions as a complementary bit line transistor in each memory cell ¶ [0030]) and two inverters (FIG. 2, two inverters are present in the center of each memory cell’s circuit structure ¶ [0030]).
Regarding claim 5, Chiu discloses the limitations of claim 1 as detailed above, and further discloses that the first bit line metal line is a frontside metal line (FIG. 9B, bit line BL in cell 104B is formed in metal line 722A2, which is a frontside metal line ¶ [0049]) on an upper surface of a substrate (FIG. 9B, substrate 702 is below metal line 722A2 ¶ [0045-0049]) in which the plurality of memory cells are formed, and the second bit line metal line is a backside metal line (FIG. 9B, bit line in cell 104A is formed in metal line 722A, which is a backside metal line ¶ [0048]) on a lower surface of the substrate opposite the upper surface of the substrate (FIG. 9B, substrate 702 is above metal line 722A ¶ [0045-0049]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over a second/alternative interpretation of the disclosure of US patent publication US 20210343332 (Chiu et al hereinafter Chiu).
Chiu discloses a memory device (the device of FIGS. 1-2, 9A-9B ¶ [0004-0005, 0013-0014, 0047-0048]), comprising: a memory cell array (FIG. 1, array 102 of memory cells 104 ¶ [0028]) including a plurality of memory cells (FIGS. 1-2, memory cells 104 ¶ [0028]) arranged in a plurality of columns and rows (FIG. 1, rows and columns of memory cells are arranged along X and Y directions ¶ [0028]).
Further, FIG. 1 illustrates that the bit cells 104 are arranged in a grid and describes that the embodiment of FIGS. 9A-9B is applicable to bit cells 104 (¶ [0047]). While the FIGS.9A-9B embodiment only explicitly illustrates one instance of each of bit cells 104A and 104B, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to arrange a column of bit cells as indicated in the annotated version of FIG. 9A below, wherein multiple instances of bit cells 104A and 104B are arranged along the same columns, in order to make use of the asymmetrical frontside-backside connections to arrive at favorable coupling and parasitic capacitance levels in the device (¶ [0047, 0051]). A person of ordinary skill in the art before the effective filing date of the claimed invention would therefore have found it obvious to employ this configuration at each row and column of the memory cell array.
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Having done so, the memory device is further including first and second memory cells (annotated FIG. 9A above, two instances of memory cell 104B are first and second memory cells) in a same column and different rows (in this interpretation, columns run along the X direction and rows run along the Y direction of FIG. 9A), the plurality of columns intersecting the plurality of rows in a plan view (FIG. 9A is a plan view where the X and Y directions intersect ¶ [0013]); a first bit line transistor (FIG. 9A, first instance of bit cell 104B may have a circuit according to cell 104 of FIG. 2 which includes transistor PG-1 ¶ [0030, 0049]) electrically connected between the first memory cell and a first bit line metal line (FIG. 2, bit-line BL is located on a side of transistor PG-1 away from the rest of the memory cell ¶ [0032]); and a second bit line transistor (FIG. 9A, second instance of bit cell 104B may have a circuit according to cell 104 of FIG. 2 which includes transistor PG-2 ¶ [0030, 0049]) electrically connected between the second memory cell and a second bit line metal line (FIG. 2, complementary bit-line BLB is located on a side of transistor PG-2 away from the rest of the memory cell ¶ [0032]), wherein the first bit line metal line is on an upper surface of the memory cell array (FIG. 9B, first instance of memory cell 104B has bit-line BL on an upper surface of its device portion along the Z direction ¶ [0049]), and the second bit line metal line is on a lower surface of the memory cell array opposite the upper surface of the memory cell array (FIG. 9B, second instance of memory cell 104B has complementary bit-line BLB on a lower surface of its device portion along the Z direction ¶ [0049]).
Claims 4 and 6-8 are rejected under 35 U.S.C. 103 as being unpatentable over the second/alternative interpretation Chiu as applied to claim 1 above, and further in view of US patent publication US 20190080736 A1 (Baeck et al hereinafter Baeck).
Regarding claim 4, Chiu discloses the limitations of claim 1 as detailed regarding the second/alternative interpretation above, and further discloses that each of the plurality of columns in the memory cell array includes a plurality of sub-groups (annotated Chiu FIG. 9A above, a given column may include sub-groups which include the upper instance of cell 104B as part of one sub-group, and the lower instance of cell 104B as part of another sub-group). Chiu does not explicitly teach a first sub-group of the plurality of sub-groups is electrically connected to a sense amplifier after the first memory cell is disposed in a first direction from an uppermost word line to a lowest word line in at least one of first column and then the second memory cell is disposed, a second sub-group of the plurality of sub-groups is electrically connected to the sense amplifier after the second memory cell is disposed in the first direction in at least one of second column and then the second memory cell is disposed, and the first column of the first sub-group and the second column of the second sub-group are alternately disposed in a second direction intersecting the first direction, the first and second directions being parallel to the upper surface of the memory cell array, a configuration of sense amplifiers not being taught in Chiu.
However, Baeck discloses a memory cell array (FIG. 2, memory cell array 110 ¶ [0034]) which connects to a column decoder (FIG. 2, column decoder 190 ¶ [0040]) through bit lines (FIG. 2, bit lines BL ¶ [0069]), and the column decoder may include a plurality of sense amplifiers (non-illustrated sense amplifiers at each column ¶ [0046, 0073]) which sense and amplify data read by the memory cell array. Further, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to include a sense amplifier at each of the plurality of columns, in order to connect each bit line to a sense amplifier that can improve the signal strength of the memory cell and increase its reliability in operation.
Chiu and Baeck both pertain to the field of memory devices, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Chiu in view of Baeck to include a sense amplifier at each of the plurality of columns, in order to connect each bit line to a sense amplifier that can improve the signal strength of the memory cell and increase its reliability in operation.
Having done so, Chiu in view of Baeck further discloses a first sub-group (annotated Chiu FIG. 9A, a first sub-group may include the upper instance of cell 104B as part of its sub-group) of the plurality of sub-groups is electrically connected to a sense amplifier (Baeck ¶ [0046-0073], sense amplifiers are present at each column to electrically connect to the bit lines and by extension each of bit cells 104B) after the first memory cell is disposed (the first memory cell 104B of Chiu is at some point disposed in the device) in a first direction (Chiu FIG. 9A, the X direction) from an uppermost word line to a lowest word line (Chiu FIGS. 2 and 9A-9B, word lines WL and WLB extend along a direction orthogonal to that of the bit lines BL and BLB, and are separated from one another along the X direction; a separation between uppermost and lowest word lines along the X direction are considered to define a direction parallel to the X direction ¶ [0028-0029]) in at least one of first column (a “first column” is considered to be the portion of the column that includes the “first sub-group”) and then the second memory cell is disposed (the second memory cell 104B of Chiu is at some point disposed in the device), a second sub-group (annotated Chiu FIG. 9A, a second sub-group may include a lower instance of cell 104B as part of its sub-group in a separate column from the first) of the plurality of sub-groups is electrically connected to the sense amplifier (Baeck ¶ [0046-0073], sense amplifiers are present at each column to electrically connect to the bit lines and by extension each of bit cells 104B) after the second memory cell is disposed (the second memory cell 104B of Chiu is at some point disposed in the device) in the first direction in at least one of second column (a “second column” is considered to be the portion of the column that includes the “second sub-group”, and may be in a separate overall column as the claimed “first column”) and then the second memory cell is disposed (the second memory cell 104B of Chiu is at some point disposed in the device), and the first column of the first sub-group and the second column of the second sub-group are alternately disposed in a second direction intersecting the first direction (Chiu FIGS. 2 and annotated 9A, different instances of columns having memory cells 104B are arranged in the device along the Y direction as indicated regarding the analysis claim 1 of the second/alternative interpretation), the first and second directions being parallel to the upper surface of the memory cell array (in the context of the present interpretation of the disclosure of Chiu, the X and Y directions are both parallel to the upper surface of the memory cell array).
Regarding claim 6, Chiu in view of Baeck discloses the limitations of claim 4 as detailed above, and further discloses a direct backside contact between an upper surface of the second bit line metal line and a lower surface of a source/drain metal of the second bit line transistor to electrically connect the second bit line metal line with the source/drain metal of the second bit line transistor (Chiu FIG. 2 shows bit line transistor PG-2 having a source/drain connection to complementary bit line BLB ¶ [0030], and FIG. 9B shows a direct backside contact bit line via between complementary bit line BLB and the left-side device of bit cell 104B ¶ [0049]).
Regarding claim 7, Chiu in view of Baeck discloses the limitations of claim 4 as detailed above, and further discloses a bit line via between a lower surface of the first bit line metal line and an upper surface of a source/drain metal of the first bit line transistor to electrically connect the first bit line metal with the source/drain metal of the first bit line transistor (Chiu FIG. 2 shows bit line transistor PG-1 having a source/drain connection to bit line BL ¶ [0030], and FIG. 9B shows a contact bit line via between lower surface of bit line BL and the upper surface of right-side device of bit cell 104B ¶ [0049]).
Regarding claim 8, Chiu discloses the limitations of claim 1 as detailed regarding the second/alternative interpretation above, but does not explicitly disclose that the first bit line metal line and the second bit line metal line are respectively connected to sense amplifiers of a same column of the plurality of columns.
However, Baeck discloses a memory cell array (FIG. 2, memory cell array 110 ¶ [0034]) which connects to a column decoder (FIG. 2, column decoder 190 ¶ [0040]) through bit lines (FIG. 2, bit lines BL ¶ [0069]), and the column decoder may include a plurality of sense amplifiers (non-illustrated sense amplifiers at each column ¶ [0046, 0073]) which sense and amplify data read by the memory cell array. Further, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to include a sense amplifier at each of the plurality of columns, such that the first bit line metal line and the second bit line metal line are respectively connected to sense amplifiers of a same column of the plurality of columns, in order to connect each bit line to a sense amplifier that can improve the signal strength of the memory cell and increase its reliability in operation.
Chiu and Baeck both pertain to the field of memory devices, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Chiu in view of Baeck to include sense amplifiers such that the first bit line metal line and the second bit line metal line are respectively connected to sense amplifiers of a same column of the plurality of columns, in order to connect each bit line to a sense amplifier that can improve the signal strength of the memory cell and increase its reliability in operation.
Claims 9-14 are rejected under 35 U.S.C. 103 as being unpatentable over US patent publications US 20240251541 A1 (Chung et al hereinafter Chung) in view of US 20120195106 A1 (Wang et al hereinafter Wang).
Regarding claim 9, Chung discloses a memory device (the device of FIG. 1, which is further detailed in FIGS. 2A-3E ¶ [0035, 0071-0074]), comprising: a pair of first bit line metal lines (FIG. 1, bit lines BLL/BLBL, which may be located at a lowermost backside metal layer ¶ [0029]) at a first metal level; a memory cell array (FIG. 1, memory cells 110 in memory array 100A ¶ [0021]) on a substrate (FIGS. 2B and 3B-3C, a substrate is present but not shown around active areas A1 and A2 above the backside bit lines BLBS/BLBBS ¶ [0047, 0061]) above the first metal level, the memory cell array including first and second memory cells (FIG. 1, one memory cell 110 in each of the subsets 100AL and 100AU in a same column 100C may be the first and second memory cells ¶ [0025]) in a same column; first and second power supply metal lines (FIGS. 2A-2B and 3D-3E, reference voltage nodes VSS function in a capacity of supplying power, and are located in the frontside above the substrate ¶ [0058]) and a pair of second bit line metal lines (FIG. 1, bit lines BLU/BLBU, which may be located at an uppermost frontside metal layer above the substrate ¶ [0028]) at a second metal level above the substrate; wherein the first memory cell is connected to the pair of first bit line metal lines (FIG. 1, a memory cell 110 in subset 100AL may be the first memory cell which connects to bit lines BLL/BLBL), and the second memory cell is connected to the pair of second bit line metal lines (FIG. 1, a memory cell 110 in subset 100AU may be the second memory cell which connects to bit lines BLU/BLBU). Chung does not explicitly disclose a sense amplifier in the substrate and electrically connected to the pair of first bit line metal lines and the pair of second bit line metal lines, thought Chung does disclose I/O circuits at the ends of the columns of memory cells (FIG. 1, MIO ¶ [0022]) and formed in substrate 100B.
However, Wang discloses a memory device wherein a sense amplifier (FIG. 1, sense amplifier ¶ [0034-0035]) is located in a substrate (¶ [0034-0035]) and is electrically connected to bit line pairs in a given column (FIG. 1, bit lines B/L, B/L_ ¶ [0034-0035]). Further, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to include a sense amplifier at each of the plurality of columns, such that a sense amplifier is in the substrate and electrically connected to the pair of first bit line metal lines and the pair of second bit line metal lines, in order to connect each bit line to a sense amplifier that can improve the signal strength of the memory cell and increase its reliability in operation.
Chung and Wang both pertain to the field of memory devices, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Chung in view of Wang such that a sense amplifier is in the substrate and electrically connected to the pair of first bit line metal lines and the pair of second bit line metal lines, in order to connect each bit line to a sense amplifier that can improve the signal strength of the memory cell and increase its reliability in operation.
Regarding claim 10, Chung in view of Wang discloses the limitations of claim 9 as detailed above, and Chung further discloses that each of the first and second memory cells is a static random access memory that includes a bit line transistor, a complementary bit line transistor and two inverters (Chung FIG. 2A, each instance of memory cell 110 includes the circuit structure of memory cell 200, which includes transistors N1, N4, and two cross-coupled inverters ¶ [0040-0041]).
Regarding claim 11, Chung in view of Wang discloses the limitations of claim 10 as detailed above, and Chung further discloses that the second memory cell (a memory cell in the 100AU subset) includes a first bit line via (FIGS. 3A and 3D, via structure V3 ¶ [0046]) between a lower surface of the second bit line metal line and an upper surface of a source/drain metal of the bit line transistor of the second memory cell (FIG. 3D, via V3 is between lower surface of frontside bit line BLFS and transistor N1) to electrically connect the second memory cell to the second bit line metal line (the circuit of FIG. 2A illustrates that transistor N1 has a source/drain that electrically connects to bit line BL).
Regarding claim 12, Chung in view of Wang discloses the limitations of claim 11 as detailed above, and Chung further discloses that the second memory cell (a memory cell in the 100AU subset) includes a second bit line via (FIG. 3A and 3E, via structure V4 ¶ [0046]) between a lower surface of a second complementary bit line metal line (FIG. 3E, bit line BLBFS is a complementary bit line where via V4 is below its lower surface) and an upper surface of a source/drain metal of the complementary bit line transistor of the second memory cell (FIG. 3E, via V4 is above transistor N4) to electrically connect the second memory cell to the second complementary bit line metal line (the circuit of FIG. 2A illustrates that transistor N4 has a source/drain that electrically connects to complementary bit line BLB).
Regarding claim 13, Chung in view of Wang discloses the limitations of claim 10 as detailed above, and Chung further discloses that the first memory cell includes a first direct backside contact (FIGS. 3A-3B, via V3 which connects to backside bit line BLBS in subset 100AL ¶ [0046]) between an upper surface of a first bit line metal line (FIG. 3B, backside bit line BLBS upper surface ¶ [0059]) and a lower surface of a source/drain metal of the bit line transistor of the first memory cell (FIGS. 2B and 3B, transistor N1 of the memory cell in the 100AL region is above via V3 ¶ [0041]) to electrically connect the first bit line metal line with the source/drain metal of the bit line transistor of the first memory cell (FIGS. 2B and 3B, transistor N1 is electrically connected to backside bit line BL/BLBS).
Regarding claim 14, Chung in view of Wang discloses the limitations of claim 13 as detailed above, and Chung further discloses that the first memory cell includes a second direct backside contact (FIGS. 3A and 3C, via structure V4 below MD4 ¶ [0046]) between an upper surface of a second complementary bit line metal line (FIGS. 2A and 3C, backside bit line BLBBS, the upper surface of which is below via V4 ¶ [0059]) and a lower surface of a source/drain metal of the complementary bit line transistor of the second memory cell (FIGS. 2B and 3B, transistor N4 of the memory cell is above via V4 ¶ [0041]; the first memory cell is found applicable here in view of the discussion of this claim regarding 35 U.S.C. 112(b) above) to electrically connect the second complementary bit line metal line with the source/drain metal of the complementary bit line transistor of the second memory cell (FIGS. 2B and 3B, transistor N4 is electrically connected to backside complementary bit line BLB/BLBBS).
Claims 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chung in view of US patent publication US 20240257867 A1 (You et al hereinafter You).
Regarding claim 15, Chung discloses a memory device (the device of FIG. 1, which is further detailed in FIGS. 2A-3E ¶ [0035, 0071-0074]), comprising: a memory cell array (FIG. 1, memory cells 110 in memory array 100A ¶ [0021]) including a plurality of memory cells (cells 110) in a substrate (FIGS. 2B and 3B-3C, a substrate is present but not shown around active areas A1 and A2 ¶ [0047, 0061]); a pair of first bit line metal lines (FIG. 1, bit lines BLL/BLBL, which may be located at a lowermost backside metal layer ¶ [0029]; backside bit lines BLBS/BLBBS of FIG. 2B illustrate such an embodiment) spaced apart from each other in a second direction (FIG. 2B, backside bit lines BLBS/BLBBS are spaced apart along the Y direction) at a lower metal level (FIGS. 3B-3C, bit lines BLBS/BLBBS on metal segments S3/S4 are below the substrate ¶ [0046]) below the substrate in a third direction (FIGS. 3B-3C, the Z direction) and extending in a first direction (FIGS. 3A-3C, the X direction), the first and second directions intersecting one another and being parallel to an upper surface of the substrate, and the third direction being perpendicular to the upper surface of the substrate and to the first and second directions (FIGS. 2B-3E, the XYZ directions intersect as claimed ¶ [0020, 0073]); a first power supply metal line (FIGS. 2A-2B, reference voltage line VSS in metal segment S1 connecting at N2 transistor of a given memory cell 200 functions in the capacity of supplying power ¶ [0037]) extending in the first direction (FIG. 3E, voltage line VSS in metal segment S1 extends along the X direction) at a first upper metal level (FIG. 3E, metal segment S1 is above the substrate along the Z direction ¶ [0046, 0062]) above the substrate in the third direction; a pair of second power supply metal lines (FIGS. 2A-2B, reference voltage line VSS in metal segment S6 connecting at N3 transistor in a neighboring memory cell 200, and a reference voltage line VSS in metal segment S1 connecting at N2 transistor of the neighboring memory cell 200 function in the capacity of supplying power ¶ [0037]) spaced apart from the pair of first power supply metal lines in the second direction (FIG. 2B, voltage lines VSS in metal segments, S1 of the given cell 200 and the S1 and S6 segments of the neighboring cell 200 are separated along the Y direction and located at the frontside FS, extending along the X direction ¶ [0058]) at the first upper metal level and extending in the first direction; a pair of lower word line metal lines (FIGS. 2A-2B, the gates G1 and G4 of transistors N1 and N4 and connect to metal segments S2 and S5, which are word line metal lines ¶ [0046]) spaced apart from the pair of second power supply metal lines in the second direction on a first directional axis the same as that of the pair of second power supply metal lines (FIG. 2B, VSS segments S1 and S6 are spaced apart from word line segments S2 and S5 in a manner matching the configuration illustrated in present application’s FIGS. 10 and 12, and are therefore found to meet this limitation on that basis) at the first upper metal level (metal segments S1, S2, S5, and S6 are at the same frontside FS level ¶ [0058]); a pair of second bit line metal lines (FIG. 1, bit lines BLU/BLBU, which may be located at an uppermost frontside metal layer above the substrate ¶ [0028]; frontside bit lines BLFS/BLBFS of FIG. 2B illustrate such an embodiment) between each of the pair of second power supply metal lines and the first power supply metal line (FIGS. 2B, 3B, 3C, bit lines BLFS and BLBFS of segments S3 and S4 are between voltage lines VSS at segments S1 and S6 along the Y direction) at the first upper metal level (FIGS. 2B, 3B, 3C, bit lines BLFS and BLBFS of segments S3 and S4 are in the frontside FS metal level) and extending in the first direction (FIGS. 3B-3C, bit lines BLFS and BLBFS extend along the X direction).
Chung does not explicitly show a plurality of upper word line metal lines extending in the second direction at a second upper metal level above the first upper metal level in the third direction. Chung does however illustrate in FIG. 1 that the word lines WL extend lengthwise along the Y direction perpendicular to the various bit lines BLL/BLU/BLBL/BLBU extending lengthwise along the X direction, connecting to the word line driver (FIG. 1, WLD ¶ [0022]).
Furthermore, You discloses a memory device (the device of FIGS. 1-2E ¶ [0004-0008]) which includes a plurality of upper word line metal lines (FIG. 2A, word lines WL) extending in the second direction (FIG. 2A, the y direction) at a second upper metal level (FIG. 2A, word lines WL are formed at an upper level of frontside interconnect structure 206 ¶ [0035]) above the first upper metal level (FIG. 2A, bit lines BL/BLB are located in a metal lower comparatively lower than word line WL) in the third direction (FIG. 2A the z direction). You also shows that a pair of lower wordlines (FIG. 2A, unlabeled metal line segments between word line WL and word line contact N4WL ¶ [0040]) may be connected to the upper wordline through a contact structure, which allows the word lines WL to be oriented perpendicular to the bit lines, allowing for the indicated configuration of Chung wherein word lines and bit lines extend at perpendicular directions (Chung FIG. 1, ¶ [0022]).
Chung and You both pertain to the field of memory devices, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Chung in view of You to include a plurality of upper word line metal lines extending in the second direction at a second upper metal level above the first upper metal level in the third direction, in order to arrange the bit lines and word lines along perpendicular directions as was indicated in the disclosure of Chung, making effective use of space in the device to allow the word lines to connect to the word line driver.
Regarding claim 16, Chung in view of You discloses the limitations of claim 15 as detailed above, and Chung further discloses that each of the plurality of memory cells is a static random access memory (FIG. 2A, memory cells 200 are SRAM ¶ [0021]) that includes a bit line transistor (FIG. 2A, transistor N1 functions as a bit line transistor ¶ [0039]), a complementary bit line transistor (FIG. 2A, transistor N4 functions as a complementary bit line transistor ¶ [0039]) and two inverters (FIG. 2A, memory cell 200 includes cross-coupled inverters ¶ [0040]).
Regarding claim 17, Chung in view of You discloses the limitations of claim 15 as detailed above, and Chung further discloses that a first memory cell (FIG. 1, a memory cell 110 in subset 100AL ¶ [0025]) and a second memory cell (FIG. 1, a memory cell 110 in subset 100AU ¶ [0025]) of the plurality of memory cells are included in one column (FIG. 1, the left of the two illustrated columns 100C includes the first and second memory cells ¶ [0025]) of the plurality of memory cells, the first memory cell is electrically connected to the pair of first bit line metal lines (FIGS. 3A-3C, a memory cell in the 100AL subset is electrically connected to backside bit lines BLBS/BLBBS at segments S3 and S4) and a pair of first lower word line metal lines (FIGS. 2A-3A, the gates G1 and G4 of transistors N1 and N4 connect to metal segments S2 and S5, which are word line metal lines in a memory cell in the 100AL subset ¶ [0046]), and the second memory cell is electrically connected to the pair of second bit line metal lines (FIGS. 3A-3C, a memory cell in the 100AU subset is electrically connected to frontside bit lines BLFS/BLBFS at segments S3 and S4) and a pair of second lower word line metal lines (FIGS. 2A-3A, the gates G1 and G4 of transistors N1 and N4 connect to metal segments S2 and S5, which are word line metal lines in a memory cell in the 100AU subset ¶ [0046]).
Regarding claim 18, Chung in view of You discloses the limitations of claim 17 as detailed above, and Chung further discloses a direct backside contact (FIGS. 3A-3C, backside via structures V3 and V4 form direct backside contacts between upper surfaces of bit line BLBS/BLBBS segments S3 and S4 and lower surfaces of S/D regions of transistors N1 and N4 ¶ [0046]; see also FIG. 2A circuit diagram) between an upper surface of the pair of first bit line metal lines and a lower surface of a source/drain metal of the bit line transistor and the complementary bit line transistor of the first memory cell, and the first memory cell is electrically connected to the pair of first bit line metal lines (FIG. 2A illustrates the electrical connection with the circuit diagram, and FIGS. 3B and 3C illustrate vias V3 and V4 connecting bit line segments BLBS/BLBBS to the transistors N1 and N4).
Regarding claim 19, Chung in view of You discloses the limitations of claim 18 as detailed above, and Chung further discloses that the first memory cell further includes a pair of first lower word line metal lines (FIGS. 2A-3A, the gates G1 and G4 of transistors N1 and N4 connect to metal segments S2 and S5, which are word line metal lines in a memory cell in the 100AL subset ¶ [0046]) extending in the first direction along a first axis the same as that of the pair of first power supply metal lines at the first upper metal level (FIG. 2B, metal segments S2 and S5 of the word lines extend along the X direction with voltage lines VSS segments S1 and S6 while being at the frontside FS level ¶ [0046]), electrically connecting respective gate electrodes of the bit line transistor and the complementary bit line transistor of the second memory cell with a second upper word line metal line (FIG. 2A, as can be seen in the circuit diagram, transistors N1 and N4 include gates electrodes which connect to the word lines).
Regarding claim 20, Chung in view of You discloses the limitations of claim 17 as detailed above, and Chung further discloses a bit line via (FIGS. 3A-3C, frontside via structures V3 and V4 form frontside contacts between upper surfaces of bit line BLFS/BLBFS segments S3 and S4 and upper surfaces of S/D regions of transistors N1 and N4 ¶ [0046]; see also FIG. 2A circuit diagram) between a lower surface of the pair of second bit line metal lines and an upper surface of a source/drain metal of each of the bit line transistor and the complementary bit line transistor of the second memory cell, wherein the second memory cell is electrically connected to the pair of second bit line metal lines through the bit line via (FIG. 2A illustrates the electrical connection with the circuit diagram, and FIGS. 3B and 3C illustrate vias V3 and V4 connecting bit line segments BLFS/BLBFS to the transistors N1 and N4).
Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US patent publications US 20230333742 A1, US 20200243486 A1, US 20200168616 A1, and US 20130170275 A1.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWARD RHETT CHEEK whose telephone number is (571)272-3461. The examiner can normally be reached Monday - Thursday 7:30am - 5pm, Every other Friday 8:30am - 5pm.
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/E.R.C./Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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