DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant’s amendment filed 05/11/2026 which has
been entered and made of record. Claims 1-3, 6-7, 9, 11-14, 17-19 and 21-22 have been amended. No claims have been newly added or cancelled. Claims 1-3, 6-9, 11-14, 17-19 and 21-22 are pending in the application.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-3, 6-9, 11-14, 17-19 and 21-22 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument (due to applicant’s arguments directed to newly amend limitation(s) which is addressed by new prior art presented in this Office Action).
Claim Rejections - 35 USC § 112
Previous 35 U.S.C. 112(b) rejection for claims 5-7, 10-11, 16-17 and 20-21 have been withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 6, 8-9, 11-12, 17, 19 and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over DOYLE et al. (U.S. Patent Application Publication No. 2023/0377247), hereinafter referenced as DOYLE, in view of Hakura (U.S. Patent Application Publication No. 2014/0118393 A1), hereinafter referenced as Hakura, Muthler (U.S. Patent Application Publication No. 2020/0050550), hereinafter referenced as Muthler, and Allgyer (Real-time Ray Tracing using CUDA), hereinafter referenced as Allgyer.
Regarding claim 1, DOYLE teaches A method of operating a tile-based graphics processing system or graphics processor (paragraph 111 teaches “compute engine cluster 332 can include a set of compute engine tiles 340A-340D that include execution logic that is optimized for parallel or vector-based general-purpose compute operation”); this shows operations would be of tile-based graphics processing system; the method comprising: generating bounding box hierarchy information representative of a hierarchy of bounding boxes representing positions of primitives of a set of primitives to be processed to generate a render output; (paragraph 482 teaches "a BVH builder to determine coordinates of child nodes of the first BVH node by performing non-spatial-split binning or spatial-split binning for the first BVH node using primitives associated with the first BVH node"); primitives associated with first node (of BVH[bounding volume/block hierarchy]) acts as a set since it contains multiple primitives, and binning for such shows bounding box information must be generated (alongside positions due to mention of determining coordinates) and kept for each primitive of set of primitives, and this is all done for the rendering output objective described in abstract and mentioned above; and storing the bounding box hierarchy information in a set of one or more blocks of memory space for use (paragraph 126 teaches “Each execution unit in execution units 508A-508N operates on arrays of data elements”); this shows array (block of memory) for storing the aforementioned BVH information, and one of ordinary skill in the art would understand that the binning previously mentioned is also putting data in memory blocks.
However, DOYLE fails to teach for use to identify primitives of the set of primitives to process to generate a rendering tile of the render output;
However, Hakura teaches for use to identify primitives of the set of primitives to process to generate a rendering tile of the render output (Hakura, fig. 8, step 850 and paragraph 107 teaches "If an additional accumulated bounding box is not received, then the tiling unit 375 begins the process of tiled rendering at step 850 by identifying a cache tile 410 for which the accumulated bounding boxes and graphics primitives currently stored in the buffer memory are to be processed." and paragraph 109 teaches "after each cache tile 410 has been processed with respect to the current tiled rendering pass, the results stored in the array may be cleared, and, at step 810, the next batch of accumulated bounding boxes and graphics primitives may be received by the tiling unit 375 and stored in the buffer memory."); this marks beginning of the tile rendering process, comes after reading and using the bounding box of step 810 of fig. 8, also it identifies primitives using the tiling unit and then identifies/generates a cache tile which is a rendering tile of the render output since used in tiled rendering process. Hakura is considered to be analogous art because it is reasonably pertinent to the problem faced by the inventor of rendering tile techniques using bounding box information and primitive. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify DOYLE's invention with the bounding box and primitive for rendering tiles techniques of Hakura to ensure the technique improves cache memory locality during processing in the screen space pipeline, where multiple memory operations associated with a first cache tile access a region of the L2 caches, or any other technically feasible cache memory, that may stay resident during screen space processing of the first cache tile (Hakura, paragraph 67). This means better and more efficient memory usage due to rendering tile generated by using bounding box information to identify primitives.
However, the combination of DOYLE and Hakura fails to explicitly teach
wherein storing the bounding box hierarchy information in the set of one or more blocks of memory space comprises: storing first information representative of a first bounding box of a lower level of the hierarchy of bounding boxes in a first location in a block of memory space of the set of one or more blocks of memory space
However, Muthler teaches wherein storing the bounding box hierarchy information in the set of one or more blocks of memory space comprises: storing first information representative of a first bounding box of a lower level of the hierarchy of bounding boxes in a first location in a block of memory space of the set of one or more blocks of memory space (Muthler, paragraph 113 teaches "FIGS. 8A and 8B show a recursively-subdivided bounding volume of a 3D scene (FIG. 8A) and a corresponding tree data structure (FIG. 8B) that may be accessed by the traversal coprocessor 138 and used for hardware-accelerated operations performed by traversal coprocessor. The division of the bounding volumes may be represented in a hierarchical tree data structure with the large bounding volume shown in FIG. 2B represented by a parent node of the tree and the smaller bounding volumes represented by children nodes of the tree that are contained by the parent node"); corresponding data structure in fig. 8B for bounding volumes shows levels of hierarchy with each level being a node meaning that each level inclusive of lower level of hierarchy of the bounding volume is stored in a respective (lower level stored in first when viewed in combination with Allgyer below) location in block of memory space; Muthler is considered to be analogous art because it is reasonably pertinent to the problem faced by the inventor of levels of the hierarchy of bounding boxes and data structure relations to such. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify , the combination of DOYLE and Hakura with the bounding box in relation to data structure techniques of Muthler to ensure an improved hardware-based scheduling cache memory for ray tracing bounding volume hierarchy traversal and other performance and/or memory management enhancements (Muthler, paragraph 8). This would be from the data structure's efficient management of the levels of the hierarchy of bounding boxes.
However, the combination of DOYLE, Hakura, and Muthler fails to explicitly teach determining, based on the first location, one or more further locations in the same block of memory space of the set of one or more blocks of memory space for storing further information representative of one or more related bounding boxes of one or more higher levels of the hierarchy of bounding boxes that bound the first bounding box; and
storing the further information representative of one or more related bounding boxes of one or more higher levels of the hierarchy of bounding boxes that bound the first bounding box in the determined one or more further locations in the same block of memory space of the set of one or more blocks of memory space;
However, Allgyer explicitly teaches determining, based on the first location, one or more further locations in the same block of memory space of the set of one or more blocks of memory space for storing further information representative of one or more related bounding boxes of one or more higher levels of the hierarchy of bounding boxes that bound the first bounding box (Allgyer, page 24, second paragraph teaches “so the arrays described above must be of fixed size. This means a maximum size had to be chosen and the arrays are always given this size… maximum size could be modified to allow for larger scenes, however”); maximum size modified shows further location in same block/array of memory space of the set of one or more blocks of memory space, this is for storing related bounding box further information (hence the size increase), and this would be for higher levels of the hierarchy of bounding boxes that bound the first bounding box when using the following Allgyer, page 21, second paragraph explanation/citation from below; and
storing the further information representative of one or more related bounding boxes of one or more higher levels of the hierarchy of bounding boxes that bound the first bounding box in the determined one or more further locations in the same block of memory space of the set of one or more blocks of memory space;
(Allgyer, page 21, second paragraph teaches “The upshot of this is BoundingVolume contains pointers to matrices and children. This means I need to recursively write this data to GPU memory. To do this, I recurse down to the deepest leaf first, copy that node to the GPU memory, use that pointer for its parent, copy the parent, and so on.”); this shows if deepest level first is stored then the next ones (further information representative of one or more related bounding boxes) would be higher levels of hierarchy bounding box that bound the first/deepest/lower bounding box (which are stored in further locations of same block of memory space of the aforementioned set of blocks of memory space as explained above). Allgyer is considered to be analogous art because it is reasonably pertinent to the problem faced by the inventor of memory allocation and specific ordering of storing/reading information. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of DOYLE, Hakura, and Muthler with the locations in memory block(s) and ordering the storing/reading of BVH techniques of Allgyer to ensure GPU is very efficient at performing the same operations on many sets of data, while the CPU is good at recursion and handling complex data structures (Allgyer, page 10, third paragraph). This means a more efficient system overall.
Regarding claim 8, the non-transitory computer readable storage claim 8 recites similar limitations as method claim 1, and thus is rejected under similar rationale. In addition, DOYLE, paragraph 511 teaches " software instructions stored in memory embodied in a non-transitory computer readable medium. Thus, the techniques shown in the figures can be implemented using code and data stored and executed on one or more electronic devices".
Regarding claim 9, DOYLE teaches A method of operating a tile-based graphics processing system or graphics processor (paragraph 111 teaches “compute engine cluster 332 can include a set of compute engine tiles 340A-340D that include execution logic that is optimized for parallel or vector-based general-purpose compute operation”); this shows operations would be of tile-based graphics processing system; the method comprising: generating bounding box hierarchy information representative of a hierarchy of bounding boxes representing positions of primitives of a set of primitives to be processed to generate a render output;
reading, from a set of one or more blocks of memory space, (paragraph 126 teaches “Each execution unit in execution units 508A-508N operates on arrays of data elements”); this shows array (block of memory) for storing the following BVH information, and one of ordinary skill in the art would understand that the binning mentioned is abstract also putting data (to be read) in memory blocks; reading…bounding box hierarchy information representative of a hierarchy of bounding boxes representing positions of primitives of a set of primitives to be processed to generate the render output; (paragraph 482 teaches "a BVH builder to determine coordinates of child nodes of the first BVH node by performing non-spatial-split binning or spatial-split binning for the first BVH node using primitives associated with the first BVH node"); primitives associated with first node (of BVH[bounding volume/block hierarchy]) acts as a set since it contains multiple primitives, and binning for such shows bounding box information must be generated (alongside positions due to mention of determining coordinates) and kept for each primitive of set of primitives, and this is all done for the rendering output objective described in abstract and mentioned above; and
reading the further information representative of one or more related bounding boxes of one or more lower levels of the hierarchy of bounding boxes that the first bounding box bounds from the determined one or more further locations in the same block of memory space of the set of one or more blocks of memory space (paragraph 126 teaches “Each execution unit in execution units 508A-508N operates on arrays of data elements”, paragraph 347 teaches “produce a reduced-precision top-down BVH builder” and paragraph 482 teaches “a geometry quantizer to read vertices of the primitives at the first precision and to adaptively quantize the vertices of the primitives to a second precision associated with a first local coordinate grid of a first BVH node positioned within a global coordinate grid, the second precision lower than the first precision”); this shows array (block of memory) for storing the aforementioned BVH information (thus this is from the determined one or more further locations in the same block of memory space of the set of one or more blocks of memory space from the combination below), information stored (including the further information of mentioned lower level [second-precision] primitives) is to be read, and top-down BVH here also shows further information representing lower levels of the hierarchy of bounding boxes that the first bounding box bounds from.
However, DOYLE fails to teach generating a rendering tile of a render output by: using the bounding box hierarchy information to identify primitives of the set of primitives to process to generate the rendering tile; and
processing the identified primitives to generate the rendering tile;
However, Hakura teaches generating a rendering tile of a render output by:
(Hakura, paragraph 66 teaches “screen space is divided into cache tiles, where each cache tile is associated with a portion of the screen space” and abstract teaches “ identifying a first cache tile associated with a render surface”); cache tile is associated with rendering thus is considered rendering tile of a render output (since also used for display/screen space); using the bounding box hierarchy information to identify primitives of the set of primitives to process to generate the rendering tile; (Hakura, paragraph 65 teaches "The VPC 370 performs clipping, culling, and viewport transform to determine which graphics primitives are potentially viewable in the final rendered image and which graphics primitives are not potentially viewable. The VPC 370 then transmits processed graphics primitives and their associated bounding boxes to a bounding box (BB) unit 372. The bounding box unit 372 combines the bounding boxes to generate one or more accumulated bounding boxes." and fig. 5 teaches the steps for generating accumulated bounding boxes starting at step 510 which teaches "receive graphics primitive and/or bounding box"); graphics primitives that are potentially viewable are identified because they would be processed to generate rendering tiles since viewable and this is done by traversing respective hierarchy or bounding box (thus using bounding box information) due to the fig. 5 saying it can also receive a bounding box alongside the graphics primitive and this step looping after "yes" in step 580; and processing any identified primitives to generate the rendering tile (Hakura, paragraph 66 teaches "Graphics primitives are processed in the world space pipeline 352 and then transmitted to the tiling unit 375. The screen space is divided into cache tiles, where each cache tile is associated with a portion of the screen space. For each graphics primitive, the tiling unit 375 identifies the set of cache tiles that intersect with the graphics primitive, a process referred to herein as "tiling."); this shows processing the aforementioned primitives to generate the rendering tile/cache tiles. Hakura is considered to be analogous art because it is reasonably pertinent to the problem faced by the inventor of rendering tile techniques using bounding box information and primitive. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify DOYLE's invention with the bounding box and primitive for rendering tiles techniques of Hakura to ensure the technique improves cache memory locality during processing in the screen space pipeline, where multiple memory operations associated with a first cache tile access a region of the L2 caches, or any other technically feasible cache memory, that may stay resident during screen space processing of the first cache tile (Hakura, paragraph 67). This means better and more efficient memory usage due to rendering tile generated by using bounding box information to identify primitives.
However, the combination of DOYLE and Hakura fails to explicitly teach wherein reading the bounding box hierarchy information from the set of one or more blocks of memory space comprises:
reading first information representative of a first bounding box of a higher level of the hierarchy of bounding boxes from a first location in a block of memory space of the set of one or more blocks of memory space;
However, Muthler teaches wherein reading the bounding box hierarchy information from the set of one or more blocks of memory space comprises:
reading first information representative of a first bounding box of a higher level of the hierarchy of bounding boxes from a first location in a block of memory space of the set of one or more blocks of memory space (Muthler, paragraph 113 teaches "FIGS. 8A and 8B show a recursively-subdivided bounding volume of a 3D scene (FIG. 8A) and a corresponding tree data structure (FIG. 8B) that may be accessed by the traversal coprocessor 138 and used for hardware-accelerated operations performed by traversal coprocessor. The division of the bounding volumes may be represented in a hierarchical tree data structure with the large bounding volume shown in FIG. 2B represented by a parent node of the tree and the smaller bounding volumes represented by children nodes of the tree that are contained by the parent node"); corresponding data structure in fig. 8B for bounding volumes shows levels of hierarchy with each level being a node meaning that each level inclusive of first/higher level of hierarchy of the bounding volume is stored in a respective (first/higher level stored in first) location in block of memory space, also, "the first location in the block of memory space" is the contents at that location, which would be the parent (higher level) node, and storing information is done for later reading it; Muthler is considered to be analogous art because it is reasonably pertinent to the problem faced by the inventor of levels of the hierarchy of bounding boxes and data structure relations to such. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of DOYLE and Hakura with the bounding box in relation to data structure techniques of Muthler to ensure an improved hardware-based scheduling cache memory for ray tracing bounding volume hierarchy traversal and other performance and/or memory management enhancements (Muthler, paragraph 8). This would be from the data structure's efficient management of the levels of the hierarchy of bounding boxes.
However, the combination of DOYLE, Hakura, and Muthler fails to explicitly teach determining, based on the first location, one or more further locations in the same block of memory space of the set of one or more blocks of memory space for reading further information representative of one or more related bounding boxes of one or more lower levels of the hierarchy of bounding boxes that the first bounding box bounds;
However, Allgyer teaches
determining, based on the first location, one or more further locations in the same block of memory space of the set of one or more blocks of memory space for reading further information representative of one or more related bounding boxes of one or more lower levels of the hierarchy of bounding boxes that the first bounding box bounds (Allgyer, page 24, second paragraph teaches “so the arrays described above must be of fixed size. This means a maximum size had to be chosen and the arrays are always given this size… maximum size could be modified to allow for larger scenes, however”); maximum size modified shows further location in same block/array of memory space of the set of one or more blocks of memory space, this is for storing/reading related bounding box further information (hence the size increase), and this would be for lower levels of the hierarchy of bounding boxes that the first bounding box bounds when viewed in combination with the above references and top-bottom BVH scheme aforementioned from DOYLE. Allgyer is considered to be analogous art because it is reasonably pertinent to the problem faced by the inventor of memory allocation and specific ordering of storing/reading information. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of DOYLE, Hakura, and Muthler with the locations in memory block(s) and ordering the storing/reading of BVH techniques of Allgyer to ensure GPU is very efficient at performing the same operations on many sets of data, while the CPU is good at recursion and handling complex data structures (Allgyer, page 10, third paragraph). This means a more efficient system overall.
Regarding claim 6, the combination of DOYLE, Hakura, Muthler and Allgyer teaches wherein storing the further information comprises: updating, at the determined one or more further locations in the same block of memory space of the set of one or more blocks of memory space, the one or more related bounding boxes that bound the first bounding box based on the first bounding box (Muthler, paragraph 117 teaches "When bounding volume N7 is in a different coordinate space from its parent bounding volume N3, an instance node N7′ which provides the ray transformation necessary to traverse the subtree rooted at N7, may connect the rest of the tree to the subtree rooted at N7. Instance node N7′ connects the bounding volume or BVH corresponding to nodes N1-N3, with the bounding volumes or BVH corresponding to nodes N7 etc. by defining the transformation from the coordinate space of N1-N3 (e.g., world space) to the coordinate space of N7 etc. (e.g., object space)"); this shows when a child node is in different coordinate space, it impacts/updates the parent Nodes N1-N3 by defining the transformation meaning the N1 node/higher-level bounding box [bounding box that bounds first/lowest bounding box] is updated based on the first/lower-level bounding box/N7 node. The same motivations used in claim 1 apply here in claim 6.
Regarding claim 11, the combination of DOYLE, Hakura, Muthler and Allgyer teaches determining whether the rendering tile overlaps the first bounding box (Hakura, paragraph 121 teaches “If a coarse bounding box intersects the current cache tile, then the tiling unit determines whether each accumulated bounding box included in the coarse bounding box intersects the cache tile.”); this intersection test shows determining if overlap occurs in tile and coarse bounding box/highest-level/first bounding box; and when it is determined that the rendering tile overlaps the first bounding box: reading the further information representative of one or more related bounding boxes that the first bounding box bounds from the determined one or more further locations in the same block of memory space of the set of one or more blocks of memory space (Hakura, paragraph 121 teaches "If a coarse bounding box intersects the current cache tile, then the tiling unit determines whether each accumulated bounding box included in the coarse bounding box intersects the cache tile"); bounding box included in coarse bounding box indicates related bounding box and it must be read/obtained (which would be from the aforementioned further location in block of memory space) to make the cited determination; and using the further information to determine whether the rendering tile overlaps the one or more related bounding boxes that the first bounding box bounds (Hakura, paragraph 9 teaches "method further includes comparing each bounding box included in the plurality of bounding boxes against the first cache tile to determine that a first set of one or more bounding boxes included in the plurality of bounding boxes intersects the first cache tile" and paragraph 10 teaches "by analyzing the fine bounding boxes only after determining that the corresponding coarse bounding box intersects the current cache tile, the number of intersection calculations performed for each cache tile may be reduced"); comparing each bounding box for intersection with tile and analyzing fine bounding boxes shows determining of whether the rendering tile overlaps related bounding boxes that the first bounding box bounds. The same motivations used in claim 1 apply here in claim 11.
Regarding claim 12, the system claim 12 recites similar limitations as method claim 1, and thus is rejected under similar rationale. In addition, DOYLE, paragraph 108 teaches " graphics processor 320 having a tiled architecture," and fig. 1 shows a computer system that can be implemented as the tile-based graphics processing system with a processing circuit 107 and storing/memory circuit 124.
Regarding claim 17, the system claim 17 recites similar limitations as method claim 6, and thus is rejected under similar rationale.
Regarding claim 19, the system claim 19 recites similar limitations as method claim 9, and thus is rejected under similar rationale. In addition, DOYLE, paragraph 108 teaches "graphics processor 320 having a tiled architecture," and fig. 1 shows a computer system that can be implemented as the tile-based graphics processing system with a processing circuit 107 and GPU 106; GPU acts as rendering circuit since it comprises a circuit for rendering and the processing circuit is the primitive providing circuit since the CPU executes code and that’s what sends/provides/receives primitives mentioned in the abstract and title of DOYLE.
Regarding claim 21, the system claim 21 recites similar limitations as method claim 11, and thus is rejected under similar rationale.
Claim(s) 2-3 and 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of DOYLE, Hakura, Muthler and Allgyer as applied to claims 1 and 12 above, and further in view of Engh-Halstvedt (U.S. Patent Application Publication No. 20210295584 A1), hereinafter referenced as Engh-Halstvedt.
Regarding claim 2, the combination of DOYLE, Hakura, Muthler and Allgyer
fails to explicitly teach wherein the set of one or more blocks of memory space is a linked list of blocks of memory space, and the method comprises: determining whether the linked list of blocks of memory space has insufficient memory space available to store the first information;
and when it is determined that the linked list of blocks of memory space has insufficient memory space available to store the first information:
adding a block of memory space to an end of the linked list of blocks of memory space; storing the first information and the further information in memory space of the block of memory space added to the end of the linked list of blocks of memory space; and storing a pointer pointing to the block of memory space added to the end of the linked list of blocks of memory space.
However, Engh-Halstvedt teaches wherein the set of one or more blocks of memory space is a linked list of blocks of memory space, and the method comprises: (Engh-Halstvedt, abstract teaches "set of blocks of memory space that may be represented by a linked list is provided"); determining whether the linked list of blocks of memory space has insufficient memory space available to store the first information (Engh-Halstvedt, paragraph 114 teaches “check is therefore in an embodiment performed (by the memory space allocation circuit) to determine whether the current memory space block has sufficient memory space available”); this shows determination whether linked list of blocks of memory space has insufficient memory to store the aforementioned first information;
and when it is determined that the linked list of blocks of memory space has insufficient memory space available to store the first information (Engh-Halstvedt, paragraph 117 teaches “it can readily be (and in an embodiment is) determined when the memory space block has been used up (when there is insufficient free space in the memory space block for further data)”); this shows aforementioned linked list with insufficient memory space available to store the first information;
adding a block of memory space to an end of the linked list of blocks of memory space (Engh-Halstvedt, paragraph 127 teaches "additional memory space is added to the set (list) (in an embodiment by adding one or more additional memory space blocks to the end of the list)"); this shows adding new blocks of memory space to the end of the linked list; storing the first information and the further information in memory space of the block of memory space added to the end of the linked list of blocks of memory space (Engh-Halstvedt, paragraph 129 teaches “a memory space block is newly set aside (by the host processor) for use by the graphics processing pipeline”); this shows the first information and further information from graphics pipeline aforementioned in the above explanations (when viewed in combination) would be stored in the memory space of block of memory space added to the end of the linked list of blocks of memory space; and storing a pointer pointing to the block of memory space added to the end of the linked list of blocks of memory space (Engh-Halstvedt, paragraph 170 teaches "for example, moving or adding one or more memory space blocks to the end of a linked list in an embodiment comprises updating the sequence indicating link (e.g. pointer) for the memory space block that was previously at the end of the linked list to indicate that the (first) newly added memory space block is now the next memory space block in the linked list"); this shows pointer stored for newly added memory space at the end of the linked list. Engh-Halstvedt is considered to be analogous art because it is reasonably pertinent to the problem faced by the inventor of usage of pointers alongside linked lists and blocks of memory space. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of DOYLE, Hakura, Muthler and Allgyer with the specific data structure techniques of Engh-Halstvedt to facilitate simpler and more flexible memory management and improve the handling of “out-of-memory” situations, and moreover, can allow the size of the overall pool (heap) of memory space to be dynamically adjusted in response to the actual amount of memory space that is being used for a graphics output (Engh-Halstvedt, paragraph 45). This means more efficient memory management
Regarding claim 3, the combination of DOYLE, Hakura, Muthler, Allgyer and Engh-Halstvedt teaches wherein the block of memory space added to the end of the linked list of blocks of memory space is larger than the block(s) of memory space already in the linked list of blocks of memory space (Engh-Halstvedt, paragraph 66 teaches "size of a (each) memory space block may be selected based on an amount of data that the set is expected to store, e.g. and in an embodiment, for a graphics output (e.g. frame) that the graphics processing pipeline is generating. Thus, for example and in an embodiment, a larger memory space block size may be used when generating a more memory intensive"); this shows larger (than that which already exists) memory space block being added. The same motivations used in claim 2 apply here in claim 3.
Regarding claim 13, the system claim 13 recites similar limitations as method claim 2, and thus is rejected under similar rationale.
Regarding claim 14, the system claim 14 recites similar limitations as method claim 3, and thus is rejected under similar rationale.
Claim(s) 7 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of DOYLE, Hakura, Muthler and Allgyer as applied to claims 1 and 12 above, and further in view of Muthler G. (U.S. Patent Application Publication No. 20240009226), hereinafter referenced as Muthler2.
Regarding claim 7, the combination of DOYLE, Hakura, Muthler and Allgyer fails to teach further comprising storing, in association with the first bounding box, a pointer pointing to data that defines primitives of a subset of primitives that the first bounding box bounds.
However, Muthler2 teaches further comprising storing, in association with the first bounding box, a pointer pointing to data that defines primitives of a subset of primitives that the first bounding box bounds (Muthler2, paragraph 181 teaches "each fetched complet references its parent complet with a parent pointer or offset, encodes child pointers in compressed form, and provides a per-child struct containing a child bounding box and per-child data used by the RayOp test (e.g. Rval, invert RayOp result flag), and (in the case of leaf nodes) data used to address and process blocks of leaf nodes (e.g. item count, starting primitive index, number of blocks in leaf, a flag indicating the presence of alpha primitives)"); child pointers providing a struct for addressing and processing blocks of leaf nodes including primitive index shows a pointer pointing to data defining the primitives of subset, encodes shows storing and this is in association with a child node/first bounding box. Muthler2 is considered to be analogous art because it is reasonably pertinent to the problem faced by the inventor of pointers used with lower-level bounding boxes which have primitives. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of DOYLE, Hakura, Muthler and Allgyer with the pointer techniques of Muthler2 to ensure a system that is more efficient to further volumetrically subdivide and thereby limit the number of primitives in any “leaf node” to something like 16 or fewer (Muthler2, paragraph 96). This would be due to the pointer pointing to data used to address and process blocks of the leaf node, leading to a more efficient system.
Regarding claim 18, the system claim 18 recites similar limitations as method claim 7, and thus is rejected under similar rationale.
Claim(s) 22 is/are rejected under 35 U.S.C. 103 as being unpatentable the combination of DOYLE, Hakura, Muthler and Allgyer as applied to claim 1 above, and further in view of Hensley et al. (U.S. Patent Application Publication No. 2019/0102865), hereinafter referenced as Hensley.
Regarding claim 22, the combination of DOYLE, Hakura, Muthler and Allgyer fails to teach comprising: using the bounding box hierarchy information to identify primitives to rasterise and render to generate the rendering tile; and rasterising and rendering the identified primitives to generate the rendering tile.
However, Hensley teaches comprising: using the bounding box hierarchy information to identify primitives to rasterise and render to generate the rendering tile; and rasterising and rendering the identified primitives to generate the rendering tile. (Hensley, paragraph 68 teaches “bounding box may be used to determine which primitives should be considered for each tile, which are then rasterized for the tile after translation”); rasterize for tile after translation shows rasterizing and rendering a identified primitive to generate a translated/rendering tile and the bounding box is used to identify the primitive to do such here. Hensley is considered to be analogous art because it is reasonably pertinent to the problem faced by the inventor of rasterizing primitives. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of DOYLE, Hakura, Muthler and Allgyer with the rasterizing techniques of Hensley to further reduce computation and power consumption in a graphics unit, improve image quality as displayed to a user (Hensley, abstract). This would be done by the use of bounding box to identify primitives to rasterize.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Wald (U.S. Patent Application Publication No. 2023/0118972) paragraph 55 teaches “one or more portions of BVH 124 and/or BVH data 222 can be stored in an L2 cache in each partition unit 215, in lieu of or in addition to being stored on DRAM 220 in PP memory”; this shows memory blocks/partitioning alongside allocation for further locations and levels of bounding boxes.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NAUMAN U AHMAD whose telephone number is (703)756-5306. The examiner can normally be reached Monday - Friday 9:00am - 5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kee Tung can be reached at (571) 272-7794. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/N.U.A./Examiner, Art Unit 2611
/KEE M TUNG/Supervisory Patent Examiner, Art Unit 2611
Prosecution Insights