DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant’s amendment filed 01/08/2026 which has
been entered and made of record. Claims 1-3, 6-7, 9, 11-14, 17-19 and 21 have been amended.
Claim 22 has been newly added. Claims 4-5, 10, 15-16, and 20 have been cancelled. Claims 1-3, 6-9, 11-14, 17-19 and 21-22 are pending in the application. Applicant’s
amendments to the Specification and Claims have overcome each and every objection
previously set forth in the Non-Final Office Action mailed October 27th 2025.
Response to Arguments
Applicant’s arguments with respect to claim(s) Claims 1-3, 6-9, 11-14, 17-19 and 21-22 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument (due to applicant’s arguments directed to newly amend limitation(s) (and change of scope) which is addressed by new prior art presented in this Office Action).
In response to applicant’s argument that “Muthler does not disclose storing information representative of related bounding boxes in a same block of memory space.”, examiner respectfully disagrees because the entirety of the tree of Muthler, fig. 8B can be considered a "block" of memory space as cited below.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Previous 35 U.S.C. 112(b) rejection for claims 5-7, 10-11, 16-17 and 20-21 have been withdrawn, however, new rejections are presented below.
Claims 1-3, 6-9, 11-14, 17-19 and 21-22 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation " generating… bounding box information" in lines 2-3 and “generating… bounding box information” in line 7. There is insufficient antecedent basis for this limitation in the claim. This is because the claim first mentions “generating bounding box information”, (two times which makes it unclear if it’s the same instance of bounding box information being generated), then the claim further mentions “the bounding box information”, thus it is unclear which instance of bounding box information "the bounding box information" is referring to.
Claims 1 and 9 recites the limitation "a hierarchy " in line 3 and “a first level of a hierarchy” in lines 19-20 for claim 1 and lines 17-18 for claim 9. There is insufficient antecedent basis for this limitation in the claim. This is because it is unclear when the second time “a hierarchy” is mentioned whether it is the same instance as the first time the hierarchy is mentioned or a newer/different instance of a hierarchy.
Claim 2 recites the limitation "store bounding box information" in each of line 4 and line 6 and “storing bounding box information” in line 11. There is insufficient antecedent basis for this limitation in the claim. This is because it is unclear whether the bounding box information is the same instance as before (each time it is mentioned) or a newer/different instance.
Claim 3 recites the limitation "wherein adding a block of memory space to the end of the linked list of blocks of memory space comprises adding a block of memory space to the end of the linked list" in lines 1-3. There is insufficient antecedent basis for this limitation in the claim. This is because it is unclear whether the two mentions of block of memory are the same instance or a newer/different instance.
Claim 9 recites the limitation " generating… bounding box information" in lines 2-3, “reading… bounding box information” in lines 9-10, and “reading… bounding box information” in line 16, alongside various instances of “the bounding box information”. There is insufficient antecedent basis for this limitation in the claim. This is because the claim mentions various instances of “bounding box information”, then the claim further mentions “the bounding box information”, thus it is unclear which instance of bounding box information "the bounding box information" is referring to or if these are meant to be the same instance of “bounding box information”.
Claim 9 recites the limitation " to generate a rendering tile” in line 5, and “generating a rendering tile” in line 7, alongside various instances of “the rendering tile” (lines 13-15). There is insufficient antecedent basis for this limitation in the claim. This is because the claim mentions various instances of “a rendering tile”, then the claim further mentions “the rendering tile”, thus it is unclear which instance of rendering tile "the rendering tile" is referring to or if these are meant to be the same instance of “generating a rendering tile”.
Claim 9 recites the limitation "generate a render output” in line 2 and line 10, and “rendering tile of a render output” in line 7. There is insufficient antecedent basis for this limitation in the claim. This is because the claim mentions various instances of “a render output”, thus it is unclear which instance of render output is referred to or if these are meant to be the same instance of “render output”.
Claim 17 recites the limitation "The system or processor of claim 15" in line 1. There is insufficient antecedent basis for this limitation in the claim. This is because a claim which doesn’t exist is being referred to since claim 15 is cancelled. Therefore, it is unclear on which claim, claim 17 depends. Note: claim 17 has been interpreted to depend from claim 12.
Claims 8, 12-14 and 19 are rejected for the same reasons listed above since they recite similar limitations.
Claim 6-7, 11, 18 and 21-22 rejected under 35 U.S.C. 112(b) since it depends on a claim that is rejected under 35 U.S.C. 112(b).
Note. Most likely these claims depend on some dependent claim or are missing elements.
In order to fix this issue, dependency should be reviewed and any first instance of an element
should be made clear that it’s a first instance and should be referred to as “a” or “an” instead of
“the”, and if multiple instances exist, further instances should be further distinguished for example by saying “first”, “second”, and/or “third” etc..
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 6, 8-9, 11-12, 17, 19 and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (U.S. Patent Application Publication No. 2015/0348306 A1), hereinafter referenced as Yang, in view of Hakura (U.S. Patent Application Publication No. 2014/0118393 A1), hereinafter referenced as Hakura, Chalfin et al. (U.S. Patent Application Publication No. 2021/0158584 A1), hereinafter referenced as Chalfin, Muthler (U.S. Patent Application Publication No. 2020/0050550), hereinafter referenced as Muthler, and W3 Schools (DSA Array Implementation), hereinafter referenced as W3.
Regarding claim 1, Yang teaches a method of operating a tile-based graphics processing system or graphics processor that is operable to generate a render output by generating and storing bounding box information representative of a hierarchy of bounding boxes representing positions of primitives to be processed to generate the render output (fig. 2 and paragraph 21 teach "graphics processing system 200 is a tile-based deferred rendering system", paragraph 27 teaches "the primitive block allocation module 216 maintains a bounding box, which is a region in screen space that bounds all the primitives allocated to that primitive block" and paragraph 31 teaches "Another indication of a spatial position is a bounding box, which may be used, e.g. if a primitive has no shared vertices with any of the open primitive blocks. For example, a primitive may have a bounding box within which it is entirely located"); for bounding box to be maintained/stored it must first be generated, this bounding box contains information of space bounding primitives as well as location/spatial position, and these primitives are later processed to generate render output as described below; the method comprising: generating bounding box information for a set of primitives to be processed to generate a render output (paragraph 21 teaches "The data store 220 is configured to store a set of primitive blocks 222.sub.n to which primitives can be allocated" and paragraph 27 teaches "For each open primitive block the primitive block allocation module 216 maintains a bounding box, which is a region in screen space that bounds all the primitives allocated to that primitive block."); primitive block acts as a set since it contains multiple primitives and fig. 5 shows an example of this as well with multiple primitives in the primitive block, and if each primitive block has a bounding box, then that means bounding box information must be generated and kept for each primitive block/set of primitives, and this is all done for the rendering output objective described in abstract and mentioned above.
However, Yang fails to teach and reading and using the bounding box information to identify primitives to process to generate a rendering tile of the render output; and storing the bounding box information in a set of one or more blocks of memory space; wherein storing the bounding box information comprises, storing first information representative of a first bounding box of a first level of a hierarchy of bounding boxes in a first location in a block of memory space of the set of one or more blocks of memory space; and storing further information representative of one or more related bounding boxes of one or more further levels of the hierarchy of bounding boxes in one or more further locations in the same block of memory space: wherein the one or more further locations in the block of memory space are determinable from the first location in the block of memory space.
However, Hakura teaches and reading and using the bounding box information to identify primitives to process to generate a rendering tile of the render output (Hakura, fig. 8, step 850 and paragraph 107 teaches "If an additional accumulated bounding box is not received, then the tiling unit 375 begins the process of tiled rendering at step 850 by identifying a cache tile 410 for which the accumulated bounding boxes and graphics primitives currently stored in the buffer memory are to be processed." and paragraph 109 teaches "after each cache tile 410 has been processed with respect to the current tiled rendering pass, the results stored in the array may be cleared, and, at step 810, the next batch of accumulated bounding boxes and graphics primitives may be received by the tiling unit 375 and stored in the buffer memory."); this marks beginning of the tile rendering process, comes after reading and using the bounding box of step 810 of fig. 8, also it identifies primitives using the tiling unit and then identifies/generates a cache tile which is a rendering tile of the render output since used in tiled rendering process. Hakura is considered to be analogous art because it is reasonably pertinent to the problem faced by the inventor of rendering tile techniques using bounding box information and primitive. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Yang's invention with the bounding box and primitive for rendering tiles techniques of Hakura to ensure the technique improves cache memory locality during processing in the screen space pipeline, where multiple memory operations associated with a first cache tile access a region of the L2 caches, or any other technically feasible cache memory, that may stay resident during screen space processing of the first cache tile (Hakura, paragraph 67). This means better and more efficient memory usage due to rendering tile generated by using bounding box information to identify primitives.
However, the combination of Yang and Hakura fails to teach and storing the bounding box information in a set of one or more blocks of memory space; wherein storing the bounding box information comprises, storing first information representative of a first bounding box of a first level of a hierarchy of bounding boxes in a first location in a block of memory space of the set of one or more blocks of memory space; and storing further information representative of one or more related bounding boxes of one or more further levels of the hierarchy of bounding boxes in one or more further locations in the same block of memory space: wherein the one or more further locations in the block of memory space are determinable from the first location in the block of memory space.
However, Chalfin teaches and storing the bounding box information in a set of one or more blocks of memory space (Chalfin, paragraph 131 teaches "Once a block of memory space has been allocated for a particular region, any primitive data for the region can then be added into the block (at least until the block is full)"); since bounding box information contains information on primitives as explained above from Yang, this storage of primitive into block of memory space is the storing of the bounding box information; Chalfin is considered to be analogous art because it is reasonably pertinent to the problem faced by the inventor of dynamic memory management and adding blocks of memory space when needed. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Yang and Hakura with the dynamic memory allocation techniques of Chalfin to allow for an improved (more efficient) usage of memory space and/or improvements in power or performance (Chalfin, paragraph 62). This would be due to on demand memory allocation.
However, the combination of Yang, Hakura and Chalfin fails to teach wherein storing the bounding box information comprises, storing first information representative of a first bounding box of a first level of a hierarchy of bounding boxes in a first location in a block of memory space of the set of one or more blocks of memory space; and storing further information representative of one or more related bounding boxes of one or more further levels of the hierarchy of bounding boxes in one or more further locations in the same block of memory space: wherein the one or more further locations in the block of memory space are determinable from the first location in the block of memory space.
However, Muthler teaches wherein storing bounding box information comprises, storing first information representative of a first bounding box of a first level of a hierarchy of bounding boxes in a first location in a block of memory space of the set of one or more blocks of memory space (Muthler, paragraph 113 teaches "FIGS. 8A and 8B show a recursively-subdivided bounding volume of a 3D scene (FIG. 8A) and a corresponding tree data structure (FIG. 8B) that may be accessed by the traversal coprocessor 138 and used for hardware-accelerated operations performed by traversal coprocessor. The division of the bounding volumes may be represented in a hierarchical tree data structure with the large bounding volume shown in FIG. 2B represented by a parent node of the tree and the smaller bounding volumes represented by children nodes of the tree that are contained by the parent node"); corresponding data structure in fig. 8B for bounding volumes shows levels of hierarchy with each level being a node meaning that each level inclusive of first level of hierarchy of the bounding volume is stored in a respective (first level stored in first) location in block of memory space, also, "the first location in the block of memory space" is the contents at that location, which would be the parent node; and storing further information representative of one or more related bounding boxes of one or more further levels of the hierarchy of bounding boxes in one or more further locations in the same block of memory space (Muthler, paragraph 115 teaches "FIG. 8A, bounding volume N1 is subdivided into bounding volumes N2 and N3. Children nodes N2 and N3 of the tree structure of FIG. 8B correspond to and represent the bounding volumes N2 and N3 shown in FIG. 8A. The children nodes N2 and N3 in the tree data structure identify the vertices of respective bounding volumes N2 and N3 in space"); children nodes in the data structure corresponding to the further levels of hierarchy of bounding boxes show the storing of further information and since these are nodes it would be in further locations in the block of memory space. Muthler is considered to be analogous art because it is reasonably pertinent to the problem faced by the inventor of levels of the hierarchy of bounding boxes and data structure relations to such. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Yang, Hakura and Chalfin with the bounding box in relation to data structure techniques of Muthler to ensure an improved hardware-based scheduling cache memory for ray tracing bounding volume hierarchy traversal and other performance and/or memory management enhancements (Muthler, paragraph 8). This would be from the data structure's efficient management of the levels of the hierarchy of bounding boxes.
However, the combination of Yang, Hakura, Chalfin, and Muthler fails to explicitly teach wherein the one or more further locations in the block of memory space are determinable from the first location in the block of memory space (although, Muthler, paragraph 95 teaches "it is possible to push nodes onto the traversal stack in the order the nodes appear in memory, or in the order that they appear along the length of the ray, or in some other order."); if pushed into stack in order the nodes appear in memory, one of ordinary skill in the art could use traversing techniques to differentiable locations.
However, W3 explicitly teaches wherein the one or more further locations in the block of memory space are determinable from the first location in the block of memory space
(W3, page 2, first paragraph teaches “Binary Tree can be stored in an Array starting with the root node R on index 0. The rest of the tree can be built by taking a node stored on index 2*i+1, and storing its left child node on index 2*i+2”
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); this shows root/parent node being at index 0 and children nodes being at different index meaning parent node at first location is determinable from the further children locations due to different indices, also the block of memory space is the tree itself since stored in array (contiguous block of memory) and this concept is applied to the tree in fig. 8B of Muthler. W3 is considered to be analogous art because it is reasonably pertinent to the problem faced by the inventor of having locations in memory space determinable from other locations. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Yang, Hakura, Chalfin, and Muthler with the determinable locations of memory spaces techniques of W3 so
an Array implementation of a Binary Tree can make sense as it needs less memory, it can be easier to implement, and it can be faster for certain operations due to cache locality. (W3, page 1, paragraph 2). This means more efficient system.
Regarding claim 8, the non-transitory computer readable storage claim 8 recites similar limitations as method claim 1, and thus is rejected under similar rationale. In addition, Yang, paragraph 60 teaches "wherein a non-transitory computer readable storage medium may have stored thereon processor executable instructions that when executed at such a computer system".
Regarding claim 9, Yang teaches a method of operating a tile-based graphics processing system or graphics processor that is operable to generate a render output by generating and storing bounding box information representative of a hierarchy of bounding boxes representing positions of primitives to be processed to generate the render output, (fig. 2 and paragraph 21 teach "graphics processing system 200 is a tile-based deferred rendering system", paragraph 27 teaches "the primitive block allocation module 216 maintains a bounding box, which is a region in screen space that bounds all the primitives allocated to that primitive block" and paragraph 31 teaches "Another indication of a spatial position is a bounding box, which may be used, e.g. if a primitive has no shared vertices with any of the open primitive blocks. For example, a primitive may have a bounding box within which it is entirely located", also, claim 13 teaches “compare the bounding box of the received primitive and the bounding boxes of the primitive blocks stored in the data store to determine whether the bounding box of the received primitive overlaps with, or is within a minimum distance from overlapping with, the bounding box of a primitive block stored in the data store”); for bounding box to be maintained/stored it must first be generated, this bounding box contains information of space bounding primitives as well as location/spatial position, and these primitives are later processed to generate render output as described below, also, if bounding boxes overlap as in claim 13, it shows a hierarchy of bounding boxes which can further be explained from the combination below);
However, Yang fails to teach and reading and using the bounding box information to identify primitives to process to generate a rendering tile of the render output; the method comprising: generating a rendering tile of a render output by, reading, from a set of one or more blocks of memory space, bounding box information for a set of primitives to be processed to generate a render output; using the bounding box information to identify primitives to process to generate the rendering tile; and processing the identified primitives to generate the rendering tile; wherein reading bounding box information comprises: reading first information representative of a first bounding box of a first level of a hierarchy of bounding boxes from a first location in a block of memory space of the set of one or more blocks of memory space; and reading further information representative of one or more related bounding boxes of one or more further levels of the hierarchy of bounding boxes from one or more further locations in the same block of memory space; wherein the one or more further locations in the block of memory space are determinable from the first location in the block of memory space.
However, Hakura teaches and reading and using the bounding box information to identify primitives to process to generate a rendering tile of the render output; (Hakura, fig. 8, step 850 and paragraph 107 teaches "If an additional accumulated bounding box is not received, then the tiling unit 375 begins the process of tiled rendering at step 850 by identifying a cache tile 410 for which the accumulated bounding boxes and graphics primitives currently stored in the buffer memory are to be processed." and paragraph 109 teaches "after each cache tile 410 has been processed with respect to the current tiled rendering pass, the results stored in the array may be cleared, and, at step 810, the next batch of accumulated bounding boxes and graphics primitives may be received by the tiling unit 375 and stored in the buffer memory."); this marks beginning of the tile rendering process, comes after reading and using the bounding box of step 810 of fig. 8, also it identifies primitives using the tiling unit and then identifies/generates a cache tile which is a rendering tile of the render output since used in tiled rendering process; the method comprising: generating a rendering tile of a render output by,
(Hakura, paragraph 66 teaches “screen space is divided into cache tiles, where each cache tile is associated with a portion of the screen space” and abstract teaches “ identifying a first cache tile associated with a render surface”); cache tile is associated with rendering thus is considered rendering tile of a render output (since also used for display/screen space); reading, from a set of one or more blocks of memory space, bounding box information for a set of primitives to be processed to generate a render output (Hakura, fig. 11 and paragraph 113 teaches "any number of accumulated bounding boxes may be combined to generate each coarse bounding box. In one implementation, each coarse bounding box may include approximately 128 graphics primitives...example of this type of bounding box hierarchy is shown in FIG. 11, which is a conceptual illustration showing the relationship between a coarse bounding box 1110-2 and multiple accumulated bounding boxes 620"); when viewed in combination, this would be read from the aforementioned respective block of memory space since bounding box information is stored in blocks of memory in Chalfin and this shows graphics primitives thus primitives to be processed to generate a render output; using the bounding box information to identify primitives to process to generate the rendering tile; (Hakura, paragraph 65 teaches "The VPC 370 performs clipping, culling, and viewport transform to determine which graphics primitives are potentially viewable in the final rendered image and which graphics primitives are not potentially viewable. The VPC 370 then transmits processed graphics primitives and their associated bounding boxes to a bounding box (BB) unit 372. The bounding box unit 372 combines the bounding boxes to generate one or more accumulated bounding boxes." and fig. 5 teaches the steps for generating accumulated bounding boxes starting at step 510 which teaches "receive graphics primitive and/or bounding box"); graphics primitives that are potentially viewable are identified because they would be processed to generate rendering tiles since viewable and this is done by traversing respective hierarchy or bounding box (thus using bounding box information) due to the fig. 5 saying it can also receive a bounding box alongside the graphics primitive and this step looping after "yes" in step 580; and processing any identified primitives to generate the rendering tile (Hakura, paragraph 66 teaches "Graphics primitives are processed in the world space pipeline 352 and then transmitted to the tiling unit 375. The screen space is divided into cache tiles, where each cache tile is associated with a portion of the screen space. For each graphics primitive, the tiling unit 375 identifies the set of cache tiles that intersect with the graphics primitive, a process referred to herein as "tiling."); this shows processing the aforementioned primitives to generate the rendering tile/cache tiles. Hakura is considered to be analogous art because it is reasonably pertinent to the problem faced by the inventor of rendering tile techniques using bounding box information and primitive. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Yang's invention with the bounding box and primitive for rendering tiles techniques of Hakura to ensure the technique improves cache memory locality during processing in the screen space pipeline, where multiple memory operations associated with a first cache tile access a region of the L2 caches, or any other technically feasible cache memory, that may stay resident during screen space processing of the first cache tile (Hakura, paragraph 67). This means better and more efficient memory usage due to rendering tile generated by using bounding box information to identify primitives.
However, the combination of Yang and Hakura fails to explicitly teach one or more blocks of memory space; although one of ordinary skill in the art would understand that block of memory is just bytes of data and that in Hakura this must exist [however, below reference is included for further explicit teachings].
However, Chalfin explicitly teaches one or more blocks of memory space: (Chalfin, paragraph 131 teaches "Once a block of memory space has been allocated for a particular region, any primitive data for the region can then be added into the block" and paragraph 216 teaches "In a tile-based rendering system the render output is divided into a plurality of tiles for rendering. The tiles are then rendered separately to generate the render output. To do this, it is first necessary to sort the primitives according to which tiles they should be rendered for"); this also shows rendering tiles and each being able to have their own memory block meaning a tile is generated for each block of memory since the block of memory space can hold any primitive data for a particular region which would be considered a tile. Chalfin is considered to be analogous art because it is reasonably pertinent to the problem faced by the inventor of dynamic memory management and adding blocks of memory space when needed. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Yang and Hakura with the dynamic memory allocation techniques of Chalfin to allow for an improved (more efficient) usage of memory space and/or improvements in power or performance (Chalfin, paragraph 62). This would be due to on demand memory allocation.
However, the combination of Yang, Hakura and Chalfin fails to teach wherein reading bounding box information comprises: reading first information representative of a first bounding box of a first level of a hierarchy of bounding boxes from a first location in a block of memory space of the set of one or more blocks of memory space; and reading further information representative of one or more related bounding boxes of one or more further levels of the hierarchy of bounding boxes from one or more further locations in the same block of memory space; wherein the one or more further locations in the block of memory space are determinable from the first location in the block of memory space.
However, Muthler teaches wherein reading bounding box information comprises: reading first information representative of a first bounding box of a first level of a hierarchy of bounding boxes from a first location in a block of memory space of the set of one or more blocks of memory space (Muthler, paragraph 113 teaches "FIGS. 8A and 8B show a recursively-subdivided bounding volume of a 3D scene (FIG. 8A) and a corresponding tree data structure (FIG. 8B) that may be accessed by the traversal coprocessor 138 and used for hardware-accelerated operations performed by traversal coprocessor. The division of the bounding volumes may be represented in a hierarchical tree data structure with the large bounding volume shown in FIG. 2B represented by a parent node of the tree and the smaller bounding volumes represented by children nodes of the tree that are contained by the parent node"); corresponding data structure in fig. 8B for bounding volumes shows levels of hierarchy with each level being a node meaning that each level inclusive of first level of hierarchy of the bounding volume is stored in a respective (first level stored in first) location in block of memory space, also, "the first location in the block of memory space" is the contents at that location, which would be the parent node, and storing information is done for later reading it; and reading further information representative of one or more related bounding boxes of one or more further levels of the hierarchy of bounding boxes from one or more further locations in the same block of memory space (Muthler, paragraph 115 teaches "FIG. 8A, bounding volume N1 is subdivided into bounding volumes N2 and N3. Children nodes N2 and N3 of the tree structure of FIG. 8B correspond to and represent the bounding volumes N2 and N3 shown in FIG. 8A. The children nodes N2 and N3 in the tree data structure identify the vertices of respective bounding volumes N2 and N3 in space"); children nodes in the data structure corresponding to the further levels of hierarchy of bounding boxes show the storing of further information and since these are nodes it would be in further locations in the block of memory space. Muthler is considered to be analogous art because it is reasonably pertinent to the problem faced by the inventor of levels of the hierarchy of bounding boxes and data structure relations to such. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Yang, Hakura and Chalfin with the bounding box in relation to data structure techniques of Muthler to ensure an improved hardware-based scheduling cache memory for ray tracing bounding volume hierarchy traversal and other performance and/or memory management enhancements (Muthler, paragraph 8). This would be from the data structure's efficient management of the levels of the hierarchy of bounding boxes.
However, the combination of Yang, Hakura, Chalfin, and Muthler fails to explicitly teach wherein the one or more further locations in the block of memory space are determinable from the first location in the block of memory space (although, Muthler, paragraph 95 teaches "it is possible to push nodes onto the traversal stack in the order the nodes appear in memory, or in the order that they appear along the length of the ray, or in some other order."); if pushed into stack in order the nodes appear in memory, one of ordinary skill in the art could use traversing techniques to differentiable locations.
However, W3 explicitly teaches wherein the one or more further locations in the block of memory space are determinable from the first location in the block of memory space
(W3, page 2, first paragraph teaches “Binary Tree can be stored in an Array starting with the root node R on index 0. The rest of the tree can be built by taking a node stored on index 2*i+1, and storing its left child node on index 2*i+2”
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); this shows root/parent node being at index 0 and children nodes being at different index meaning parent node at first location is determinable from the further children locations due to different indices, also the block of memory space is the tree itself since stored in array (contiguous block of memory) and this concept is applied to the tree in fig. 8B of Muthler. W3 is considered to be analogous art because it is reasonably pertinent to the problem faced by the inventor of having locations in memory space determinable from other locations. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Yang, Hakura, Chalfin, and Muthler with the determinable locations of memory spaces techniques of W3 so
an Array implementation of a Binary Tree can make sense as it needs less memory, it can be easier to implement, and it can be faster for certain operations due to cache locality. (W3, page 1, paragraph 2). This means more efficient system.
Regarding claim 6, the combination of Yang, Hakura, Chalfin, Muthler and W3 teaches comprising, generating a lower-level bounding box that bounds all of the primitives of a subset of the set of primitives (Muthler, paragraph 115 teaches "Bounding volume N7 include two bounding volumes N8 and N9. Bounding volume N8 includes the triangles O7 and O8, and bounding volume N9 includes leaf bounding volumes N10 and N11 as its child bounding volumes. Leaf bounding volume N10 includes a primitive range (e.g., triangle range) O10 and leaf bounding volume N11 includes an item range O9"); leaf bounding volume such as N10 including a primitive range/subset shows generating lower level bounding volume; storing the lower-level bounding box at the first location in the block of memory space (Muthler, paragraph 95 teaches "it is possible to push nodes onto the traversal stack in the order the nodes appear in memory"); this means node N10 representing a lower level bounding box would also be stored at a location in block of memory space which can be considered first; locating, based on information indicating the first location in the block of memory space, the one or more further locations in the block of memory space (Muthler, paragraph 356 teaches "a generic “NodeRef” hit type is provided that consists of a pointer to the parent complet itself," and paragraph 93 teaches " In example non-limiting embodiments, “complets” (compressed treelets) specify root or interior nodes (i.e., volumes) of the bounding volume hierarchy with children that are other complets or leaf nodes of a single type per complet"); pointer to parent complet/node shows that the location, for storing higher-level bounding box/parent node (which contains lower-level bounding box), is obtained, and this would be based on the aforementioned nodes appearing in memory meaning it is based on information indicating the location in the block of memory space; and updating, at the one or more further locations in the block of memory space, one or more related higher-level bounding boxes that bound the lower-level bounding box based on the lower-level bounding box (Muthler, paragraph 117 teaches "When bounding volume N7 is in a different coordinate space from its parent bounding volume N3, an instance node N7′ which provides the ray transformation necessary to traverse the subtree rooted at N7, may connect the rest of the tree to the subtree rooted at N7. Instance node N7′ connects the bounding volume or BVH corresponding to nodes N1-N3, with the bounding volumes or BVH corresponding to nodes N7 etc. by defining the transformation from the coordinate space of N1-N3 (e.g., world space) to the coordinate space of N7 etc. (e.g., object space)"); this shows when a child node is in different coordinate space, it impacts/updates the parent Nodes N1-N3 by defining the transformation meaning the N1 node/higher-level bounding box is updated based on the lower-level bounding box/N7 node. The same motivations used in claim 1 apply here in claim 6.
Regarding claim 11, the combination of Yang, Hakura, Chalfin, Muthler and W3 teaches comprising: reading a highest-level bounding box from the first location in the block of memory space (Hakura, paragraph 121 teaches "During tiled rendering, the tiling unit then determines whether each coarse bounding box intersects the current cache tile."); coarse bounding box indicates highest-level bounding box and it must be read/obtained (which would be from the aforementioned location in block of memory space) to make the cited determination; determining whether the rendering tile overlaps the highest-level bounding box (Hakura, paragraph 121 teaches “If a coarse bounding box intersects the current cache tile, then the tiling unit determines whether each accumulated bounding box included in the coarse bounding box intersects the cache tile.”); this intersection test shows determining if overlap occurs in tile and coarse bounding box/highest-level bounding box); and when it is determined that the rendering tile overlaps the highest-level bounding box: locating, based on information indicating the first location in the block of memory space, the one or more further locations in the block of memory space (Hakura, claim 1 teaches “determining that the coarse bounding box intersects the first cache tile; comparing each bounding box included in the plurality of bounding boxes against the first cache tile to determine that a first set of one or more bounding boxes included in the plurality of bounding boxes intersects the first cache tile”); the determination of coarse bounding box intersecting leads to comparing the bounced boxes included within it (lower-level) which means they must be located, also when viewed in combination, this would be based on aforementioned information indicating the location in the block of memory space; reading one or more related lower-level bounding boxes that the highest- level bounding box bounds from the one or more further locations in the block of memory space (Hakura, paragraph 121 teaches "If a coarse bounding box intersects the current cache tile, then the tiling unit determines whether each accumulated bounding box included in the coarse bounding box intersects the cache tile"); bounding box included in coarse bounding box indicates lower-level bounding box and it must be read/obtained (which would be from the aforementioned further location in block of memory space) to make the cited determination; and determining whether the rendering tile overlaps the one or more related lower-level bounding boxes (Hakura, paragraph 9 teaches "method further includes comparing each bounding box included in the plurality of bounding boxes against the first cache tile to determine that a first set of one or more bounding boxes included in the plurality of bounding boxes intersects the first cache tile" and paragraph 10 teaches "by analyzing the fine bounding boxes only after determining that the corresponding coarse bounding box intersects the current cache tile, the number of intersection calculations performed for each cache tile may be reduced"); comparing each bounding box for intersection with tile and analyzing fine bounding boxes shows determining of whether the rendering tile overlaps lower-level bounding boxes. The same motivations used in claim 1 apply here in claim 11.
Regarding claim 12, the system claim 12 recites similar limitations as method claim 1, and thus is rejected under similar rationale. In addition, Yang, paragraph 51 teaches "a tile-based graphics processing system" and fig. 6 shows a computer system that can be implemented as the tile-based graphics processing system with a processing circuit 602 and storing/memory circuit 604.
Regarding claim 17, the system claim 17 recites similar limitations as method claim 6, and thus is rejected under similar rationale.
Regarding claim 19, the system claim 19 recites similar limitations as method claim 9, and thus is rejected under similar rationale. In addition, Yang, paragraph 51 teaches "a tile-based graphics processing system" and fig. 6 shows a computer system that can be implemented as the tile-based graphics processing system with a processing circuit 602 and GPU 202; GPU acts as rendering circuit since it comprises a circuit for rendering and the processing circuit is the primitive providing circuit since the CPU executes code and that’s what sends/provides/receives primitives mentioned in the abstract and title of Yang.
Regarding claim 21, the system claim 21 recites similar limitations as method claim 11, and thus is rejected under similar rationale.
Claim(s) 2-3 and 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Yang, Hakura, Chalfin, Muthler and W3 as applied to claims 1 and 12 above, and further in view of Engh-Halstvedt (U.S. Patent Application Publication No. 20210295584 A1), hereinafter referenced as Engh-Halstvedt.
Regarding claim 2, the combination of Yang, Hakura, Chalfin, Muthler and W3 teaches
determining whether the linked list of blocks of memory space has insufficient memory space available to store bounding box information for a subset of the set of primitives (Chalfin, paragraph 146 teaches "when new primitive data for a primitive (or set of primitives) associated with a particular region is to be written to a respective data structure associated with that region memory, it is in an embodiment first determined whether memory space (a data structure) has already been allocated for the region...When the current memory block is full,"); knowing when memory block is full means determination must be made to see if it has insufficient memory space available and since this can be for primitive instead of set of primitives, the primitive can be considered a subset since a subset can contain one item (one primitive from the set of primitives), also paragraph 136 of Chaflin ensures this is for linked list blocks of memory; and when it is determined that the linked list of blocks of memory space has insufficient memory space available to store bounding box information for the subset of the set of primitives: adding a block of memory space to an end of the linked list of blocks of memory space (Chalfin, paragraph 132 teaches "data structure for a particular region may thus comprise a linked set of memory blocks." and paragraph 146 teaches "When the current memory block is full, a new, free memory block can then be allocated and linked to the data structure."); this shows adding block of memory when insufficient memory is available to store the primitive/subset of set of primitives (contained in aforementioned bounding box information), and viewing in combination with reference below ensures this is done to an end of linked list of blocks of memory space; storing bounding box information for the subset of the set of primitives in memory space of the block of memory space added to the end of the linked list of blocks of memory space (Chalfin, paragraph 175 teaches "when a new primitive is received to be processed, it is first checked in which manner the primitive data should be stored, and the primitive data is then written into the appropriate data structure(s) accordingly."); this shows the new data/subset primitive (contained in bounding box information aforementioned from above) is also written accordingly to the newly allocated block (when checking and determining whether current memory block is full) since the newly allocated block would be the appropriate data structure, and viewing in combination with reference below ensures this is done to an end of linked list of blocks of memory space.
However, the combination of Yang, Hakura, Chalfin, Muthler and W3 fails to explicitly teach wherein the set of one or more blocks of memory space is a linked list of blocks of memory space, and the method comprises: (although Chalfin, paragraph 136 does teach linking the first and second memory blocks such that the data structure comprises a set of linked memory blocks. This is in an embodiment then repeated if/when the second memory block becomes full, with a third memory block then being allocated and linked to the second memory block, and so on” (without using the explicit words linked list)); adding a block of memory space to an end of the linked list of blocks of memory space; and storing a pointer pointing to the block of memory space added to the end of the linked list of blocks of memory space.
However, Engh-Halstvedt teaches wherein the set of one or more blocks of memory space is a linked list of blocks of memory space, and the method comprises: (Engh-Halstvedt, abstract teaches "set of blocks of memory space that may be represented by a linked list is provided"); adding a block of memory space to an end of the linked list of blocks of memory space (Engh-Halstvedt, paragraph 127 teaches "additional memory space is added to the set (list) (in an embodiment by adding one or more additional memory space blocks to the end of the list)"); this shows adding new blocks of memory space to the end of the linked list; and storing a pointer pointing to the block of memory space added to the end of the linked list of blocks of memory space (Engh-Halstvedt, paragraph 170 teaches "for example, moving or adding one or more memory space blocks to the end of a linked list in an embodiment comprises updating the sequence indicating link (e.g. pointer) for the memory space block that was previously at the end of the linked list to indicate that the (first) newly added memory space block is now the next memory space block in the linked list"); this shows pointer stored for newly added memory space at the end of the linked list. Engh-Halstvedt is considered to be analogous art because it is reasonably pertinent to the problem faced by the inventor of usage of pointers alongside linked lists and blocks of memory space. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Yang, Hakura, Chalfin, Muthler and W3 with the specific data structure techniques of Engh-Halstvedt to facilitate simpler and more flexible memory management and improve the handling of “out-of-memory” situations, and moreover, can allow the size of the overall pool (heap) of memory space to be dynamically adjusted in response to the actual amount of memory space that is being used for a graphics output (Engh-Halstvedt, paragraph 45). This means more efficient memory management
Regarding claim 3, the combination of Yang, Hakura, Chalfin, Muthler, W3 and Engh-Halstvedt teaches wherein adding a block of memory space to the end of the linked list of blocks of memory space comprises adding a block of memory space to the end of the linked list of blocks of memory space that is larger than the block(s) of memory space already in the linked list of blocks of memory space (Engh-Halstvedt, paragraph 66 teaches "size of a (each) memory space block may be selected based on an amount of data that the set is expected to store, e.g. and in an embodiment, for a graphics output (e.g. frame) that the graphics processing pipeline is generating. Thus, for example and in an embodiment, a larger memory space block size may be used when generating a more memory intensive"); this shows larger (than that which already exists) memory space block being added. The same motivations used in claim 2 apply here in claim 3.
Regarding claim 13, the system claim 13 recites similar limitations as method claim 2, and thus is rejected under similar rationale.
Regarding claim 14, the system claim 14 recites similar limitations as method claim 3, and thus is rejected under similar rationale.
Claim(s) 7 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Yang, Hakura, Chalfin, Muthler and W3 as applied to claims 6 and 17 above, and further in view of Muthler G. (U.S. Patent Application Publication No. 20240009226), hereinafter referenced as Muthler2.
Regarding claim 7, the combination of Yang, Hakura, Chalfin, Muthler and W3 fails to teach further comprising storing, in association with the lower-level bounding box that bounds all of the primitives of the subset, a pointer pointing to data that defines the primitives of the subset.
However, Muthler2 teaches further comprising storing, in association with the lower-level bounding box that bounds all of the primitives of the subset, a pointer pointing to data that defines the primitives of the subset (Muthler2, paragraph 181 teaches "each fetched complet references its parent complet with a parent pointer or offset, encodes child pointers in compressed form, and provides a per-child struct containing a child bounding box and per-child data used by the RayOp test (e.g. Rval, invert RayOp result flag), and (in the case of leaf nodes) data used to address and process blocks of leaf nodes (e.g. item count, starting primitive index, number of blocks in leaf, a flag indicating the presence of alpha primitives)"); child pointers providing a struct for addressing and processing blocks of leaf nodes including primitive index shows a pointer pointing to data defining the primitives of the subset, encodes shows storing and this is in association with a child node/lower-level bounding box. Muthler2 is considered to be analogous art because it is reasonably pertinent to the problem faced by the inventor of pointers used with lower-level bounding boxes which have primitives. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Yang, Hakura, Chalfin, Muthler and W3 with the pointer techniques of Muthler2 to ensure a system that is more efficient to further volumetrically subdivide and thereby limit the number of primitives in any “leaf node” to something like 16 or fewer (Muthler2, paragraph 96). This would be due to the pointer pointing to data used to address and process blocks of the leaf node, leading to a more efficient system.
Regarding claim 18, the system claim 18 recites similar limitations as method claim 7, and thus is rejected under similar rationale.
Claim(s) 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Yang, Hakura, Chalfin, Muthler and W3 as applied to claim 1 above, and further in view of Hensley et al. (U.S. Patent Application Publication No. 2019/0102865), hereinafter referenced as Hensley.
Regarding claim 22, the combination of Yang, Hakura, Chalfin, Muthler and W3 fails to teach comprising: using the bounding box information to identify primitives to rasterise and render to generate a rendering tile; and rasterising and rendering the identified primitives to generate the rendering tile.
However, Hensley teaches comprising: using the bounding box information to identify primitives to rasterise and render to generate a rendering tile; and rasterising and rendering the identified primitives to generate the rendering tile (Hensley, paragraph 68 teaches “bounding box may be used to determine which primitives should be considered for each tile, which are then rasterized for the tile after translation”); rasterize for tile after translation shows rasterizing and rendering a identified primitive to generate a translated/rendering tile and the bounding box is used to identify the primitive to do such here. Hensley is considered to be analogous art because it is reasonably pertinent to the problem faced by the inventor of rasterizing primitives. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Yang, Hakura, Chalfin, Muthler and W3 with the rasterizing techniques of Hensley to further reduce computation and power consumption in a graphics unit, improve image quality as displayed to a user (Hensley, abstract). This would be done by the use of bounding box to identify primitives to rasterize.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Fan (PBRT _ Bounding Volume Hierarchies _ HSWEIF) page 1 teaches “Bounding volume hierarchies (BVHs) is a widely used method, which organizes the primitives of a scene with a binary tree… each node of the binary tree stores a bounding box that includes all primitives of the subtree.” And pages 14-15 teach child node and parent node in different memory locations.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/N.U.A./ Examiner, Art Unit 2611
/KEE M TUNG/ Supervisory Patent Examiner, Art Unit 2611