Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention recites a judicial exception, is directed to that judicial exception, an abstract idea, as it has not been integrated into practical application and the claims further do not recite significantly more than the judicial exception. Examiner has evaluated the claims under the framework provided in the 2019 Patent Eligibility Guidance published in the Federal Register 01/07/2019 and has provided such analysis below.
Step 1: Claims 1-14 are directed to devices and fall within the statutory category of machines; Claims 15-20 are directed to methods and fall within the statutory category of processes. Therefore, “Are the claims to a process, machine, manufacture or composition of matter?” Claims 1-20, Yes.
In order to evaluate the Step 2A inquiry “Is the claim directed to a law of nature, a natural phenomenon or an abstract idea?” we must determine, at Step 2A Prong 1, whether the claim recites a law of nature, a natural phenomenon or an abstract idea and further whether the claim recites additional elements that integrate the judicial exception into a practical application.
Step 2A Prong 1:
Claims 1 and 15: The limitations of “assign data associated with the tasks to memories associated with the plurality of PPCs and the CPC in a first assignment order; and a scheduler to assign the tasks to the plurality of PPCs in a second assignment order different from the first assignment order such that a task associated with data assigned to the CPC is assigned to at least one of the plurality of PPCs”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can think determine which memory a particular piece of data should be assigned to according to a selected order or pattern. A person can also mentally determine which processing unit a particular task should be assigned to according to a different order or pattern, including determining that a task associated with data assigned to the CPC should be assigned to one of the PPCs. These limitations therefore amount to mentally evaluating and planning how the data and tasks are associated with the memories and processing units, without requiring anything more than the underlying association or assignment.
Claim 8: The limitation “the scheduler assigns the tasks to the plurality of PPCs such that a task associated with data assigned to the CPC is assigned to at least one of the plurality of PPCs.”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can mentally determine that a task associated with data assigned to the CPC should be assigned to one of the PPCs and plan that assignment.
Therefore, Yes, claims 1, 12 and 20 recite judicial exceptions.
The claims have been identified to recite judicial exceptions, Step 2A Prong 2 will evaluate whether the claims are directed to the judicial exception.
Step 2A Prong 2:
Claims 1, 8, and 15: The judicial exception is not integrated into a practical application. In particular, the claim recites the following additional elements – “a multi-chiplet processor”, “a plurality of parallel processing chiplets (PPCs)”, “a central processing chiplet (CPC)”, and “a scheduler” which are merely recitations of generic computing components and functions merely using a computer as a tool to apply the abstract idea (see MPEP § 2106.05(f)) which does not integrate a judicial exception into practical application.
Therefore, “Do the claims recite additional elements that integrate the judicial exception into a practical application? No, these additional elements do not integrate the abstract idea into a practical application and they do not impose any meaningful limits on practicing the abstract idea. The claims are directed to an abstract idea.
After having evaluating the inquires set forth in Steps 2A Prong 1 and 2, it has been concluded that claims 1, 12 and 20 not only recite a judicial exception but that the claims are directed to the judicial exception as the judicial exception has not been integrated into practical application.
Step 2B:
Claims 1, 8, and 15: The claims do not include additional elements, alone or in combination, that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements amount to no more than generic computing components merely using a computer as a tool to apply an abstract idea which do not amount to significantly more than the abstract idea.
Therefore, “Do the claims recite additional elements that amount to significantly more than the judicial exception? No, these additional elements, alone or in combination, do not amount to significantly more than the judicial exception.
Having concluded analysis within the provided framework, claims 1, 8, and 15 do not recite patent eligible subject matter under 35 U.S.C. § 101.
With regards to 2, 9, and 16, they recite additional abstract idea recitations of “the first assignment order sequentially assigns the data to the memories associated with the plurality of PPCs and the CPC” (claims 2 and 16), and “the processor sequentially assigns data to memories associated with the plurality of PPCs and the CPC” (claim 9), as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can mentally determine which is next in a selected sequence and assign each item of data to the next memory in that sequence, including cycling back to the first memory once the last memory is reached. A person could also use pen and paper to keep track of the sequence and determine which memory should receive the next item of data. For the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claims 2, 9 and 16 also fails both Step 2A prong 2, thus the claims are directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more Therefore, Claims 2, 9, and 16 do not recite patent eligible subject matter under 35 U.S.C. § 101.
With regards to 3, 10, and 17, they recite additional abstract idea recitations of “wherein the second assignment order sequentially assigns a first set of the tasks to the plurality of PPCs while skipping a task that would be assigned to the CPC if the CPC were included in the second assignment order” (claims 3 and 17), and “the scheduler sequentially assigns a first set of the tasks to the plurality of PPCs while skipping a task that would be assigned to the CPC if the CPC were included in the sequential assignment” (claim 10), as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can mentally determine which task would otherwise be assigned to the CPC, skip that task, and sequentially assign the remaining tasks to the PPCs. A person could also use pen and paper to keep track of which tasks are skipped and which tasks are assigned to each PPC. For the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claims 3, 10, and 17 also fails both Step 2A prong 2, thus the claims are directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more Therefore, Claims 3, 10, and 17 do not recite patent eligible subject matter under 35 U.S.C. § 101.
With regards to 4, 11, and 18, they recite additional abstract idea recitations of “the task that would be assigned to the CPC if the CPC were included in the second assignment order is sequentially assigned to the plurality of PPCs after sequentially assigning the first set of the tasks” (claims 4 and 18), and “the task that would be assigned to the CPC if the CPC were included in the sequential assignment is sequentially assigned to the plurality of PPCs after sequentially assigning the first set of the tasks” (claim 11), as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can mentally return to the task that was previously skipped after completing the first set of task assignments and then assign that task to the next PPC in the sequence. A person could also use pen and paper to keep track of which previously skipped tasks remain to be assigned and the order in which they should be assigned. For the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claims 4, 11, and 18 also fails both Step 2A prong 2, thus the claims are directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more Therefore, Claims 4, 11, and 18 do not recite patent eligible subject matter under 35 U.S.C. § 101.
With regards to 5, 12, and 19, they recite additional abstract idea recitations of “the second assignment order assigns tasks to the plurality of PPCs to optimize correspondence between the data associated with the tasks that is assigned to the memories associated with the plurality of PPCs and the tasks assigned to the plurality of PPCs” (claims 5 and 19), and “the scheduler assigns tasks to the plurality of PPCs to optimize correspondence between data associated with the tasks that is assigned to memories associated with the plurality of PPCs and the tasks assigned to the plurality of PPCs” (claim 12), as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can mentally determine where the data associated with a particular task is located and then determine that the task should preferably be assigned to the PPC associated with the memory storing that data. For the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claims 5, 12, and 19 also fails both Step 2A prong 2, thus the claims are directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more Therefore, Claims 5, 12, and 19 do not recite patent eligible subject matter under 35 U.S.C. § 101.
With regards to 6, 13, and 20, they recite additional abstract idea recitations of “the scheduler is to reassign a task to a different PPC of the plurality of PPCs to balance a number of tasks assigned to each of the plurality of PPCs” (claims 6), and “reassigning a task to a different PPC of the plurality of PPCs in order to balance a number of tasks assigned to each of the plurality of PPCs” (claim 13 and 20), as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can mentally determine that one PPC has more tasks assigned to it than another and reassign a task from the PPC having fewer tasks in order to balance the number of tasks assigned to each. For the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claims 6, 13, and 20 also fails both Step 2A prong 2, thus the claims are directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more Therefore, Claims 6, 13, and 20 do not recite patent eligible subject matter under 35 U.S.C. § 101.
With regards to 7 and 14, they recite additional abstract idea recitations of “the scheduler is to reassign the task to a different PPC of the plurality of PPCs when a different one of the tasks is cancelled” (claim 7), and “the scheduler reassigns the task to a different PPC of the plurality of PPCs when a different one of the tasks is cancelled” (claim 14), as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can mentally recognize that one task has been cancelled and, in response, determine another task should be reassigned to the PPC that is now available. For the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claims 7 and 14 also fails both Step 2A prong 2, thus the claims are directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more Therefore, Claims 7 and 14 do not recite patent eligible subject matter under 35 U.S.C. § 101.
Therefore, claims 1-20 do not recite patent eligible subject matter under 35 U.S.C. § 101.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 8, 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Piednoel et al. Pub. No. US 20240378090 A1 (hereafter Piednoel) in view of Jahagirdar et al. Pub. No. US 20140026146 A1 (hereafter Jahagirdar).
With regards to claim 1, Piednoel teaches an apparatus comprising: a multi-chiplet processor comprising: a plurality of parallel processing chiplets (PPCs) to process tasks; a central processing chiplet (CPC): “the plurality of chiplets can include a sensor data input chiplet, a central chiplet, and a number of additional workload processing chiplets (e.g., machine learning (ML) accelerator chiplet, autonomous drive chiplets, high-bandwidth memory chiplets, general compute chiplets, and the like) [0003]”; “the workload processing chiplets can continuously monitor and update the reservation table provided in the shared memory of the SoC [0006]”; “the processors 340 and workload processing chiplets 320 can execute multiple independent workload pipelines in parallel, with each workload pipeline including a plurality of workloads to be executed in a deterministic manner. [0054]”; “the central chiplet 300 can include a shared memory 360 storing a reflex program 330…the reflex program 330 can comprise a set of instructions for executing reflex workloads in independent pipelines. The reflex workloads can comprise sensor data acquisition, sensor fusion, and inference tasks that facilitate scene understanding [0047]” showing that the CPC 340 execute this narrower category of workloads distinct from general workload pipelines executed by the PPCs.
Piednoel teaches wherein the multi-chiplet processor is to assign data associated with the tasks to memories associated with the plurality of PPCs and the CPC in a first assignment order “The sensor data input chiplet 210 can automatically dump the received sensor data as it's received into a cache memory 231 of the central chiplet 220 [0036]"; “The autonomous drive chiplet 240 can be connected to a dedicated HBM-RAM chiplet 235 in which the autonomous drive chiplet 240 can publish all status information, variables, statistical information, and/or processed sensor data as processed by the autonomous drive chiplet 240 [0040]”; “the sensor data input chiplet 310 of FIG.3 can correspond to the sensor data input chiplet 210 shown in FIG. 2, and the workload processing chiplets 320 shown in FIG. 3, can correspond to the general compute chiplets 245, ML accelerator chiplet 250, and/or the autonomous drive chiplet 240 shown in FIG. 2. [0046]” Examiner’s Note: Spec [0023] (“order” or “assignment order” do not necessarily refer to a sequence in time but rather an order, or pattern, of assignments relative to the particular components). Sensor data is consistently dumped to the central chiplet’s memory, and the autonomous drive chiplet data is consistently dumped into its own memory. That consistent affinity between a given category of data and a given memory pattern satisfies “first assignment order” under BRI. The order here is analogous to the pattern, of assignments relative to the particular components, rather than timing of the assignments.
Piednoel doesn’t teach a scheduler to assign the tasks to the plurality of PPCs in a second assignment order different from the first assignment order such that a task associated with data assigned to the CPC is assigned to at least one of the plurality of PPCs.
However, in analogous art, Jahagirdar teaches a scheduler to assign the tasks to the plurality of cores in a second assignment order different from the first assignment order such that a task associated with data assigned to the first core is assigned to at least one of the plurality of second cores “an operating system 148 that includes a scheduler 150 may schedule one or more threads 152 for execution at the first core 104. [0021]”; “The second instruction set 130 may include at least one particular instruction (e.g., a multimedia instruction) that the second core 106 is capable of executing but that the first core 104 is incapable of executing. [0019]”; “the first core 104 may be a lower power usage and lower performance core while the second core 106 may be a higher power usage and higher performance core. [0029]”; “The processor 102 may determine... that the first core 104 is incapable of executing one or more of the instructions 154 and that the second core 106 is capable of executing the instructions 154. [0028]”; and in response “may migrate 156...the threads 152 from one core (e.g., the first core 104) to another core (e.g., the second core 106) [0021]”. Examiner’s Note: Applied to Piednoel ‘s architecture, the scheduler assigns a task associated with data assigned to the CPC (lower capability) to a workload processing chiplet capable of executing it (PPC), in an assignment pattern governed by chiplet capability rather than fixed data to memory arrangement, and thus different from the first assignment order.
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to modify Piednoel’s chiplet dispatch mechanism so that the scheduler assigns a task associated with data at the central chiplet to a workload processing chiplet instead, consistent with Jahagirdar ‘s capability based scheduling. A person having ordinary skill in the art would have been motivated to make this combination because Jahagirdar established that instruction not supported by a given core cannot be executed at the core [0019] unless migrated to a core that supports it. Applying this same functional necessity to Piednoel’s system, where the central chip cannot execute general workload tasks efficiently, a person would have recognized the need to hand off the task to a capable chiplet.
With regards to claim 8, Piednoel teaches an apparatus comprising: a multi-chiplet processor including a scheduler, a plurality of parallel processing chiplets (PPCs) to process tasks, and a central processing chiplet (CPC) “the plurality of chiplets can include a sensor data input chiplet, a central chiplet, and a number of additional workload processing chiplets (e.g., machine learning (ML) accelerator chiplet, autonomous drive chiplets, high-bandwidth memory chiplets, general compute chiplets, and the like) [0003]”; “the workload processing chiplets can continuously monitor and update the reservation table provided in the shared memory of the SoC [0006]”; “the processors 340 and workload processing chiplets 320 can execute multiple independent workload pipelines in parallel, with each workload pipeline including a plurality of workloads to be executed in a deterministic manner. [0054]”; “the central chiplet 300 can include a shared memory 360 storing a reflex program 330…the reflex program 330 can comprise a set of instructions for executing reflex workloads in independent pipelines. The reflex workloads can comprise sensor data acquisition, sensor fusion, and inference tasks that facilitate scene understanding [0047]” showing that the CPC 340 execute this narrower category of workloads distinct from general workload pipelines executed by the PPCs.
Piednoel doesn’t teach wherein: the scheduler assigns the tasks to the plurality of PPCs such that a task associated with data assigned to the CPC is assigned to at least one of the plurality of PPCs.
However, in analogous art, Jahagirdar teaches wherein: the scheduler assigns the tasks to the plurality of cores such that a task associated with data assigned to the first core is assigned to at least one of the plurality of second cores “an operating system 148 that includes a scheduler 150 may schedule one or more threads 152 for execution at the first core 104. [0021]”; “The second instruction set 130 may include at least one particular instruction (e.g., a multimedia instruction) that the second core 106 is capable of executing but that the first core 104 is incapable of executing. [0019]”; “the first core 104 may be a lower power usage and lower performance core while the second core 106 may be a higher power usage and higher performance core. [0029]”; “The processor 102 may determine... that the first core 104 is incapable of executing one or more of the instructions 154 and that the second core 106 is capable of executing the instructions 154. [0028]”; and in response “may migrate 156...the threads 152 from one core (e.g., the first core 104) to another core (e.g., the second core 106) [0021]”. Examiner’s Note: Applied to Piednoel ‘s architecture, the scheduler assigns a task associated with data assigned to the CPC (lower capability) to a workload processing chiplet capable of executing it (PPC), in an assignment pattern governed by chiplet capability rather than fixed data to memory arrangement, and thus different from the first assignment order.
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to modify Piednoel’s multi chiplet processor to incorporate Jahagirdar ‘s capability based scheduling. A person having ordinary skill in the art would have been motivated to make this combination because Jahagirdar established that instruction not supported by a given core cannot be executed at the core [0019] unless migrated to a core that supports it. Applying this same functional necessity to Piednoel’s system, where the central chip cannot execute general workload tasks efficiently, a person would have recognized the need to hand off the task to a capable chiplet.
With regards to claim 15, Piednoel teaches a method of assigning tasks in a multi-chiplet processor including a plurality of parallel processing chiplets (PPCs) and a central processing chiplet (CPC), “the plurality of chiplets can include a sensor data input chiplet, a central chiplet, and a number of additional workload processing chiplets (e.g., machine learning (ML) accelerator chiplet, autonomous drive chiplets, high-bandwidth memory chiplets, general compute chiplets, and the like) [0003]”; “the workload processing chiplets can continuously monitor and update the reservation table provided in the shared memory of the SoC [0006]”; “the processors 340 and workload processing chiplets 320 can execute multiple independent workload pipelines in parallel, with each workload pipeline including a plurality of workloads to be executed in a deterministic manner. [0054]”; “the central chiplet 300 can include a shared memory 360 storing a reflex program 330…the reflex program 330 can comprise a set of instructions for executing reflex workloads in independent pipelines. The reflex workloads can comprise sensor data acquisition, sensor fusion, and inference tasks that facilitate scene understanding [0047]” showing that the CPC 340 execute this narrower category of workloads distinct from general workload pipelines executed by the PPCs.
Piednoel teaches assigning data associated with the tasks to memories associated with the plurality of PPCs and the CPC in a first assignment order “The sensor data input chiplet 210 can automatically dump the received sensor data as it's received into a cache memory 231 of the central chiplet 220 [0036]"; “The autonomous drive chiplet 240 can be connected to a dedicated HBM-RAM chiplet 235 in which the autonomous drive chiplet 240 can publish all status information, variables, statistical information, and/or processed sensor data as processed by the autonomous drive chiplet 240 [0040]”; “the sensor data input chiplet 310 of FIG.3 can correspond to the sensor data input chiplet 210 shown in FIG. 2, and the workload processing chiplets 320 shown in FIG. 3, can correspond to the general compute chiplets 245, ML accelerator chiplet 250, and/or the autonomous drive chiplet 240 shown in FIG. 2. [0046]” Examiner’s Note: Spec [0023] (“order” or “assignment order” do not necessarily refer to a sequence in time but rather an order, or pattern, of assignments relative to the particular components). Sensor data is consistently dumped to the central chiplet’s memory, and the autonomous drive chiplet data is consistently dumped into its own memory. That consistent affinity between a given category of data and a given memory pattern satisfies “first assignment order” under BRI. The order here is analogous to the pattern, of assignments relative to the particular components, rather than timing of the assignments.
Piednoel doesn’t teach assigning the tasks to the plurality of PPCs in a second assignment order different from the first assignment order such that a task associated with data assigned to the CPC is assigned to at least one of the plurality of PPCs.
However, in analogous art, Jahagirdar teaches assigning the tasks to the plurality of cores in a second assignment order different from the first assignment order such that a task associated with data assigned to the first core is assigned to at least one of the plurality of second cores “an operating system 148 that includes a scheduler 150 may schedule one or more threads 152 for execution at the first core 104. [0021]”; “The second instruction set 130 may include at least one particular instruction (e.g., a multimedia instruction) that the second core 106 is capable of executing but that the first core 104 is incapable of executing. [0019]”; “the first core 104 may be a lower power usage and lower performance core while the second core 106 may be a higher power usage and higher performance core. [0029]”; “The processor 102 may determine... that the first core 104 is incapable of executing one or more of the instructions 154 and that the second core 106 is capable of executing the instructions 154. [0028]”; and in response “may migrate 156...the threads 152 from one core (e.g., the first core 104) to another core (e.g., the second core 106) [0021]”. Examiner’s Note: Applied to Piednoel ‘s architecture, the scheduler assigns a task associated with data assigned to the CPC (lower capability) to a workload processing chiplet capable of executing it (PPC), in an assignment pattern governed by chiplet capability rather than fixed data to memory arrangement, and thus different from the first assignment order.
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to modify Piednoel’s method so that the scheduler assigns a task associated with data at the central chiplet to a workload processing chiplet instead, consistent with Jahagirdar ‘s capability based scheduling. A person having ordinary skill in the art would have been motivated to make this combination because Jahagirdar established that instruction not supported by a given core cannot be executed at the core [0019] unless migrated to a core that supports it. Applying this same functional necessity to Piednoel’s system, where the central chip cannot execute general workload tasks efficiently, a person would have recognized the need to hand off the task to a capable chiplet.
Claim(s) 2, 9, and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Piednoel in view of Jahagirdar, further in view of Jayasena et al Pub. No. US 20160048327 A1 (hereafter Jayasena).
With regards to claim 2, Piednoel and Jahagirdar teach the apparatus of claim 1.
Piednoel and Jahagirdar do not teach wherein the first assignment order sequentially assigns the data to the memories associated with the plurality of PPCs and the CPC.
However, in analogous art, Jayasena teaches sequentially assigns the data to the memories: “FIG. 3(a) illustrates a fine-grain interleaving pattern and includes memory devices 301a-d [0039]”; “the received data may be stored consecutively in memory device 301a, in memory device 301b and then in memory device 301c…the subsequently received data may be stored consecutively, starting in memory device 301d, and then returning to memory device 301a, followed by memory device 301b and completing in memory device 301c [0040]”; “each memory device 401a-d may include a processor, such as processor 201…Processor 201 may have higher-speed access only to the encompassing memory device [0047]”; “Segment 420 may be organized in a fine-grain interleaving pattern, as shown by the dashed lines”. Examiner’s Note: Under BRI, the instant application’s spec[0023] states that “the terms “order” or “assignment order” do not necessarily refer to a sequence in time but rather an order, or pattern, of assignments relative to the particular components” and gives a ‘Z’ order example where “data 1 201 is assigned to HBM 226-1, data 2 202 is assigned to HBM 226-2, data 3 203 is assigned to HBM 226-3, data 4 204 is assigned to HBM 226-4, data 5 205 is assigned to HBM 226-1, and so on”. Jayasena teaches the same consecutive, cyclical pattern across memories associated with respective processors. Applied to the Piednoel/Jahagirdar combination, results in wherein the first assignment order sequentially assigns the data to the memories associated with the plurality of PPCs and the CPC.
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to modify the combined system of claim 1 to incorporate the consecutive multi device storage patter Jayasena teaches. A person having ordinary skill in the art would have been motivated to make this combination because as Jayasena teaches that storing data consecutively across separate memory devices lets a processor “access memory devices 105a-d in parallel, thereby reading or writing data up to four times faster than if all data was stored in a single memory device. [0041]” showing that spreading data across multiple memories in this pattern improves efficiency.
With regards to claim 9, Piednoel and Jahagirdar teach the apparatus of claim 8.
Piednoel and Jahagirdar do not teach wherein the processor sequentially assigns data to memories associated with the plurality of PPCs and the CPC.
However, in analogous art, Jayasena teaches sequentially assigns the data to the memories: “FIG. 3(a) illustrates a fine-grain interleaving pattern and includes memory devices 301a-d [0039]”; “the received data may be stored consecutively in memory device 301a, in memory device 301b and then in memory device 301c…the subsequently received data may be stored consecutively, starting in memory device 301d, and then returning to memory device 301a, followed by memory device 301b and completing in memory device 301c [0040]”; “each memory device 401a-d may include a processor, such as processor 201…Processor 201 may have higher-speed access only to the encompassing memory device [0047]”; “Segment 420 may be organized in a fine-grain interleaving pattern, as shown by the dashed lines”. Examiner’s Note: Under BRI, the instant application’s spec[0023] states that “the terms “order” or “assignment order” do not necessarily refer to a sequence in time but rather an order, or pattern, of assignments relative to the particular components” and gives a ‘Z’ order example where “data 1 201 is assigned to HBM 226-1, data 2 202 is assigned to HBM 226-2, data 3 203 is assigned to HBM 226-3, data 4 204 is assigned to HBM 226-4, data 5 205 is assigned to HBM 226-1, and so on”. Jayasena teaches the same consecutive, cyclical pattern across memories associated with respective processors. Applied to the Piednoel/Jahagirdar combination, results in wherein the first assignment order sequentially assigns the data to the memories associated with the plurality of PPCs and the CPC.
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to modify the combined system of claim 8 to incorporate the consecutive multi device storage patter Jayasena teaches. A person having ordinary skill in the art would have been motivated to make this combination because as Jayasena teaches that storing data consecutively across separate memory devices lets a processor “access memory devices 105a-d in parallel, thereby reading or writing data up to four times faster than if all data was stored in a single memory device. [0041]” showing that spreading data across multiple memories in this pattern improves efficiency.
With regards to claim 16, Piednoel and Jahagirdar teach the method of claim 15.
Piednoel and Jahagirdar do not teach wherein the first assignment order sequentially assigns the data to the memories associated with the plurality of PPCs and the CPC. .
However, in analogous art, Jayasena teaches sequentially assigns the data to the memories: “FIG. 3(a) illustrates a fine-grain interleaving pattern and includes memory devices 301a-d [0039]”; “the received data may be stored consecutively in memory device 301a, in memory device 301b and then in memory device 301c…the subsequently received data may be stored consecutively, starting in memory device 301d, and then returning to memory device 301a, followed by memory device 301b and completing in memory device 301c [0040]”; “each memory device 401a-d may include a processor, such as processor 201…Processor 201 may have higher-speed access only to the encompassing memory device [0047]”; “Segment 420 may be organized in a fine-grain interleaving pattern, as shown by the dashed lines”. Examiner’s Note: Under BRI, the instant application’s spec[0023] states that “the terms “order” or “assignment order” do not necessarily refer to a sequence in time but rather an order, or pattern, of assignments relative to the particular components” and gives a ‘Z’ order example where “data 1 201 is assigned to HBM 226-1, data 2 202 is assigned to HBM 226-2, data 3 203 is assigned to HBM 226-3, data 4 204 is assigned to HBM 226-4, data 5 205 is assigned to HBM 226-1, and so on”. Jayasena teaches the same consecutive, cyclical pattern across memories associated with respective processors. Applied to the Piednoel/Jahagirdar combination, results in wherein the first assignment order sequentially assigns the data to the memories associated with the plurality of PPCs and the CPC.
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to modify the combined system of claim 15 to incorporate the consecutive multi device storage patter Jayasena teaches. A person having ordinary skill in the art would have been motivated to make this combination because as Jayasena teaches that storing data consecutively across separate memory devices lets a processor “access memory devices 105a-d in parallel, thereby reading or writing data up to four times faster than if all data was stored in a single memory device. [0041]” showing that spreading data across multiple memories in this pattern improves efficiency.
Claim(s) 3, 4, 10, 11, 17, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Piednoel in view of Jahagirdar further in view of Chan et al Pub. No. US 20090276781 A1 (hereafter Chan).
With regards to claim 3, Piednoel and Jahagirdar teach the apparatus of claim 1.
Piednoel and Jahagirdar do not teach wherein the second assignment order sequentially assigns a first set of the tasks to the plurality of PPCs while skipping a task that would be assigned to the CPC if the CPC were included in the second assignment order.
However, in analogous art, Chan teaches wherein the second assignment order sequentially assigns a first set of the tasks to the plurality of nodes while skipping a task that would be assigned to the node if the node were included in the second assignment order a scheduler that processes a list of jobs in sequence, moving one to the next “the current scheduler pass moves to the next job and processing returns to block 804…if a job cannot be scheduled, it is skipped, and the scheduler considers other jobs in the list [0045]”. Examiner’s Note: Under BRI, the second assignment order established in claim 1 only assigns tasks to PPCs, the CPC is excluded. A task tied to CPC’s data would go there if the CPC were included, so its’s skipped instead. Chan’s job that “cannot be scheduled” is that skipped task. The scheduler passes over it and moves to the next job. Applied to Piednoel/ Jahagirdar, the combination teaches wherein the second assignment order sequentially assigns a first set of the tasks to the plurality of PPCs while skipping a task that would be assigned to the CPC if the CPC were included in the second assignment order.
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to modify the Piednoel/ Jahagirdar combination to incorporate Chan’s scan and skip scheduling mechanism. A person having ordinary skill in the art would have been motivated to make this combination because Chan itself teaches that upon reaching a job which cannot be scheduled, that job “it is skipped, and the scheduler considers other jobs in the list [0045]”, teaching that proceeding through the list and skipping an unschedulable item avoids stalling assignment of the remaining items.
With regards to claim 4, Piednoel, Jahagirdar, and Chan teaches the apparatus of claim 3.
Chan further teaches the task that would be assigned to the CPC if the CPC were included in the second assignment order is sequentially assigned to the plurality of PPCs after sequentially assigning the first set of the tasks “At the next pass, all idle jobs are again checked to see if they can now run (due to changes in node availability) [0045]”; “The job queue 106 may also include a state column 212 indicating whether a job is running (R) or idle (I) [0025]”. Examiner’s Note: the skipped job isn’t dropped. Chan tracks it as “idle” and picks it back up on the next pass, once the rest of the list’s been handled. Applied to the combined system of claim 3, the task that would be assigned to the CPC if the CPC were included in the second assignment order is sequentially assigned to the plurality of PPCs after sequentially assigning the first set of the tasks, consistent with Chen next job reassignment of idle jobs.
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to modify the claim 3 combination to incorporate Chan’s next pass revisiting mechanism. A person having ordinary skill in the art would have been motivated to make this combination because Chan itself teaches that upon reaching a job which cannot be scheduled, that job “At the next pass, all idle jobs are again checked to see if they can now run [0045]”, teaching that skipped item should be revisited once the rest of the list has been processed, rather than left unassigned.
With regards to claim 10, Piednoel and Jahagirdar teach the apparatus of claim 8.
Piednoel and Jahagirdar do not teach wherein the scheduler sequentially assigns a first set of the tasks to the plurality of PPCs while skipping a task that would be assigned to the CPC if the CPC were included in the sequential assignment.
However, in analogous art, Chan teaches wherein the second assignment order sequentially assigns a first set of the tasks to the plurality of nodes while skipping a task that would be assigned to the node if the node were included in the second assignment order a scheduler that processes a list of jobs in sequence, moving one to the next “the current scheduler pass moves to the next job and processing returns to block 804…if a job cannot be scheduled, it is skipped, and the scheduler considers other jobs in the list [0045]”. Examiner’s Note: Applied to Piednoel’s architecture, the CPC task still ends up on a PPC (capable core) consistent with claim 8. The skip here just means it’s not part of the first pass, not that it’s left unassigned. PPCs get tasks in that pass; the CPC is the lower capability core that task would otherwise tie to. Chan supplies a scheduler that moves job to job and when it hits one that cant be scheduled, it’s skipped and scheduler moves on to the next resulting in, wherein the scheduler sequentially assigns a first set of the tasks to the plurality of PPCs while skipping a task that would be assigned to the CPC if the CPC were included in the sequential assignment.
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to modify the Piednoel/ Jahagirdar combination to incorporate Chan’s scan and skip scheduling mechanism. A person having ordinary skill in the art would have been motivated to make this combination because Chan itself teaches that upon reaching a job which cannot be scheduled, that job “it is skipped, and the scheduler considers other jobs in the list [0045]”, teaching that proceeding through the list and skipping an unschedulable item avoids stalling assignment of the remaining items.
With regards to claim 11, Piednoel, Jahagirdar, and Chan teaches the apparatus of claim 10.
Chan further teaches the task that would be assigned to the CPC if the CPC were included in the second assignment order is sequentially assigned to the plurality of PPCs after sequentially assigning the first set of the tasks “At the next pass, all idle jobs are again checked to see if they can now run (due to changes in node availability) [0045]”; “The job queue 106 may also include a state column 212 indicating whether a job is running (R) or idle (I) [0025]”. Examiner’s Note: the skipped job isn’t dropped. Chan tracks it as “idle” and picks it back up on the next pass, once the rest of the list’s been handled. Applied to the combined system of claim 10, wherein the task that would be assigned to the CPC if the CPC were included in the sequential assignment is sequentially assigned to the plurality of PPCs after sequentially assigning the first set of the tasks, consistent with Chen next job reassignment of idle jobs.
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to modify claim 10’s combination to incorporate Chan’s next pass revisiting mechanism. A person having ordinary skill in the art would have been motivated to make this combination because Chan itself teaches that upon reaching a job which cannot be scheduled, that job “At the next pass, all idle jobs are again checked to see if they can now run [0045]”, teaching that skipped item should be revisited once the rest of the list has been processed, rather than left unassigned.
With regards to claim 17, Piednoel and Jahagirdar teach the method of claim 15.
Piednoel and Jahagirdar do not teach wherein the second assignment order sequentially assigns a first set of the tasks to the plurality of PPCs while skipping a task that would be assigned to the CPC if the CPC were included in the second assignment order.
However, in analogous art, Chan teaches wherein the second assignment order sequentially assigns a first set of the tasks to the plurality of nodes while skipping a task that would be assigned to the node if the node were included in the second assignment order a scheduler that processes a list of jobs in sequence, moving one to the next “the current scheduler pass moves to the next job and processing returns to block 804…if a job cannot be scheduled, it is skipped, and the scheduler considers other jobs in the list [0045]”. Examiner’s Note: Under BRI, the second assignment order established in claim 1 only assigns tasks to PPCs, the CPC is excluded. A task tied to CPC’s data would go there if the CPC were included, so its’s skipped instead. Chan’s job that “cannot be scheduled” is that skipped task. The scheduler passes over it and moves to the next job. Applied to Piednoel/ Jahagirdar, the combination teaches wherein the second assignment order sequentially assigns a first set of the tasks to the plurality of PPCs while skipping a task that would be assigned to the CPC if the CPC were included in the second assignment order.
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to modify the Piednoel/ Jahagirdar combination to incorporate Chan’s scan and skip scheduling mechanism. A person having ordinary skill in the art would have been motivated to make this combination because Chan itself teaches that upon reaching a job which cannot be scheduled, that job “it is skipped, and the scheduler considers other jobs in the list [0045]”, teaching that proceeding through the list and skipping an unschedulable item avoids stalling assignment of the remaining items.
With regards to claim 18, Piednoel, Jahagirdar, and Chan teaches the method of claim 17.
Chan further teaches the task that would be assigned to the CPC if the CPC were included in the second assignment order is sequentially assigned to the plurality of PPCs after sequentially assigning the first set of the tasks “At the next pass, all idle jobs are again checked to see if they can now run (due to changes in node availability) [0045]”; “The job queue 106 may also include a state column 212 indicating whether a job is running (R) or idle (I) [0025]”. Examiner’s Note: the skipped job isn’t dropped. Chan tracks it as “idle” and picks it back up on the next pass, once the rest of the list’s been handled. Applied to the combined system of claim 3, the task that would be assigned to the CPC if the CPC were included in the second assignment order is sequentially assigned to the plurality of PPCs after sequentially assigning the first set of the tasks, consistent with Chen next job reassignment of idle jobs.
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to modify claim 17’s combination to incorporate Chan’s next pass revisiting mechanism. A person having ordinary skill in the art would have been motivated to make this combination because Chan itself teaches that upon reaching a job which cannot be scheduled, that job “At the next pass, all idle jobs are again checked to see if they can now run [0045]”, teaching that skipped item should be revisited once the rest of the list has been processed, rather than left unassigned.
Claim(s) 5, 6, 12, 13, 19, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Piednoel in view of Jahagirdar further in view of LeBeane et al Pub. No. US 20180081715 A1 (hereafter LeBeane).
With regards to claim 5, Piednoel and Jahagirdar teach the apparatus of claim 1.
Piednoel and Jahagirdar do not teach wherein the second assignment order assigns tasks to the plurality of PPCs to optimize correspondence between the data associated with the tasks that is assigned to the memories associated with the plurality of PPCs and the tasks assigned to the plurality of PPCs.
However, in analogous art, LeBeane teaches assign tasks to compute device to optimize correspondence between the data assigned to a device and with the tasks that is assigned to that device : “In the data-locality policy, the scheduler 208 assigns tasks to compute devices 202 based on data-locality. Data-locality refers to the locality of data used by the task with respect to the compute device 202 to which the task 206 is assigned…data that is local is assigned a particular score and data that is not local is assigned a different, lower score (such as 0) [0027]”. Examiner’s Note: Applied to the combined system of claim 1 results in, wherein the second assignment order assigns tasks to the plurality of PPCs to optimize correspondence between the data associated with the tasks that is assigned to the memories associated with the plurality of PPCs and the tasks assigned to the plurality of PPCs.
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to modify the combined system of Piednoel/ Jahagirdar to incorporate the data locality scheduling taught by LeBeane. A person having ordinary skill in the art would have been motivated to make this combination because as LeBeane presents data locality as one of several selectable scheduling policies and states that this policy “favors compute devices…for which such local data exists [0027]”
With regards to claim 6, Piednoel and Jahagirdar teach the apparatus of claim 1.
Piednoel and Jahagirdar do not teach wherein the scheduler is to reassign a task to a different PPC of the plurality of PPCs to balance a number of tasks assigned to each of the plurality of PPCs.
However, in analogous art, LeBeane teaches reassign a task to a different compute device to balance a number of tasks assigned to each compute device: “a device 142 is performing a set of work and is aware that another device 142 is less busy. In response, the busy device 142 transmits one or more tasks to the less busy device 142 [0014]”. Examiner’s Note: Applied to the combined system of claim 1 results in, wherein the scheduler is to reassign a task to a different PPC of the plurality of PPCs to balance a number of tasks assigned to each of the plurality of PPCs.
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to modify the combined system of claim 1 to incorporate the busy to less busy task reassignment taught by LeBeane. A person having ordinary skill in the art would have been motivated to make this combination because LeBeane itself teaches that “a device 142 is performing a set of work and is aware that another device 142 is less busy. In response, the busy device 142 transmits one or more tasks to the less busy device 142 [0014] and identifies transmitting tasks to the less busy device as a deliberate “load balancing” policy used for balancing tasks across devices.
With regards to claim 12, Piednoel and Jahagirdar teach the apparatus of claim 8.
Piednoel and Jahagirdar do not teach wherein the scheduler assigns tasks to the plurality of PPCs to optimize correspondence between data associated with the tasks that is assigned to memories associated with the plurality of PPCs and the tasks assigned to the plurality of PPCs.
However, in analogous art, LeBeane teaches assign tasks to compute device to optimize correspondence between the data assigned to a device and with the tasks that is assigned to that device : “In the data-locality policy, the scheduler 208 assigns tasks to compute devices 202 based on data-locality. Data-locality refers to the locality of data used by the task with respect to the compute device 202 to which the task 206 is assigned…data that is local is assigned a particular score and data that is not local is assigned a different, lower score (such as 0) [0027]”. Examiner’s Note: Applied to the combined system of claim 8 results in, wherein the scheduler assigns tasks to the plurality of PPCs to optimize correspondence between data associated with the tasks that is assigned to memories associated with the plurality of PPCs and the tasks assigned to the plurality of PPCs.
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to modify the combined system of Piednoel/ Jahagirdar to incorporate the data locality scheduling taught by LeBeane. A person having ordinary skill in the art would have been motivated to make this combination because as LeBeane teaches “Data-locality refers to the locality of data used by the task with respect to the compute device 202 to which the task 206 is assigned” and that local data placement “is assigned a particular score and data that is not local is assigned a different, lower score (such as 0) [0027]” teaching that scheduling a task to the device holding its data is a deliberate scored objective.
With regards to claim 13, Piednoel and Jahagirdar teach the apparatus of claim 8.
Piednoel and Jahagirdar do not teach wherein the scheduler reassigns a task to a different PPC of the plurality of PPCs in order to balance a number of tasks assigned to each of the plurality of PPCs.
However, in analogous art, LeBeane teaches reassign a task to a different compute device to balance a number of tasks assigned to each compute device : “a device 142 is performing a set of work and is aware that another device 142 is less busy. In response, the busy device 142 transmits one or more tasks to the less busy device 142 [0014]”. Examiner’s Note: Applied to the combined system of claim 8 results in, wherein the scheduler reassigns a task to a different PPC of the plurality of PPCs in order to balance a number of tasks assigned to each of the plurality of PPCs.
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to modify the combined system of of Piednoel/ Jahagirdar to incorporate the busy to less busy task reassignment taught by LeBeane. A person having ordinary skill in the art would have been motivated to make this combination because LeBeane itself teaches that “a device 142 is performing a set of work and is aware that another device 142 is less busy. In response, the busy device 142 transmits one or more tasks to the less busy device 142 [0014] and identifies transmitting tasks to the less busy device as a deliberate “load balancing” policy used for balancing tasks across devices.
With regards to claim 19, Piednoel and Jahagirdar teach the method of claim 15.
Piednoel and Jahagirdar do not teach wherein the second assignment order assigns tasks to the plurality of PPCs to optimize correspondence between the data associated with the tasks that is assigned to the memories associated with the plurality of PPCs and the tasks assigned to the plurality of PPCs.
However, in analogous art, LeBeane teaches assign tasks to compute device to optimize correspondence between the data assigned to a device and with the tasks that is assigned to that device : “In the data-locality policy, the scheduler 208 assigns tasks to compute devices 202 based on data-locality. Data-locality refers to the locality of data used by the task with respect to the compute device 202 to which the task 206 is assigned…data that is local is assigned a particular score and data that is not local is assigned a different, lower score (such as 0) [0027]”. Examiner’s Note: Applied to the combined system of claim 15 results in, wherein the second assignment order assigns tasks to the plurality of PPCs to optimize correspondence between the data associated with the tasks that is assigned to the memories associated with the plurality of PPCs and the tasks assigned to the plurality of PPCs.
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to modify the combined system of Piednoel/ Jahagirdar to incorporate the data locality scheduling taught by LeBeane. A person having ordinary skill in the art would have been motivated to make this combination because as LeBeane teaches “Data-locality refers to the locality of data used by the task with respect to the compute device 202 to which the task 206 is assigned” and that local data placement “is assigned a particular score and data that is not local is assigned a different, lower score (such as 0) [0027]” teaching that scheduling a task to the device holding its data is a deliberate scored objective.
With regards to claim 20, Piednoel and Jahagirdar teach the method of claim 15.
Piednoel and Jahagirdar do not teach further comprising reassigning a task to a different PPC of the plurality of PPCs in order to balance a number of tasks assigned to each of the plurality of PPCs.
However, in analogous art, LeBeane teaches reassign a task to a different compute device to balance a number of tasks assigned to each compute device : “a device 142 is performing a set of work and is aware that another device 142 is less busy. In response, the busy device 142 transmits one or more tasks to the less busy device 142 [0014]”. Examiner’s Note: Applied to the combined system of claim 15 results in, further comprising reassigning a task to a different PPC of the plurality of PPCs in order to balance a number of tasks assigned to each of the plurality of PPCs.
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to modify the combined system of of Piednoel/ Jahagirdar to incorporate the busy to less busy task reassignment taught by LeBeane. A person having ordinary skill in the art would have been motivated to make this combination because LeBeane itself teaches that “a device 142 is performing a set of work and is aware that another device 142 is less busy. In response, the busy device 142 transmits one or more tasks to the less busy device 142 [0014] teaching reassigning tasks toward less busy processing units balances load across the available units.
Claim(s) 7 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Piednoel in view of Jahagirdar, in view of LeBeane, further in view of He et al Pub. No. US 20140181825 A1 (hereafter He).
With regards to claim 7, Piednoel, Jahagirdar, and LeBeane teach the apparatus of claim 6.
Piednoel, Jahagirdar, and LeBeane do not teach wherein the scheduler is to reassign the task to a different PPC of the plurality of PPCs when a different one of the tasks is cancelled.
However, in analogous art, He teaches reassigns the task to a different processing module when a different one of the tasks is cancelled “At time t.sub.5, assume that the job J.sub.1 that is running on the processing module C ends, e.g., either because its work is done, or because its allotted processing time has expired, or because it has been suspended, or because it terminates for any other reason. At time t.sub.6, the scheduling module 118 responds to this event by transferring the most-urgent in-progress job from a "smaller" processing module to the processing module C [0051]”; “the scheduling module 118 determines whether a job that is running on one of the processing modules has terminated for any reason described above. This termination leaves a newly-vacated processing module…the scheduling module 118 moves the in-progress job to the newly-vacated module.[0056]”. Examiner’s Note: Applied to the combined system of claim 6 results in, wherein the scheduler is to reassign the task to a different PPC of the plurality of PPCs when a different one of the tasks is cancelled.
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to modify the combined system of claim 6 to incorporate the termination triggered job migration taught by He. A person having ordinary skill in the art would have been motivated to make this combination because He taches that when a job “terminates for any other reason”, the scheduler “responds to this event by transferring” another in progress job into the newly vacated processing module teaching that a processing unit freed by a task ending should be filled with another task rather than left idle.
With regards to claim 14, Piednoel, Jahagirdar, and LeBeane teach the apparatus of claim 13.
Piednoel, Jahagirdar, and LeBeane do not teach wherein the scheduler reassigns the task to a different PPC of the plurality of PPCs when a different one of the tasks is cancelled.
However, in analogous art, He teaches reassigns the task to a different processing module when a different one of the tasks is cancelled: “At time t.sub.5, assume that the job J.sub.1 that is running on the processing module C ends, e.g., either because its work is done, or because its allotted processing time has expired, or because it has been suspended, or because it terminates for any other reason. At time t.sub.6, the scheduling module 118 responds to this event by transferring the most-urgent in-progress job from a "smaller" processing module to the processing module C [0051]”; “the scheduling module 118 determines whether a job that is running on one of the processing modules has terminated for any reason described above. This termination leaves a newly-vacated processing module…the scheduling module 118 moves the in-progress job to the newly-vacated module.[0056]”. Examiner’s Note: Applied to the combined system of claim 13 results in, wherein the scheduler reassigns the task to a different PPC of the plurality of PPCs when a different one of the tasks is cancelled.
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to modify the combined system of claim 13 to incorporate the termination triggered job migration taught by He. A person having ordinary skill in the art would have been motivated to make this combination because He taches that when a job “terminates for any other reason”, the scheduler “responds to this event by transferring” another in progress job into the newly vacated processing module teaching that a processing unit freed by a task ending should be filled with another task rather than left idle.
Conclusion
US 12099439 B2
Teaches
Pulling multiple 2D arrays elements in one memory cycle via stride/transpose addressing
US 20220319089 A1
Teaches
Auto-splits one task’s workgroup across chiplets, syncs when done
US 20230004363 A1
Teaches
Runs stream jobs as plain OS processes instead of master/worker
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MEZMURE DAWIT whose telephone number is (571)270-5581. The examiner can normally be reached Mon-Fri 7:30am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Bradley Teets can be reached at 571-272-3338. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. visit: https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MEZMURE DAWIT/Examiner, Art Unit 2197
/BRADLEY A TEETS/Supervisory Patent Examiner, Art Unit 2197
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