DETAILED ACTION
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
Claims 1-3, 7-8 and 13-15 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-21 of U.S. Patent No. 11,960,436. Although the claims at issue are not identical, they are not patentably distinct from each other because the present application simply claims a broader scope from the ’436 patent.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 7-9, 11-17 and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Seo (US 10,719,105).
Referring to claims 1, 8 and 15, Seo discloses a method of synchronizing system state data (fig. 10, between first and second processor) executable by at least one hardware processor (fig. 14, first/second processor 121/123) of a system (fig. 1, system 100), the method comprising:
executing a first processor (fig. 10, first processor 121) of the hardware processor based on initial state data (fig. 10, turn-on state 1001), wherein the initial state data represents an initial system state (18:49-52, turn-on state) of the system;
detecting (fig. 10, receive external input mode switch request 1003), prior to a predefined progress position (fig. 10, sleep mode 1007 & operate in external input mode 1013; 18:49-19:17, before state switched), a first change in state (fig. 10, turn off display device 1005 & switch to external input mode 1006) of the system by the first processor using a sensor (fig. 7, sensing data 707; 1:64-2:2, sensor), the first change in state being added to a first record of modified state data (fig. 10, instruct switching to external input mode 1006) until the predefined progress position;
designating the first record of modified state data as second state data (fig. 10, operate in external input mode 1013) based on reaching the predefined progress position; and
transitioning from execution of the first processor based on the initial state data (fig. 10, transition from turn-on state 1001) to execution of the first processor based on the second state data (fig. 10, transition to external input mode 1013).
As to claims 2, 11, 16 and 19, Seo discloses the method of claim 1, wherein designating comprises: communicating (fig. 10, instruct switching to external input mode 1006) the second state data to a second processor (fig. 10, second processor 123) of the hardware processor, wherein the method comprises: transitioning (fig. 10, transitioning from turn-state 1001 to sleep mode 1007 and external input mode 1013) from execution of the second processor based on the initial state data, to execution of the second processor based on the second state data.
As to claims 3, 12 and 20, Seo discloses the method of claim 2, wherein the method comprises: receiving an acknowledgement (fig. 10, transition from instruct switching 1006 to operate in external input mode 1013) that the second processor received the second state data, wherein transitioning of the second processor is based on receipt of the acknowledgement (fig. 9, external mode request 905).
As to claims 4, 9 and 17, Seo discloses the method of claim 1, comprising: detecting, after the predefined progress position, second change in state (fig. 10, change from external input mode 1013 to turn on display device 1009/normal input mode 1017) of the system by the first processor using sensor (fig. 10, detect predetermined condition 1015), the second change in state being added to a second record of modified state data (fig. 10, activate first processor 1016 & operate in normal input mode 1017).
As to claims 7 and 13, Seo discloses the method of claim 1, wherein the first change in state include a physical engagement (fig. 2, device 200/201 in four different states; 7:3-8:31) with a device (fig. 2, device 200/201) including the hardware processor.
As to claim 14, Seo discloses the system of claim 8, wherein the system is to activate the synchronization manager (fig. 3, sensor module 176), based on the sensor detecting the first change in state, the synchronization manager being operable to conduct designation and transition (fig. 3, senor module 176 to first/second processors 123/121).
Allowable Subject Matter
Claims 5-6, 10 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The claim limitation of “after reaching the predefined progress position, the initial state data is stored in a first state data portion of a first state data buffer associated with the first processor, the second state data is stored in a second portion of the first state data buffer, and the second record of modified state data is stored in a modified state data portion of the first state data buffer, wherein transitioning includes transitioning from execution of the first processor on the first state data portion of the first state data buffer to execution of the first processor on the second portion of the first state data buffer” as required in dependent claims 5, 10 and 18.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to examiner Cheng-Yuan Tseng whose telephone number is (571)272-9772, and fax number is (571)273-9772. The examiner can normally be reached on Monday through Friday from 09:00 to 17:30 Eastern Time. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alicia Harrington can be reached on (571)272-2330. The fax phone number for the organization where this application or proceeding is assigned is (571)273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at (866)217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call (800)786-9199 (IN USA OR CANADA) or (571)272-1000.
/CHENG YUAN TSENG/Primary Examiner, Art Unit 2615