Prosecution Insights
Last updated: April 19, 2026
Application No. 18/612,599

ELECTRONIC DEVICE AND METHOD FOR CONTROLLING DATA THROUGHPUT BASED ON HEAT GENERATION IN ELECTRONIC DEVICE

Non-Final OA §103§DP
Filed
Mar 21, 2024
Examiner
RASHID, WISSAM
Art Unit
2195
Tech Center
2100 — Computer Architecture & Software
Assignee
Samsung Electronics Co., Ltd.
OA Round
5 (Non-Final)
88%
Grant Probability
Favorable
5-6
OA Rounds
2y 11m
To Grant
99%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allow Rate
572 granted / 654 resolved
+32.5% vs TC avg
Moderate +12% lift
Without
With
+12.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 11m
Avg Prosecution
25 currently pending
Career history
679
Total Applications
across all art units

Statute-Specific Performance

§101
9.7%
-30.3% vs TC avg
§103
44.9%
+4.9% vs TC avg
§102
12.4%
-27.6% vs TC avg
§112
19.5%
-20.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 654 resolved cases

Office Action

§103 §DP
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This is a Non-Final Office Action responsive to Applicant’s Request for Continued Examination filed 12/31/2025. Claims 1-5, 7, 8, and 10-22 are pending. Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 1-5, 7, 8, and 10-22 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11977931 (hereinafter ‘931). Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the ‘931 patent anticipate the claims of the instant application. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1, 13, and 20-22 are rejected under 35 U.S.C. 103 as being unpatentable over Dorsey et al. (US 8170606) in view of Lassa et al. (US 2012/0331207). With respect to claim 1, Dorsey discloses: at least one antenna (col. 14, lines 6-7, “…the radio/modem…have…antennas…”); first communication circuitry configured to provide first communication via the at least one antenna (col. 14 lines 4-24, col. 13, lines 27-29, “radio transmission” corresponds to “first communication”, “radio/modem subsystem” corresponds to “first communication circuitry”); at least one temperature sensor (col. 14, lines 45-62, “temperature sensors” corresponds to Applicant’s “temperature sensor”); memory storing computer-executable instructions (col. 6, lines 24-25, “memory comprises a plurality of instructions…executed...processing device”); and one or more processors operationally connected to the first communication circuitry, the at least one temperature sensor, and the memory (Fig. 1, 102A corresponds to processor, 108 corresponds to “first communication circuitry”, 152 corresponds to “temperature sensor”, 102 includes a processing system tightly coupled to operational memory, see e.g., col. 13, lines 31-37), wherein the computer-executable instructions, when executed by the one or more processors individually or collectively, cause the electronic device to (col. 14, lines 63- col. 14 line 6): identify a temperature associated with the first communication via the at least one temperature sensor (Fig. 5, 502, col. 20, lines 47-51, Applicant’s original specification at paragraph [0080] describes “…the first communication may be a temperature according to heat generation of at least one of elements operating while the first communication is performed”. Dorsey takes the temperature data from the temperature sensor that is distributed throughout the client chassis that include heat generating elements such as the radio/modem subsystem, see e.g., col. 14, lines 45-55), Dorsey does not specifically disclose: based on the temperature being equal to or higher than a threshold value, identify a first application in a background state and a second application in a foreground state among a plurality of applications, wherein the first application is associated with data throughput of the first communication to or more than designated throughput, and adjust first data throughput of the first application by reducing a running time of the one or more processors for processing the first application. However, Lassa discloses: based on the temperature being equal to or higher than a threshold value, identify a first application in a background state having a data throughput of the first communication equal to or more than a designated throughput and a second application in a foreground state among a plurality of applications, and adjust first data throughput of the first application by reducing a running time of the one or more processors for processing the first application ([0051], [0052], where program, read, and erase commands are foreground commands. Each individual command corresponds to a “foreground application”. Each background commands corresponds to a “background application”. When the MCP or storage device becomes hot, background commands are throttled. Had background and foreground commands not been identified the controller would not know which commands to throttle. The background activities are throttled based on local power or thermal limits so that the background commands are ceased or delayed based on power or temperature. Therefore, the background commands are throttled based on the power and heat that exceeds a limit, i.e., a designated throughput). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Lassa to ensure case temperature is managed without sacrificing performance of high priority tasks/applications. With respect to claims 13, it recites similar limitations as claim 1 and is therefore rejected under the same citations and rationale. With respect to claim 20, it recites similar limitations as claim 1 and is therefore rejected under the same citations and rationale. With respect to claim 21, Dorsey discloses: wherein the temperature is identified based on a temperature value obtained by a temperature sensor, of the at least one temperature sensor, which is arranged in position adjacent to an antenna, of the at least one antenna, for sensing the temperature value corresponding to heat generated by the antenna which is operating while the first communication is performed (Fig. 1, 108A corresponds to antenna, 152 corresponds to temperatures sensor, col. 14, line 47 discloses that the sensors are distributed throughout the chassis and exterior surface). With respect to claim 22, Dorsey discloses: wherein the temperature is identified based on a temperature value obtained by a temperature sensor, of the at least one temperature sensor, which is arranged in position adjacent to an antenna, of the at least one antenna, for sensing the temperature value corresponding to heat generated by the antenna which is operating while the first communication is performed which is operating while the first communication is performed, wherein a first communication circuitry comprises a 5th generation (5G) modem (Fig. 1, 108A corresponds to antenna, 152 corresponds to temperatures sensor, col. 14, line 47 discloses that the sensors are distributed throughout the chassis and exterior surface. Examiner takes Official Notice that 5G modems existed in the prior art before the filing date of the invention). Claim(s) 5, 7,15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Dorsey et al. (US 8170606) in view of Lassa et al. (US 2012/0331207) further in view of Jang et al. (US 2018/0181171). With respect to claim 5, Jang discloses: use at least one processor among the plurality of processors for processing first application and adjust the first data throughput of the first application by changing the running time of the at least one processor for processing the first application ([0081]). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Jang to control the temperature of Dorsey’s electronic device at an application granular level thereby enabling Dorsey to finetune the data throughput at an application level rather than just on the bases of temperature and data throughput alone. With respect to claim 7, Jang discloses: based on the CPU a central processing unit (CPU) running time control scheme being used, the at least one processor electronic device to: change the running time of at least one processor among the one or more processors for processing the first application within a CPU bandwidth from a first time interval to a second time interval which is smaller than the first time interval ([0080], [0081], when the processor stops or suspends the application, the running time is interpreted as being slower than when it was actually executing, because execution of the application is halted). With respect to claim 15, Jang discloses: identifying whether the first application is operating in a background state or a foreground state; and when the first application is operating in the background state, adjusting the first data throughput of the first application, or when the first application is operating in the foreground state, maintain the first data throughput of the first application ([0079]-[0081], the background application has a lower priority and therefore has higher restrictions on the resources. The application may be stopped or suspended in order to lower the temperature. The “or when the first application is operating in foreground…maintain…application” is not given patentable weight for examining purposes as it is recited in the alternative). With respect to claim 16, Jang discloses: wherein the background state comprises a state in which the electronic device displays a screen of the first application on a display of the electronic device, and wherein the foreground state comprises a state in which the electronic device does not display the screen of the first application on the display of the electronic device (id.). With respect to claim 17, it recites similar limitations as claim 7 and is therefore rejected under the same citations and rationale. Claim(s) 2 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Dorsey et al. (US 8170606) in view of Lassa et al. (US 2012/0331207) further in view of Atsuo (JP 2011-229077), translation of Global Dossier is attached in the previous Office Action). With respect to claim 2, Dorsey and Lassa do not specifically disclose: a housing, wherein the computer-executable instructions, when executed by the one or more processors individually or collectively, cause the electronic device to: obtain a temperature on a surface of the housing based on heat generation in the electronic device via the at least one temperature sensor, based on the temperature on the surface of the housing being equal to or higher than a threshold value, obtain the temperature associated with the first communication via the at least one temperature sensor. However, Atsuo discloses: a housing, wherein the computer-executable instructions, when executed by the one or more processors individually or collectively, cause the electronic device to: obtain a temperature on a surface of the housing based on heat generation in the electronic device via the at least one temperature sensor, based on the temperature on the surface of the housing being equal to or higher than a threshold value, obtain the temperature associated with the first communication via the at least one temperature sensor ([0014]). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Atsuo into the combination of Dorsey and Lassa to ensure the combination of Dorsey and Jang can lower the temperature of the electronic device and not cause any burn injuries or discomfort to a user’s skin when the mobile phone is being used. With respect to claim 14, it recites similar limitations as claim 2 and is therefore rejected under the same citations and rationale. Claim(s) 10 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Dorsey et al. (US 8170606) in view of Lassa et al. (US 2012/0331207) further in view of Chauvel et al. (EP 1182538). Chauvel was cited in the previous Office Action. With respect to claim 10, Dorsey and Lassa do not specifically disclose: wherein the at least one processor or more processors comprises a first core and a second core, and wherein the computer-executable instructions, when executed by the one or more processors individually or collectively, based on a central processing unit (CPU) set control scheme being used, the electronic device to: adjust the first data throughput of the first application by changing the first core for processing the data of the first application from the first core to the second core having a slower processing speed than the first core. However Chauvel discloses: wherein the at least one processor or more processors comprises a first core and a second core, and wherein the computer-executable instructions, when executed by the one or more processors individually or collectively, based on a central processing unit (CPU) set control scheme being used, the electronic device to: adjust the first data throughput of the first application by changing the first core for processing the data of the first application from the first core to the second core having a slower processing speed than the first core ([0032]). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Chauvin to load balance the tasks/processes between cores so that service level objectives can be met as well as meet power objectives. Claim(s) 10 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Dorsey et al. (US 8170606) in view of Lassa et al. (US 2012/0331207) in view of Jang et al. (US 2018/0181171) further in view of Chauvel et al. (EP 1182538). With respect to claim 19, it recites similar limitations as claim 10 and is therefore rejected under the same citations and rationale. Claim(s) 11 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Dorsey et al. (US 8170606) in view of Lassa et al. (US 2012/0331207) further in view of Park et al. (US 2016/0124603). With respect to claim 11, Dorsey and Lassa do not specifically disclose: second communication circuitry configured to provide second communication via the at least one antenna wherein the first communication circuitry and the second communication circuitry operate in different networks. However, Park discloses: second communication circuitry configured to provide second communication via the at least one antenna wherein the first communication circuitry and the second communication circuitry operate in different networks ([0059], [0062]). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Park to ensure that communication between the mobile phone and other network entities can take advantage of faster networks like 5g when available to ensure lower latencies. With respect to claim 12, Park discloses: wherein the first communication circuitry comprises a 5th generation (5G) modem, and wherein the second communication circuitry comprises a 4th Generation (4G) or long-term evolution (LTE) modem (id.) Response to Arguments Applicant alleges that Lassa does not disclose the limitation “identify a first application in a background state having a data throughput of the first communication equal to or more than a designated throughput (pg. 13, Applicant’s Remarks 12/31/2025). Examiner, respectfully, disagrees. The claim does not elaborate what the “designated throughput” actually is. While throughput has many definitions in different contexts, under the broadest reasonable interpretation, the “designated throughput” can be a limit measured against any criteria that measures efficiency. In this regard, Lassa discloses throttling background commands based on whether thermal and/or power exceed certain limits. The command throughput is therefore throttled based on exceeding a thermal or power limit in order to ensure overall system efficiency is not negatively impacted. The “designated throughput” reads on Lassa’s thermal or power limit. Further, the background commands could not be throttled unless they were identifiable in the first place. Nothing in the claim language precludes such an interpretation. The rejection is, respectfully, maintained. Allowable Subject Matter Claims 3, 4, 8, and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to WISSAM RASHID whose telephone number is (571)270-3758. The examiner can normally be reached Monday-Friday 8:00 am-5:00 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Aimee Li can be reached on (571)272-4169. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /WISSAM RASHID/Primary Examiner, Art Unit 2195
Read full office action

Prosecution Timeline

Mar 21, 2024
Application Filed
Sep 28, 2024
Non-Final Rejection — §103, §DP
Nov 18, 2024
Applicant Interview (Telephonic)
Nov 18, 2024
Examiner Interview Summary
Dec 18, 2024
Response Filed
Mar 04, 2025
Final Rejection — §103, §DP
Apr 25, 2025
Request for Continued Examination
May 04, 2025
Response after Non-Final Action
May 10, 2025
Non-Final Rejection — §103, §DP
Aug 01, 2025
Response Filed
Oct 31, 2025
Final Rejection — §103, §DP
Dec 31, 2025
Request for Continued Examination
Jan 20, 2026
Response after Non-Final Action
Feb 03, 2026
Non-Final Rejection — §103, §DP (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

5-6
Expected OA Rounds
88%
Grant Probability
99%
With Interview (+12.3%)
2y 11m
Median Time to Grant
High
PTA Risk
Based on 654 resolved cases by this examiner. Grant probability derived from career allow rate.

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