Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Response to Amendment
The amendment filed on September 3, 2025 has been received and entered.
Applicant’s Amendments to the Claims have been received and acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by WINBLAD et al. (U.S. Publication No. 2021/0216482 A1), hereafter referred to as WINBLAD’482.
Referring to claim 1, WINBLAD’482, as claimed, an electronic apparatus (see Fig. 1) comprising: a processor (processor 2, see Fig. 1); memory (memory 4, see Fig. 1); a direct memory access (DMA) controller (DMA controllers 6 and 7 or single DMA controller, see Fig. 1 and para. [0028]); and a bus system (on-chip bus 5, see Fig. 1), wherein the processor is coupled to the bus system (processor 2 coupled to on-chip bus 5, see Fig. 1); wherein the memory is coupled to the bus system (memory 4 coupled to on-chip bus 5, see Fig. 1); wherein the DMA controller is coupled to the bus system at a bus connection point (see Fig. 1); wherein the DMA controller comprises a plurality of inputs (directional arrows pointing to DMA controllers 6 and 7, see Fig. 1); wherein the DMA controller comprises circuitry configured, for each input of the plurality of inputs, in response to receiving a signal at the respective input, to: determine a respective memory address in dependence on which of the plurality of inputs received the signal by reading a respective entry from a data structure stored in the memory (the DMA controller configured to fetch a job list from the memory. The job list may comprise one or more of: a memory address, data, a data length, and the data-attribute information, see para. [0032]); read from the memory a respective job list of one or more jobs located at the respective memory address (The job list may occupy a contiguous region in the memory, see para. [0032]), wherein each of the one or more jobs specifies a respective transfer operation for the DMA controller to perform (The memory address or addresses may point to data for transferring to the peripheral over the data link, or to a region of memory for receiving data transferred from the peripheral over the data link, see para. [0032]); and perform each of the one or more jobs in the job list by transferring data through the bus connection point in accordance with the respective transfer operation (write data it receives from the peripheral to a memory address determined from the job list, see para. [0035], Figs. 1 and 7).
As to claim 2, WINBLAD’482 also discloses the data structure is a table of pointers to job lists, the table holding a same number of pointers as there are inputs in the plurality of inputs (receiving the address of a job list…read a job list from the address in the job-list-address register, see paras. [0032], [0033] and Fig. 8).
As to claim 3, WINBLAD’482 also discloses the DMA controller comprises a hardware register for storing an address to the data structure, the hardware register being writable by the processor over the bus system (DMA controller comprise a hardware job-list-address register for receiving the address of a job list. This register may be writable by the processor, see para. [0033]).
As to claim 4, WINBLAD’482 also discloses the electronic apparatus comprises a plurality of processors or other hosts (the peripheral can be a cryptoprocessor…the device has further peripherals, further processors, see para. [0056] and Fig. 1), coupled to the bus system, and the circuitry of the DMA controller is configured to determine the respective memory address by reading entries from a data structure that is stored in an area of the memory that is accessible to each of the plurality of processors or hosts (reading job list from memory including information concerning location of the data and attribute information, see paras. [0069], [0071], [0079], and [0086]-[0088]).
As to claim 5, WINBLAD’482 also discloses the job list comprises a list of the one more jobs stored in a contiguous region of memory (the job list may occupy a contiguous region in the memory, see para. [0032]).
As to claim 6, WINBLAD’482 also discloses each of the one or more jobs comprises: a respective pointer field for storing an address in memory for the DMA controller to read data from or write data to; a size field for storing an amount of data to read or write; and an attribute field (the job list comprises a memory address, data, a data length, and the data-attribute information, see para. [0032]), wherein the DMA controller is configured to use a value in the attribute field to determine a type of operation to perform when performing the respective job (the data-attribute information may be a value from a predetermined set of data-attribute values. The peripheral configured to receive data of a plurality of different types, and to process the data differently according to its type. The data-attribute information may represent said types, see para. [0037]; also note: job list includes information concerning the location of the data in the memory and the attribute information associated with the data, specifying the type of data that is stored, see para. [0069] and Figs 4 and 5).
As to claim 7, WINBLAD’482 also discloses the DMA controller is a first DMA controller within a DMA module that is configured to perform DMA read and write operations between configurable memory addresses (single DMA controller, see Fig. 1 and para. [0028]), the first DMA controller being configured to perform only DMA read operations, wherein the DMA module further comprises a second DMA controller that is configured to perform only DMA write operations (receive DMA controller 6 and transmit DMA controller 7, see Fig. 1), and wherein the DMA module further comprises a flow logic module for controlling a flow of data, within the DMA module, from the first DMA controller to the second DMA controller (the cipher core have a set of control registers for receiving configuration settings from the processor. The cipher core also includes a receive buffer (Rx FIFO) for receiving incoming data from the RX DMA controller; a cipher finite state machine for performing the one or more cipher operations; and a transmit buffer for buffering outgoing data before it travels over the transmit data link to the TX DMA controller 7, see paras. [0088]-[0089]; also note: paras. [0071]-[0077] regarding memory transfer operations).
As to claim 8, WINBLAD’482 also discloses the flow logic module comprises a buffer for buffering the data flowing from the first DMA controller to the second DMA controller, wherein the buffer is sized to be at least as large as a maximum burst length of the bus system (the cipher core has a set of control registers for receiving configuration settings from the processor. The cipher core also includes a receive buffer (Rx FIFO) for receiving incoming data from the RX DMA controller; a cipher finite state machine for performing the one or more cipher operations; and a transmit buffer for buffering outgoing data before it travels over the transmit data link to the TX DMA controller 7, see paras. [0088]-[0089]; also note: paras. [0071]-[0077] regarding memory transfer operations and Fig. 8).
As to claim 9, WINBLAD’482 also discloses the second DMA controller comprises a plurality of inputs and circuitry configured (DMA controllers 6 and 7 or single DMA controller, see Figs. 1, 7, and para. [0028]), for each input of the plurality of inputs, in response to receiving a signal at the respective input (directional arrows pointing to DMA controllers 6 and 7, see Fig. 1), to: determine a respective memory address in dependence on which of the plurality of inputs received the signal (the DMA controller configured to fetch a job list from the memory. The job list may comprise one or more of: a memory address, data, a data length, and the data-attribute information, see para. [0032]); read from the memory a respective job list of one or more jobs located at the respective memory address (The job list may occupy a contiguous region in the memory, see para. [0032]), wherein each of the one or more jobs specifies a respective transfer operation for the second DMA controller to perform (The memory address or addresses may point to data for transferring to the peripheral over the data link, or to a region of memory for receiving data transferred from the peripheral over the data link, see para. [0032]); and perform each of the one or more jobs in the job list by transferring data through the bus connection point, or through a second bus connection point, in accordance with the respective transfer operation (write data it receives from the peripheral to a memory address determined from the job list, see para. [0035], Figs. 1 and 7).
As to claim 10, WINBLAD’482 also discloses each input of the plurality of inputs of the first DMA controller is also an input of the plurality of inputs of the second DMA controller (DMA controllers 6 and 7, see Figs. 1, 7, and para. [0028]).
As to claim 11, WINBLAD’482 also discloses the bus system comprises an Advanced eXtensible Interface (AXI) bus, and wherein the bus connection point is a point on the AXI bus and consists of a write address channel, a write data channel, a write response channel, a read address channel, and a read data channel (AXI is part of the AMBA specification, see paras. [0031], [0056] and Fig. 1 regarding Arm’ AMBA bus system; include one or more AHB’s (Advanced High-Performance Bus) or one or more APB’s (Advanced Peripheral Bus)).
As to claim 12, WINBLAD’482 also discloses the electronic apparatus comprises a plurality of peripherals (the peripheral can be a cryptoprocessor…the device has further peripherals, further processors, see para. [0056] and Fig. 1; also note: plurality of peripherals, see para. [0025]) that are interconnected by a configurable peripheral interconnect that is separate from the bus system (the bus system may be an Arm’ AMBA bus system; include one or more AHB’s (Advanced High-Performance Bus) or one or more APB’s (Advanced Peripheral Bus), see paras. [0031], [0056], Figs. 1 and 7; also note: data link and data-attribute link separate from the bus system, see para. [0029]), wherein the peripheral interconnect can be configured to provide one or more channels for receiving event signals from one peripheral of the plurality of peripherals and for providing the event signals as input to another peripheral of the plurality of peripherals (the DMA controller may have respective data links and data-attribute links to each of the plurality of peripherals, see para. [0025]; also note: data link and data-attribute link separate from the bus system, see para. [0029]), and wherein the plurality of inputs to the DMA controller comprise a plurality of event signal lines from the peripheral interconnect to the DMA controller (see Figs. 1 and 7).
As to claim 13, WINBLAD’482 also discloses the plurality of inputs comprises a plurality of register inputs, writable over the bus system, and wherein the DMA controller is configured to detect a write to any of the plurality of register inputs as a signal received at the respective input (the DMA controller may comprise a hardware job-list-address register for receiving the address of a job list. This register may be writable by the processor. The DMA controller may be configured to read a job list from the address in the job-list-address register, see paras. [0033], [0057], [0070], [0075], [0088], [0092], Fig. 1 and 7).
As to claim 14, WINBLAD’482 also discloses the DMA controller comprises a plurality of event signal inputs and a corresponding plurality of register inputs, and is configured, for each event signal input and corresponding register input, in response to receiving a signal at the event signal input or at the register input, to determine a same respective memory address from which to read the respective job list (the DMA controller may comprise a hardware job-list-address register for receiving the address of a job list. This register may be writable by the processor. The DMA controller may be configured to read a job list from the address in the job-list-address register, see paras. [0033], [0057], [0070], [0075], [0088], [0092], Fig. 1 and 7).
As to claim 15, WINBLAD’482 also discloses the DMA controller comprises a plurality of outputs comprising a corresponding output for each of the plurality of inputs (DMA controllers 6 and 7 or single DMA controller, see Figs. 1, 7, and para. [0028]), and is configured to determine that all of the one or jobs in the job list have been performed, and, in response to determining that all of the one or jobs in the job list have been performed, to output a completed signal from an output that corresponds to the input at which the signal was received for performing the job list (determines that it has reached the end of the DMA receive job list and in response, generates an interrupt to the processor over the interrupt channel. In some cases, provide some output via the receive DMA controller 6, see paras. [0072], [0077]; also note: end-marker value indicates the end of the job list, see paras. [0036], [0079], [0081], and [0093]).
As to claim 16, WINBLAD’482 also discloses the DMA controller comprises one or more interrupt request lines to the processor, and is configured to issue an interrupt request to the processor in response to determining that all the one or jobs in the job list have been performed (determines that it has reached the end of the DMA receive job list and in response, generates an interrupt to the processor over the interrupt channel. In some cases, provide some output via the receive DMA controller 6, see paras. [0072], [0077]; also note: end-marker value indicates the end of the job list, see paras. [0036], [0079], [0081], and [0093]).
As to claim 17, WINBLAD’482 also discloses the DMA controller is configured to queue signals received at different respective inputs of the plurality of inputs (Individual DMA transfers are combined into a DMA job list by storing them sequentially into memory, see para. [0078]; also note: DMA chain, see Figs. 4, 9, paras. [0069],[0078]), and is configured to queue a signal received at an input of the plurality of inputs while the DMA controller completes all of the one or more jobs of an active job list, and to service the queued signal once the active job list is completed (processing job list in sequence, see paras. [0034], [0035], [0041], [0082], [0093]).
As to claim 18, WINBLAD’482 also discloses each of the plurality of inputs has a different priority from an ordered set of priorities (perform conditional processing based on attribute value, see paras. [0035], [0082], also note: Individual DMA transfers are combined into a DMA job list by storing them sequentially into memory, see para. [0078]; also note: DMA chain, see Figs. 4, 9, paras. [0069],[0078]), and wherein the DMA controller is configured to service queued signals according to a priority of the respective input at which each queued signal was received (perform conditional processing based on attribute value, see paras. [0035], [0082]; also note: processing job list in sequence, see paras. [0034], [0035], [0041], [0082], [0093]).
As to claim 19, WINBLAD’482 also discloses the electronic apparatus is an integrated circuit (see Figs. 1 and 7; also note: circuitry, see paras. [0026]-[0028]).
Note claims 20 recites similar limitations of claim 1. Therefore it is rejected based on the same reason accordingly.
Response to Arguments
Applicant's arguments filed 9/3/2025 have been fully considered but they are not persuasive.
At the outset, Applicants are reminded that claims subject to examination will be given their broadest reasonable interpretation consistent with the specification. In re Morris, 127 F.3d 1048, 1054-55 (Fed. Cir. 1997). In fact, the "examiner has the duty of police claim language by giving it the broadest reasonable interpretation." Springs Window Fashions LP v. Novo Industries, L.P., 65 USPQ2d 1862, 1830, (Fed. Cir. 2003). Applicants are also reminded that claimed subject matter not the specification, is the measure of the invention. Disclosure contained in the specification cannot be read into the claims for the purpose of avoiding the prior art. In re Sporck, 55 CCPA 743, 386 F.2d, 155 USPQ 687 (1986).
With this in mind, the discussion will focus on how the terms and relationships thereof in the claims are met by the references. Response to any limitations that are not in the claims or any arguments that are irrelevant and/or do not relate to any specific claim language will not be warranted.
Applicant argued that “WINBLAD’482 does not teach determined a respective memory address in dependence on which of the plurality of inputs received the signal by reading a respective entry from a data structure stored in the memory.” (Pages 8-10 of Applicant’s Argument)
Examiner does not agree with Applicant. As set forth in the art rejection, WINBLAD’482 discloses determine a respective memory address in dependence on which of the plurality of inputs received the signal by reading a respective entry from a data structure stored in the memory (the DMA controller configured to fetch a job list from the memory. The job list may comprise one or more of: a memory address, data, a data length, and the data-attribute information, see para. [0032]). In WINBLAD’482, a job list is fetched from the memory. It defines what the DMA controller retrieves and what information the retrieved job list contains. Fetching the job list necessarily means that the DMA controller reads structured information from memory that describes the DMA job, including addresses, data, data length, and attributes. The job list is implemented as a data structure (such as an array, list, or queue) whose contents are stored at specific memory addresses. When the DMA controller fetches the job list, it is reading the bytes stored at those addresses and interpreting them according to the data structure’s layout. Selecting which job to process based on which input signal is asserted simply determines which entry of the job list is read. The term fetching a job list describes the purpose of the operation at a higher level, while reading a respective data structure from memory describes the low-level action being performed. Operationally, both involve the same memory read performed by the DMA controller.
In summary, WINBLAD’482 teaches the claimed limitations as set forth.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The examiner requests, in response to this office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application. When responding to this office action, applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R. 1.111(c).
In amending in reply to a rejection of claims in an application or patent under reexamination, the applicant or patent owner must clearly point out the patentable novelty which he or she thinks the claims present in view the state of the art disclosed by the references cited or the objections made. The applicant or patent owner must also show how the amendments avoid such references or objections.
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/TITUS WONG/Primary Examiner, Art Unit 2181