Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: 412 and 414 in Figure 4B are not mentioned in the specification. Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3-5 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3 recites the limitation “the main memory” in line 1. There is insufficient antecedent basis for this limitation in the claim. Claims 4 and 5 recite commensurate subject matter; therefore, they are indefinite for the same reason.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-3, 5, 7-11, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rigetti 1 (US 2016/0267032) and further in view of Rigetti 2 (US 10,127,499).
Regarding claim 1, Rigetti 1 teaches: A quantum controller for interfacing between a host computer and a quantum processing unit (QPU) having a plurality of qubits (¶ 37, “The example quantum computing system 100 shown in FIG. 1 includes a control system 110” and ¶ 38, “qubits (i.e., quantum bits) can be stored in and represented by an effective two-level sub-manifold of a quantum coherent physical system”), the quantum controller comprising: signal processing hardware configured for transforming instructions from the host computer into control signals readable by the QPU (¶ 316, “The FPGA 2362 can control the DAC 2364 to produce a pulse or other signal having one or more frequency components targeted to one or more qubit devices or readout devices”), the signal processing hardware comprising programmable logic and signal conversion circuits (¶ 376, “The FPGA may receive the instructions from the DLC 2820 and induce the DAC and ADC within the channel controller to produce or process signals that allow the system to perform quantum computation operations realizing those instructions”); (¶ 56, “the input signal processing system 128 includes multiple processing cards housed on a circuit board. The circuit board can include receptacle slots that form mechanical connections and signal path connections between the circuit board and the processing cards”), the carrying substrate providing power and signal routing to the signal processing hardware and the hardware accelerator components (¶ 292, “the amplifier 2356 can receive power from an external power source and increase the voltage of the qubit readout signals”).
Rigetti 1 does not teach; however, Rigetti 2 teaches: hardware accelerator components dedicated to tasks offloaded from the programmable logic (col. 12:26-30, “the host device (e.g., the CPU 302) can operate as a master device that delegates processing tasks to the other processors and controls timing and dataflow in the heterogeneous computing environment 300”), the hardware accelerator components comprising at least one processor different from the QPU (col. 12:30-35, “the CPU 302 can identify a particular type of processor device to execute each sub-process in an algorithm; and based on the type of processor device identified, the CPU 302 can delegate the sub-processes the QPU 304, the FPGA 306 or the GPU 308, or the CPU 302 or execute the sub-process itself”).
It would have been obvious to a person having ordinary skill in the art, at the effective filing date of the invention, to have applied the known technique of hardware accelerator components dedicated to tasks offloaded from the programmable logic, the hardware accelerator components comprising at least one processor different from the QPU, as taught by Rigetti 2, in the same way to the programmable logic, as taught by Rigetti 1. Both inventions are in the field of quantum processing, and combining them would have predictably resulted in a system configured to “offload computationally-intensive tasks to the specialized processors, for example, to improve system performance, system utilization, or other factors,” as indicated by Rigetti 2 (col. 13:48-50).
Regarding claim 2, Rigetti 2 teaches: The quantum controller of claim 1, wherein the signal processing hardware and the hardware accelerator components exchange data directly from a main memory coupled to the carrying substrate (col. 13:1-6, “the interconnect 310 may include memory blocks or memory devices that are accessible by multiple processor devices. For instance, the interconnect 310 can include a memory block that is shared by the CPU 302 and the QPU 304, where both the CPU 302 and the QPU 304 have read and write access to the shared memory block”).
Regarding claim 3, Rigetti 2 teaches: The quantum controller of claim 1, wherein the main memory comprises a memory controller and one or more memory cells, and the memory controller manages read and write operations by the programmable logic and the at least one processor to the one or more memory cells (col. 4:6-11, “The quantum processor cell 102 may also include readout devices that selectively interact with the qubits to detect their quantum states. For example, the readout devices may generate readout signals that indicate the computational state of the quantum processor or quantum memory”).
Regarding claim 5, Rigetti 2 teaches: The quantum controller of claim 3, wherein the main memory is implemented as a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC), and the FPGA or ASIC also comprises a network interface (col. 20:23-25, “an FPGA or ASIC memory controller can connect the GPU array to a flash memory device”).
Regarding claim 7, Rigetti 1 teaches: The quantum controller of claim 1, wherein the programmable logic comprises a Field Programmable Gate Array (FPGA), and the signal conversion circuits comprise at least one digital to analog converter (DAC) and at least one analog to digital converter (ADC) (¶ 316, “FIG. 23B shows a read/write channel controller 2361 that includes a field-programmable gate array (FPGA) 2362, an analog-to-digital converter (ADC) 2363 and a digital-to-analog converter (DAC) 2364”).
Regarding claim 8, Rigetti 2 teaches: The quantum controller of claim 1, wherein the at least one processor of the hardware accelerator components comprise a central processing unit (CPU) and a graphics processing unit (GPU) (col. 11:62-67, “The example heterogeneous computing environment 300 shown in FIG. 3A includes four distinct types of processors: a Central Processing Unit (CPU) 302, a Quantum Processor Unit (QPU) 304, a Field Programmable Gate Array (FPGA) 306, and a Graphics Processing Unit (GPU) 308”).
Regarding claim 9, Rigetti 2 teaches: The quantum controller of claim 8, wherein the GPU and the CPU are provided together as at least one system-on-module on a substrate separate from the carrying substrate and mounted thereto (col. 12:4-6, “the CPU 302, the QPU 304, the FGPA 306 and the GPU 308 are connected to an interconnect 310”).
Regarding claim 10, Rigetti 2 teaches: The quantum controller of claim 8, wherein the GPU and the CPU are each provided as a separate system-on-module on substrates separate from the carrying substrate and mounted thereto (col. 12:4-7, “the CPU 302, the QPU 304, the FGPA 306 and the GPU 308 are connected to an interconnect 310. The processors may be connected to additional or different devices and systems.”).
Regarding claim 11, Rigetti 1 teaches: The quantum controller of claim 1, wherein the signal processing hardware is provided as at least one system-on-module on a substrate separate from the carrying substrate and mounted thereto (¶ 56, “the input signal processing system 128 includes multiple processing cards housed on a circuit board. The circuit board can include receptacle slots that form mechanical connections and signal path connections between the circuit board and the processing cards.”).
Regarding claim 20, Rigetti 1 teaches: The quantum controller of claim 1, wherein the programmable logic is integrated with digital to analog radio frequency (DAC RF) converters and analog to digital radio frequency (ADC RF) converters (¶ 316, “an analog-to-digital converter (ADC) 2363 and a digital-to-analog converter (DAC) 2364”).
Claim(s) 4, 17, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rigetti 1 and Rigetti 2, as applied above, and further in view of Chernoguzov (US 2022/0398483).
Regarding claim 4, Rigetti 1 and Rigetti 2 do not teach; however, Chernoguzov discloses: the main memory is provided as a system-on-module on a substrate separate from the carrying substrate and mounted thereto (¶ 113, “each chassis comprised of a PCI module (e.g., 940A, 940B, and 940C), one or more AWG modules (e.g., 950A1, 950A2 on chassis 930A; 950B1, 950B2, 950B3 on chassis 930B; and 950C1, 950C2, and 950C3 on chassis 930C), and one or more backplane connection cards (e.g., 970A on chassis 930A”).
It would have been obvious to a person having ordinary skill in the art, at the effective filing date of the invention, to have applied the known technique of the main memory is provided as a system-on-module on a substrate separate from the carrying substrate and mounted thereto, as taught by Chernoguzov, in the same way to the main memory, as taught by Rigetti 1 and Rigetti 2. Both inventions are in the field of quantum computing controllers, and combining them would have predictably resulted in “a quantum computer that may be configured to perform conditional transport as well as just-in-time waveform selection and methods relating thereto,” as indicated by Chernoguzov (¶ 2).
Claims 17 and 18 recite commensurate subject matter as claim 4. Therefore, it is rejected for the same reason.
Claim(s) 6 and 12-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rigetti 1 and Rigetti 2, as applied above, and further in view of Shani (US 11,126,926).
Regarding claim 6, Rigetti 1 and Rigetti 2 do not teach; however, Shani discloses: an intermediate frequency (IF) circuit and a radio frequency (RF) circuit (col. 11:55-58, “an element definition in the specification 262 may include an intermediate frequency with which every pulse sent to the element is to be modulated” and col. 11:43-45, “One example of an element that a quantum machine may contain is an IQ mixer that is connected to two output ports of the controller 210”), the IF circuit converting the instructions received from the host computer into a waveform at a first frequency (col. 11:55-58, “an element definition in the specification 262 may include an intermediate frequency with which every pulse sent to the element is to be modulated”), the RF circuit upconverting the waveform at the first frequency to a second frequency higher than the first frequency (col. 9, “mixer calibration properties, used to post- shape the pulse to compensate for imperfections in the mixers used for upconverting the analog waveforms”).
It would have been obvious to a person having ordinary skill in the art, at the effective filing date of the invention, to have applied the known technique of an intermediate frequency (IF) circuit and a radio frequency (RF) circuit, the IF circuit converting the instructions received from the host computer into a waveform at a first frequency, the RF circuit upconverting the waveform at the first frequency to a second frequency higher than the first frequency, as taught by Shani, in the same way to the signal processing hardware, as taught by Rigetti 1 and Rigetti 2. Both inventions are in the field of quantum computing controllers, and combining them would have predictably resulted in “concurrent results processing in a quantum control system,” as indicated by Shani (col. 1:15-16).
Regarding claim 12, Shani teaches: The quantum controller of claim 6, wherein the IF circuit is provided as at least one system-on-module on a substrate separate from the carrying substrate and mounted thereto (col. 21:39-41, “The depicted circuits may reside on a plurality of interconnected, but physically separate quantum control modules” and col. 30:3-6, “one or more quantum control modules are connected together to form quantum controller 210 and the quantum controller 210 is connected to a quantum system”).
Regarding claim 13, Shani teaches: The quantum controller of claim 12, wherein the at least one system-on-module with the IF circuit further comprises the at least one processor of the hardware accelerator components (col. 46:41-47, “A typical implementation may comprise one or more application specific integrated circuit (ASIC), one or more field programmable gate array (FPGA), and/or one or more processors (e.g., x86, x64, ARM, PIC, and/or any other suitable processor architecture) and associated supporting circuitry”).
Regarding claim 14, Rigetti 2 teaches: The quantum controller of claim 13, wherein the at least one processor comprises at least one of a central processing unit (CPU) and a graphics processing unit (GPU) (col. 12:4-6, “the CPU 302, the QPU 304, the FGPA 306 and the GPU 308 are connected to an interconnect 310”).
Regarding claim 15, Shani teaches: The quantum controller of claim 6, wherein the RF circuit is provided as at least one system-on-module on a substrate separate from the carrying substrate and mounted thereto (col. 21:39-42, “The depicted circuits may reside on a plurality of interconnected, but physically separate quantum control modules (e.g., each module being a desktop or rack mounted device)”).
Regarding claim 16, Shani teaches: The quantum controller of claim 6, wherein the IF circuit and RF circuit are together provided as at least one system-on-module on a substrate separate from the carrying substrate and mounted thereto (col. 30:3-6, “one or more quantum control modules are connected together to form quantum controller 210 and the quantum controller 210 is connected to a quantum system”).
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rigetti 1 and Rigetti 2, as applied above, and further in view of Jennings (US 11,012,072).
Regarding claim 19, Rigetti 1 and Rigetti 2 do not teach; however, Jennings discloses: an adaptive compute acceleration platform (ACAP) having at least one scalar engine, at least one adaptable engine, and at least one intelligent engine (col. 1:24-30, “An ACAP may include scalar engines (compute cores), adaptable engines (programmable logic and memory cells), and intelligent engines (configurable artificial intelligence (AI) and digital signal processing (DSP) engines) that may selectively be connected together with a configurable high-bandwidth network-on-chip (NoC)”).
It would have been obvious to a person having ordinary skill in the art, at the effective filing date of the invention, to have applied the known technique of an adaptive compute acceleration platform (ACAP) having at least one scalar engine, at least one adaptable engine, and at least one intelligent engine, as taught by Jennings, in the same way to the signal processing hardware, as taught by Rigetti 1 and Rigetti 2. Both inventions are in the field of programmable computing platforms, and combining them would have predictably resulted in “determining an alternative configuration for the programmable device based on the temperature associated with the one or more regions and relocating functions,” as indicated by Jennings (col. 2:1-4).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Cohen (US 11,164,100) teaches “It is the job of the quantum controller to generate the precise series of external signals, usually pulses of electromagnetic waves and pulses of base band voltage, to perform the desired logic operations” (col. 2:66-67 and col. 3:1-2), which relates to the disclosed quantum controller generating control signals for a quantum processor.
Bardin (US 2021/0257969) teaches “The qubit control electronics, which may be embodied in the IC, generate qubit control signals, such as qubit XY control signals, using an envelope generator circuit that is electrically coupled to a mixer circuit” (¶ 3), which relates to the disclosed hardware generating qubit control signals.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB D DASCOMB whose telephone number is (571)272-9993. The examiner can normally be reached M-F 9:00-5:00.
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/JACOB D DASCOMB/ Primary Examiner, Art Unit 2198
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