DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. Claims 1–20 are presented for examination in a non-provisional application filed on 03/21/2024.
Drawings
3. The drawings were received on 03/21/2024 (in the filings). These drawings are acceptable.
Claim Interpretation Under 35 USC § 112
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
4. The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f):
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f), is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f), is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f), except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f), except as otherwise indicated in an Office action.
In this instant application, claim 8 is being interpreted under 35 U.S.C. 112(f).
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f), it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f), applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f).
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
5. Claims 9–14 and 19 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
6. As to independent claim 9, the claim recites:
“determining if the EFU task can be offloaded from a plurality of elementary function units (EFUs) in the GPU to a plurality of arithmetic logical units (AL Us) in the GPU according to a selection criterion.”
These limitations, as currently drafted and within their respective claim, represent processes that, under a broadest reasonable interpretation, covers performance in the mind (including observation, evaluation, judgment, opinion, etc.) but for the recitation of generic computer components.
In this instance, nothing in the claim element precludes the step from practically being performed in the mind or using pencil and paper (see MPEP 2106.04(a)(2) – Examples of Concepts The Courts Have Identified As Abstract Ideas, discussing abstract ideas or concepts relating to organizing or analyzing information in a way that can be performed mentally or is analogous to human mental work).
If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
This judicial exception is not integrated into a practical application (under Prong Two of Step 2A)
(I) Data Collection
As presented, claims 9 also includes the additional element of:
(a) “receiving an elementary function unit (EFU) task with a sequence of elementary function unit (EFU) native operations in a graphical processing unit (GPU).”
However, merely obtaining or collecting data or input for further processing or use simply does not “integrate” the abstract idea into a practical application which improves the functioning of a computer or other technology or technological field.
Moreover, the courts have also held that limitations which merely adds insignificant extra-solution activity to the judicial exception does not integrate a judicial exception into a practical application.
As discussed below and set forth in MPEP § 2106.05(g), the mere collection of data or information for processing essentially amounts to DATA GATHERING and therefore is consider an “insignificant extra-solution activity.”
(II) Particular Technological Environment or Field Of Use
As shown above, the claims also include the elements of:
(1) “an elementary function unit (EFU) task ... in a graphical processing unit (GPU)” and
(2) “a plurality of arithmetic logical units (ALUs).”
These exemplary elements however merely describes the general technical or computing environment (within which the claimed steps or processes operate) and restrict the processed information or data to a particular type or category (without imposing any functional claim limitations, activities, or steps).
Limitations that generally link the use of the judicial exception to a particular technological environment or field of use, neither meaningfully limit the claim nor transform (the abstract idea nature of) the claim to a particular useful application to improve the functioning of a computer or any other technology.
Under Step 2B of the 101 analysis:
The claims do not include additional elements, alone or in combination, that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements amount to no more than generic computing components and field of use/technological environment which do not amount to significantly more than the abstract idea.
As claimed, the activity of “mere data gathering” have also been found by the courts to be “insignificant extra-solution activity” as set forth in MPEP 2106.05(g)(3) Insignificant Extra-Solution Activity, describing that in determining whether an additional element is insignificant extra-solution activity, one may factoring into consideration whether the limitation amounts to necessary data gathering and outputting, (i.e., all uses of the recited judicial exception require such data gathering or data output).
As recited, the step of”
(a) “receiving an elementary function unit (EFU) task with a sequence of elementary function unit (EFU) native operations in a graphical processing unit (GPU)”
are mere data gathering activities for additional processing (receiving tasks or instructions) and/or insignificant data storage activities.
Accordingly, the additional step(s) or element(s) of the claims, viewed individually and as an ordered combination, added nothing to the implementation of a mental process on an unspecified, “generic” computer and therefore failed to transform the abstract idea nature of the claims into a patent-eligible application.
7. As to dependent claims 10–14 and 19, each of these claims either (1) recites additional step(s) that covers performance in the mind; or (2) merely restricts or links the process step, information or data to a particular type, technological environment, or field of use; (3) amounts to insignificant extra-solution activity to the judicial exception such as data input and output/transmission; or (4) recites a function which amounts to no more than a recitation of the words “apply it” (or an equivalent) and is no more than mere instructions to implement an abstract idea or other exception on a computer; and thus as a whole is also directed and confined to the same process set forth in claim 9. Therefore, these claims do not individually or collectively add an inventive concept or additional element(s) amounting to significantly more than the abstract idea itself. These claims are therefore not drawn to eligible subject matter as they are directed to an abstract idea without significantly more.
For instance, dependent claim 10 reciting “wherein the EFU task includes a succession of N quantity of GPU instructions” merely restricts or links the process step, information or data to a particular type, technological environment, or field of use (i.e. describing the type or features of an EFU task).
Dependent claim 11 reciting “wherein the selection criterion is a determination of whether there are no arithmetic logical unit (ALU) native operations in a succession of N quantity of GPU instructions” merely recites additional step(s) that covers performance in the mind and further restricts or links the process step, information or data to a particular type, technological environment, or field of use.
Dependent claim 12 reciting “wherein the value of N depends on a type of an elementary function unit (EFU) native operation” merely restricts or links the process step, information or data to a particular type, technological environment, or field of use (i.e. describing the type or features of an EFU task).
Dependent claim 13 reciting “wherein the selection criterion is successful” merely recites additional step(s) that covers performance in the mind and further restricts or links the process step, information or data to a particular type, technological environment, or field of use.
Dependent claim 14 reciting “converting the sequence of EFU native operations in the EFU task into a sequence of arithmetic logical unit (ALU) native operations” merely recites additional step(s) that covers performance in the mind and further restricts or links the process step, information or data to a particular type, technological environment, or field of use.
Dependent claim 19 reciting “wherein the selection criterion is failed” merely recites additional step(s) that covers performance in the mind and further restricts or links the process step, information or data to a particular type, technological environment, or field of use.
Practical Application Integration
Claims 15–18 and 20 includes element(s) integrating the abstract idea into a practical application.
Examiner’s Remarks
8. Examiner refers to and explicitly cites particular pages, sections, figures, paragraphs or columns and lines in the references as applied to Applicant’s claims to the extent practicable to streamline prosecution.
Although the cited portions of the references are representative of the best teachings in the art and are applied to meet the specific limitations of the claims, other uncited but related teachings of the references may be equally applicable as well. It is respectfully requested that, in preparing responses to the rejections, the Applicant fully considers not only the cited portions of the references, but also the references in their entirety, as potentially teaching, suggesting or rendering obvious all or one or more aspects of the claimed invention.
Abbreviations
9. Where appropriate, the following abbreviations will be used when referencing Applicant’s submissions and specific teachings of the reference(s):
i. figure / figures: Fig. / Figs.
ii. column / columns: Col. / Cols.
iii. page / pages: p. / pp.
References Cited
10. (A) Applicant’s Specification, construed as Applicant Admitted Prior Art (“AAPA”).
(B) Jiao et al., US 2008/0074433 A1 (“Jiao).
Notice re prior art available under both pre-AIA and AIA
11. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
A.
12. Claims 1–6, 9–10, and 19–20 and are rejected under 35 U.S.C. 103 as being unpatentable over (A) AAPA in view of (B) Jiao.
See “References Cited” section, above, for full citations of references.
13. Regarding claim 1, (A) AAPA teaches/suggests the invention substantially as claimed, including:
“An apparatus comprising:
a graphical processing unit (GPU) controller configured to control scene rendering;
a plurality of elementary function units (EFUs) ...; and
a plurality of arithmetic logical units (ALUs) ...”
(¶ 2: One processing engine known as a graphical processing unit (GPU) may be used for
rendering graphical images for a wide range of user applications. The GPU may include
a plurality of elementary function units (EFU s) and a plurality of arithmetic logical units
(ALUs)).
AAPA does not teach “(EFUs) configured to execute a sequence of elementary function unit (EFU) native operations; and ... (ALUs) configured to execute a sequence of arithmetic logical unit (ALU) native operations.”
(B) Jiao however teaches or suggests:
“(EFUs) configured to execute a sequence of elementary function unit (EFU) native operations; and ... (ALUs) configured to execute a sequence of arithmetic logical unit (ALU) native operations”
(¶ 19: A graphics processor 120 performs processing for programs 110a through 110n. Graphics processor 120 may split the processing of each program into a series of threads, e.g., automatically and transparent to the program. A thread ( or thread of execution) may indicate a specific task that may be performed with a set of one or more instructions;
Fig. 2 and ¶ 23: An ALU core 220 may perform arithmetic operations such as addition (ADD), subtraction (SUB), multiplication (MUL), multiply and accumulate (MAD), dot product (DPn), absolute, negation, comparison, saturation, etc.;
¶ 24: An elementary function core 230 may compute transcendental elementary functions such as sine (SIN), cosine (COS), reciprocal (RCP), logarithm (LOG), exponential (EXP), square root (SQR)).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of (B) Jiao with those of (A) AAPA to execute different types of mathematical operations on different processing cores/units. The motivation or advantage to do so is to provide for the execution (computation) of different math operations on specialized cores or processing units each optimized to execute a specific operation or function type (e.g. arithmetic, elementary, logic operations).
14. Regarding claim 2, Jiao teaches or suggests:
“wherein the sequence of EFU native operations includes one or more of the following: a power function, an exponential function, a logarithmic function, a trigonometric function, a square root function, a reciprocal function, or a reciprocal square function”
(¶ 24: An elementary function core 230 may compute transcendental elementary functions such as sine (SIN), cosine (COS), reciprocal (RCP), logarithm (LOG), exponential (EXP), square root (SQR)).
15. Regarding claim 3, Jiao teaches or suggests:
“wherein the sequence of ALU native operations includes one or more arithmetic operations”
(¶ 23: An ALU core 220 may perform arithmetic operations such as addition (ADD), subtraction (SUB), multiplication (MUL), multiply and accumulate (MAD), dot product (DPn), absolute, negation, comparison, saturation, etc.).
16. Regarding claim 4, Jiao teaches or suggests:
“wherein the one or more arithmetic operations includes an addition operation, a subtraction operation or a multiplication operation”
(¶ 23: An ALU core 220 may perform arithmetic operations such as addition (ADD), subtraction (SUB), multiplication (MUL), multiply and accumulate (MAD), dot product (DPn), absolute, negation, comparison, saturation, etc.).
17. Regarding claim 5, Jiao teaches or suggests:
“a graphical processing unit (GPU) network interface configured to receives an elementary function unit (EFU) task”
(Fig. 2 and ¶ 22: Within shader core 130, a multiplexer (Mux) 208 receives threads from programs 110a through 110n and provides these threads to a thread scheduler 210. Thread scheduler 210 performs various functions to schedule and manage execution of the threads ... An instruction cache 214 stores instructions for the threads. These instructions indicate specific operations to perform for each thread. Each operation may be an arithmetic operation, an elementary function, a logic operation).
18. Regarding claim 6, AAPA and Jiao teach or suggest:
“a central processing unit (CPU) coupled to the graphical processing unit (GPU), the CPU configured to determine if the EFU task can be offloaded from the plurality of EFUs in the GPU to the plurality of ALUs in the GPU according to a selection criterion.”
(AAPA, ¶ 2: GPU may include a plurality of elementary function units (EFU s) and a plurality of arithmetic logical units (ALUs). GPU throughput may increase by selective offloading of EFU tasks to the plurality of ALUs;
Jiao, Fig. 9 and ¶ 79: Controller/processor 926 may direct the operation of various processing and interface units within digital section 920. Display processor 928 performs processing to facilitate the display of videos, graphics, and texts on a display unit 930. ARM/DSP 932 may perform various types of processing for wireless device 900. Graphics processor 934 performs graphics processing and may be implemented as shown in FIG. 2).
19. Regarding claim 9 (independent), AAPA teaches or suggests:
“receiving an elementary function unit (EFU) task ... in a graphical processing unit (GPU); and
determining if the EFU task can be offloaded from a plurality of elementary function units (EFUs) in the GPU to a plurality of arithmetic logical units (ALUs) in the GPU according to a selection criterion”
(¶ 2: GPU may include a plurality of elementary function units (EFU s) and a plurality of arithmetic logical units (ALUs). GPU throughput may increase by selective offloading of EFU tasks to the plurality of ALUs;
see also infra, Jiao, Fig. 2 and ¶ 19, ¶ 23 and ¶ 24)
AAPA does not teach but Jiao teaches or suggests:
“(EFU) task with a sequence of elementary function unit (EFU) native operations”
(¶ 19: A graphics processor 120 performs processing for programs 110a through 110n. Graphics processor 120 may split the processing of each program into a series of threads, e.g., automatically and transparent to the program. A thread ( or thread of execution) may indicate a specific task that may be performed with a set of one or more instructions;
Fig. 2 and ¶ 23: An ALU core 220 may perform arithmetic operations such as addition (ADD), subtraction (SUB), multiplication (MUL), multiply and accumulate (MAD), dot product (DPn), absolute, negation, comparison, saturation, etc.;
¶ 24: An elementary function core 230 may compute transcendental elementary functions such as sine (SIN), cosine (COS), reciprocal (RCP), logarithm (LOG), exponential (EXP), square root (SQR)).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of (B) Jiao with those of (A) AAPA to execute different types of mathematical operations on different processing cores/units. The motivation or advantage to do so is to provide for the execution (computation) of different math operations on specialized cores or processing units each optimized to execute a specific operation or function type (e.g. arithmetic, elementary, logic operations).
20. Regarding claim 10, Jiao teaches or suggests:
“wherein the EFU task includes a succession of N quantity of GPU instructions”
(¶ 19: A graphics processor 120 performs processing for programs 110a through 110n. Graphics processor 120 may split the processing of each program into a series of threads, e.g., automatically and transparent to the program. A thread ( or thread of execution) may indicate a specific task that may be performed with a set of one or more instructions;
¶ 24: An elementary function core 230 may compute transcendental elementary functions such as sine (SIN), cosine (COS), reciprocal (RCP), logarithm (LOG), exponential (EXP), square root (SQR)).
21. Regarding claim 19, AAPA teaches or suggests:
“wherein the selection criterion is failed”
(AAPA, ¶ 2: GPU may include a plurality of elementary function units (EFU s) and a plurality of arithmetic logical units (ALUs). GPU throughput may increase by selective offloading of EFU tasks to the plurality of ALUs;
the Examiner notes that “selective offloading” suggests or implies that offloading is not performed where GPU throughput would not increase or improve).
22. Regarding claim 20, Jiao teaches or suggests:
“executing the sequence of EFU native operations to complete the EFU task”
(¶ 24: An elementary function core 230 may compute transcendental elementary functions such as sine (SIN), cosine (COS), reciprocal (RCP), logarithm (LOG), exponential (EXP), square root (SQR)).
Allowable Subject Matter
23. Claim 8 is allowed.
24. Claims 7 and 11–18 are objected to as being dependent upon a rejected base claim, but would be allowable if 1) rewritten in independent form including all of the limitations of the base claim and any intervening claims, and 2) rewritten to overcome the applied 101 rejections.
The following is the Examiner’s statement of reasons for allowance:
The prior art of record, when viewed individually or in combination, does not expressly teach nor render obvious the features of dependent claims 7 and 11 when viewed as a whole, specific to the limitation(s) of:
“wherein the selection criterion is a determination of whether there are no arithmetic logical unit (ALU) native operations in a succession of N quantity of GPU instructions” (claim 7);
“wherein the selection criterion is a determination of whether there are no arithmetic logical unit (ALU) native operations in a succession of N quantity of GPU instructions” (claim 11).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
(a) Yamada et al., US 2005/0027965 A1, teaching an instruction translation logic unit for translating an instruction in the first format into an instruction in the second format.
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/BENJAMIN C WU/Primary Examiner, Art Unit 2195
July 18, 2026
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