The present application, filed on or after March 16, 2013, is being examined under first to invent provisions of the AIA .
DETAILED ACTION
This Action is in response to communications filed 2/25/2026.
Claims 1, 3-6, 11, 12, 14 and 15 are amended. Claim 2 is cancelled.
Claims 1 and 3-16 are pending.
Claims 1, 3-5, 11, 12 and 14 are rejected. Claims 6-10, 13 and 15-16 are objected to.
Response to Arguments
Applicant`s arguments filed February 25, 2026 have been fully considered and they are persuasive with respect to prior art rejection.
As per claim 1, Applicant argued that Kawaguchi does not disclose or imply a nonvolatile flash memory architecture where a controller programmatically monitors host-initiated sync commands to selectively stamp a dedicated indicator into a physical spare area of a NAND page. Applicant further argued Yamamoto operates entirely on a high-level logical allocation layer. It completely lacks any disclosure of a physical flash memory controller, let alone a controller that dynamically reacts to an external data synchronization command by encoding specialized synchronization attributes into a physical page's spare area. Yamamoto does not address, teach, or provide any structural solution for reducing physical recovery overhead during an SPO event based on hardware markers.
However, Yamamoto discloses where the storage controller 200 may release the relevant virtual page by moving the segment being used by the virtual page corresponding to this flag 2008 to another virtual page (that is, moving the data in the real page allocated to the virtual page corresponding to this flag 2008 to another real page, and, in addition, allocating this other real page to another virtual page). However, in this example, the storage controller 200 refrains from allocating a new segment included in this virtual page, waits for the previously allocated segment to be released, and releases the relevant virtual page (Paragraph 0113), wherein moving the flag to another page and moving the segment being used by the virtual page corresponding to this flag 2008 to another virtual page (that is, moving the data in the real page allocated to the virtual page corresponding to this flag 2008 to another real page, and, in addition, allocating this other real page to another virtual page) corresponds to the claimed limitation of writes a data synchronization indicator to a spare area of at least one page among the one or more pages to which the user data is written.
As per claim 12, Applicant argued that Kavanagh's thread-waiting mechanism upon file-full status does not teach, suggest, or contemplate a hardware memory controller that actively suppresses or omits a data synchronization indicator when flushing physical buffer data due to a preset structural capacity being reached. Kavanagh does not address the interplay between an explicit host synchronization command and an un-synchronized buffer-full threshold. It merely halts thread execution when file allocation limits are met. While Kawaguchi generally discusses abstract synchronization flags between memory spaces, neither Kawaguchi nor Kavanagh teaches or suggests a mechanism to separately manage committed user data based on the presence or absence of a data synchronization indicator. where examiner relies on a newly cited reference Edgington to disclose the claimed limitation
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5, 11 and 14 is rejected under 35 U.S.C. 103(a) as being disclosed by Kawaguchi et al. (US PGPUB 2018/0246808 hereinafter referred to as Kawaguchi), and further in view of Yamamoto et al. (US PGPUB 2013/0318196 hereinafter referred to as Yamamoto).
As per independent claim 1, Kawaguchi discloses a storage device comprising: a first memory; a second memory; and a controller configured to write user data to the first memory [(Paragraphs 0029-0033; FIG. 1-3 and related text) wherein Kawaguchi teaches where FIG. 3 illustrates the overall configuration of an information processing apparatus of the present embodiment. The information processing apparatus includes a PCI (Peripheral Component Interconnect) bus 1, a processor 2 mounted on a PCI card connected to the PCI bus 1, and memories (MEM) 31-34 mounted on the PCI card and connected to the processor 2. The PCI bus 1 is a standard PCI Express, and the memories are also standard memorie to correspond to the claimed limitation] in response to a write command from an external device, and write the user data stored in the first memory to the second memory [(Paragraphs 0029-0033; FIG. 1-3 and related text) wherein Kawaguchi teaches where the PCI receiving unit 21 that receives data from the outside writes data to the memories (MEM) 31-34 via the memory space (first memory space) consisting of the last level caches (LLC) 231-234, that is, the last level caches (LLC) 231-234, and writes a flag for synchronizing data writing, to the communication register space (second memory space) consisting of the communication registers (CR) 221-224, as described below. However, in the present invention, as illustrated in FIG. 10, data may be written to the communication registers (CR) 221-224 (first memory space), and a flag may be written to the last level caches 231-234 (second memory space). Further, data and a flag may be written to the last level caches 231-234 (first memory space and the second memory space), or data and a flag may be written to the communication registers (CR) 221-224 (first memory space and the second memory space) to correspond to the claimed limitation], wherein when a data synchronization command is received from the external device, the controller writes the user data with a data synchronization indicator to the second memory [(Paragraphs 0029-0033 and 0047; FIG. 1-3 and related text) wherein Kawaguchi teaches where data may be written to the communication registers (CR) 221-224 (first memory space), and a flag may be written to the last level caches 231-234 (second memory space). Further, data and a flag may be written to the last level caches 231-234 (first memory space and the second memory space), or data and a flag may be written to the communication registers (CR) 221-224 (first memory space and the second memory space; further Kawaguchi discloses where data is transferred from the outside of the PCI and synchronization is established will be described as an example. As described above with reference to FIG. 10, any combinations of write destinations of data body and a flag are possible. In this example, the case where data body is written to the memory space and a flag for synchronization is written to the communication register space to correspond to the claimed limitation].
Kawaguchi does not appear to explicitly disclose wherein the second memory includes at least one memory device including a plurality of word lines, a plurality of bit lines, and a plurality of storage blocks; and wherein the controller writes the user data to data areas of one or more pages included in a target storage block among the plurality of storage blocks and write the data synchronization indicator to a spare area of at least one of the one or more pages upon receiving the data synchronization command.
However, Yamamoto discloses wherein the second memory includes at least one memory device including a plurality of word lines, a plurality of bit lines, and a plurality of storage blocks; and wherein the controller writes the user data to data areas of one or more pages included in a target storage block among the plurality of storage blocks and write the data synchronization indicator to a spare area of at least one of the one or more pages upon receiving the data synchronization command [(Paragraphs 0111- 0113 and 0122; Figs.1 and 4 and their related text) wherein the allocation restriction 2006 of the logical volume for storing data, which is read/written by the host 110 (hereinafter, host volume), may also be restricted. In this example, it is supposed that an allocation restriction 2006 is specified such that a real page, which is allocated to a cache volume from among multiple real pages based on a flash package group 280, not be allocated to a host volume; the storage controller 200 may release the relevant virtual page by moving the segment being used by the virtual page corresponding to this flag 2008 to another virtual page (that is, moving the data in the real page allocated to the virtual page corresponding to this flag 2008 to another real page, and, in addition, allocating this other real page to another virtual page). However, in this example, the storage controller 200 refrains from allocating a new segment included in this virtual page, waits for the previously allocated segment to be released, and releases the relevant virtual page to correspond to the claimed limitation].
Kawaguchi and Yamamoto are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Kawaguchi and Yamamoto before him or her, to modify the method of Kawaguchi to include the allocation operations of Yamamoto because it will enhance system performance.
The motivation for doing so would be [“an empty page is used as the cache area. For this reason, the cache capacity can be expanded relatively easily by dynamically allocating pages to the cache volume for the purpose of enhancing the hit ratio. Alternatively, in a case where the hit ratio is not improved much even though the cache capacity has been increased, the cache capacity can be decreased relatively easily by releasing a page from the cache volume” (Paragraph 0083 by Yamamoto)].
Therefore, it would have been obvious to combine Kawaguchi and Yamamoto to obtain the invention as specified in the instant claim.
As per dependent claim 5, Kawaguchi discloses wherein, when the data synchronization indicator is written to the spare area of the at least one of the one or more pages, the controller transmits a data synchronization response signal to the external device [(Paragraphs 0029-0033, 0037 and 0044; FIG. 1-3 and related text) wherein Kawaguchi teaches where the last level caches (LLC) 231-234 have synchronization establishment determination units 2312-2342. The synchronization establishment determination units 2312-2342 each have a function of, when receiving a synchronization command issued by the PCI receiving unit 21, returning a synchronization command reply at the time of writing the write data, held by each of the last level caches (LLC) 231-234, to the memories (MEM) 31-34, that is, at the time when the global visibility is established, as described below. When the global visibility is established, visibility of a preceding write command is guaranteed, when viewed from the processor core. This means that the last level caches (LLC) 231-234 each transmit a response representing that writing of write data is guaranteed, to the PCI receiving unit 21; further Kawaguchi teaches when synchronization between both spaces is established, the synchronization command receiving unit 212 determines that synchronization is completed, and transmits a reply to the special FENCE command to the processor core (CORE) 241-244 via the last level cache (LLC) 231-234 to correspond to the claimed limitation].
As per dependent claim 11, Yamamoto discloses wherein parity information is written to the spare areas of the one or more pages to which the user data is written [(Paragraphs 0112 and 0140-0141; FIG. 1 and 11 and related text) wherein Yamamoto teaches where the logical volume RAID group type 2003 specifies the RAID type of the relevant logical volume, such as RAID 0, RAID 1, and so forth. In a case where the parity data of the capacity of one storage unit is stored in the capacities of N storage units as in RAID 5; The processor 260 generates new parity data in the buffer 275 to correspond to the claimed limitation].
As for independent claim 14, the applicant is directed to the rejections to claim 1 set forth above, as they are rejected based on the same rationale.
Claim 3 is rejected under 35 U.S.C. 103(a) as being disclosed by Kawaguchi/Yamamoto, as applied to claim 1, and further in view of Lo et al. (US 8,984,247 hereinafter referred to as Lo).
As per dependent claim 3, Kawaguchi discloses the storage device according to claim 1.
Kawaguchi does not appear to explicitly disclose wherein the controller writes the data synchronization indicator to a spare area of a last page among the one or more pages to which the user data is written, the last page representing a page on which a program operation is performed most recently among the one or more pages.
However, Lo discloses wherein the controller writes the data synchronization indicator to a spare area of a last page among the one or more pages to which the user data is written, the last page representing a page on which a program operation is performed most recently among the one or more pages [(Column 6, lines 30-40; Figs. 4A-4C and their related text) wherein Lo teaches that the storage configuration of FIG. 4C, it can be seen that the most recently copied page 21C is the 28.sup.th (P.sub.tot) page (i.e., P.sub.27) written starting with page table page T.sub.0 written at page P.sub.0, including 6 table pages and 22 log pages. For the embodiment 400C depicted in FIG. 4C, the following equation may be used to calculate the oldest valid table page (P): P=P.sub.current-((T.sub.cnt-1).times.SegSize+(P.sub.tot% SegSize)); wherein P.sub.current is the location of the current pointer for data storage (e.g., the pointer may currently be pointing at P.sub.28, the page subsequent to the last written page; SegSize is the number of table pages saved per iteration plus the number of log pages saved per iteration to correspond to the claimed limitation].
Kawaguchi and Lo are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Kawaguchi and Lo before him or her, to modify the method of Kawaguchi to include the table data operations of Lo because it will enhance system performance.
The motivation for doing so would be [“increase the efficiency of table data reconstruction (e.g., mapping data, invalid table data, etc.) at power-up, the performance of which is often critical in applications such as solid-state storage devices” (Column 2, lines 50-55 by Lo)].
Therefore, it would have been obvious to combine Kawaguchi and Lo to obtain the invention as specified in the instant claim.
Claim 4 is rejected under 35 U.S.C. 103(a) as being disclosed by Kawaguchi/Yamamoto, as applied to claim 1, and further in view of Kavanagh et al. (US PGPUB 2019/0034452 hereinafter referred to as Kavanagh).
As per dependent claim 4, Kawaguchi discloses the storage device according to claim 1.
Kawaguchi does not appear to explicitly disclose wherein, when a total size of the user data stored in the first memory before receiving the data synchronization command is equal to or larger than a preset value, the controller writes the user data stored in the first memory to the data areas of the one or more pages.
However, Kavanagh discloses wherein, when a total size of the user data stored in the first memory before receiving the data synchronization command is equal to or larger than a preset value, the controller writes the user data stored in the first memory to the data areas of the one or more pages [(Paragraph 0176; Figs. 5A and their related text) wherein Kavanagh teaches that the requestor 2 uses the information about the value of the allocation counter 504 before the allocation counter 504 was updated based on the request 510 to determine whether requestor 2 should be responsible for rolling the file. For example, requestor 2 may determine that the allocation counter 504 was greater than the file size (i.e., 52 is greater than 50) before receiving requestor 2's request 510, and that the allocation counter 504 is also greater than the file size (i.e., 57 is greater than 50) after receiving requestor 2's request 510, and should not therefore be responsible for swapping the data store 500 for a new data store. Requestor 2 instead determines that it should wait until a new file is available before the data storage system can allocate space to store the 5 bytes associated with request 510 to correspond to the claimed limitation].
Kawaguchi and Kavanagh are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Kawaguchi and Lo before him or her, to modify the method of Kawaguchi to include the allocation operations of Kavanagh because it will enhance system performance.
The motivation for doing so would be [“eliminating file rolling conflicts which can corrupt the data or severely slow down the system” (Paragraph 0013 by Kavanagh)].
Therefore, it would have been obvious to combine Kawaguchi and Kavanagh to obtain the invention as specified in the instant claim.
Claim 12 is rejected under 35 U.S.C. 103(a) as being disclosed by Kawaguchi, in view of Kavanagh et al. (US PGPUB 2019/0034452 hereinafter referred to as Kavanagh), in view of Vishni et al. (US PGPUB 2016/0147671 hereinafter referred to as Vishni), and further in view of Edgington et al. (US 9,612,954 hereinafter referred to as Edgington).
As per dependent claim 12, Kawaguchi discloses a controller comprising: a buffer memory [(Paragraphs 0029-0033; FIG. 1-3 and related text) wherein Kawaguchi teaches where FIG. 3 illustrates the overall configuration of an information processing apparatus of the present embodiment. The information processing apparatus includes a PCI (Peripheral Component Interconnect) bus 1, a processor 2 mounted on a PCI card connected to the PCI bus 1, and memories (MEM) 31-34 mounted on the PCI card and connected to the processor 2. The PCI bus 1 is a standard PCI Express, and the memories are also standard memories to correspond to the claimed limitation]; and a processor configured to write user data to the buffer memory in response to a write command [(Paragraphs 0029-0033; FIG. 1-3 and related text) wherein Kawaguchi teaches where the PCI receiving unit 21 that receives data from the outside writes data to the memories (MEM) 31-34 via the memory space (first memory space) consisting of the last level caches (LLC) 231-234, that is, the last level caches (LLC) 231-234, and writes a flag for synchronizing data writing, to the communication register space (second memory space) consisting of the communication registers (CR) 221-224, as described below. However, in the present invention, as illustrated in FIG. 10, data may be written to the communication registers (CR) 221-224 (first memory space), and a flag may be written to the last level caches 231-234 (second memory space). Further, data and a flag may be written to the last level caches 231-234 (first memory space and the second memory space), or data and a flag may be written to the communication registers (CR) 221-224 (first memory space and the second memory space) to correspond to the claimed limitation], write the user data stored in the buffer memory to an external memory together with a data synchronization indicator when a data synchronization command is received [(Paragraphs 0029-0033 and 0047; FIG. 1-3 and related text) wherein Kawaguchi teaches where data may be written to the communication registers (CR) 221-224 (first memory space), and a flag may be written to the last level caches 231-234 (second memory space). Further, data and a flag may be written to the last level caches 231-234 (first memory space and the second memory space), or data and a flag may be written to the communication registers (CR) 221-224 (first memory space and the second memory space; further Kawaguchi discloses where data is transferred from the outside of the PCI and synchronization is established will be described as an example. As described above with reference to FIG. 10, any combinations of write destinations of data body and a flag are possible. In this example, the case where data body is written to the memory space and a flag for synchronization is written to the communication register space to correspond to the claimed limitation].
Kawaguchi does not appear to explicitly disclose write the user data stored in the buffer memory to the external memory without writing the data synchronization indicator to the external memory when a total size of the user data stored in the buffer memory is equal to or larger than a preset value before the data synchronization command is received.
However, Kavanagh discloses write the user data stored in the buffer memory to the external memory without writing the data synchronization indicator to the external memory when a total size of the user data stored in the buffer memory is equal to or larger than a preset value before the data synchronization command is received [(Paragraph 0176; Figs. 5A and their related text) wherein Kavanagh teaches that the requestor 2 uses the information about the value of the allocation counter 504 before the allocation counter 504 was updated based on the request 510 to determine whether requestor 2 should be responsible for rolling the file. For example, requestor 2 may determine that the allocation counter 504 was greater than the file size (i.e., 52 is greater than 50) before receiving requestor 2's request 510, and that the allocation counter 504 is also greater than the file size (i.e., 57 is greater than 50) after receiving requestor 2's request 510, and should not therefore be responsible for swapping the data store 500 for a new data store. Requestor 2 instead determines that it should wait until a new file is available before the data storage system can allocate space to store the 5 bytes associated with request 510 to correspond to the claimed limitation].
Kawaguchi and Kavanagh are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Kawaguchi and Lo before him or her, to modify the method of Kawaguchi to include the allocation operations of Kavanagh because it will enhance system performance.
The motivation for doing so would be [“eliminating file rolling conflicts which can corrupt the data or severely slow down the system” (Paragraph 0013 by Kavanagh)].
Kawaguchi does not appear to explicitly disclose write the user data stored in the buffer memory to the external memory without writing the data synchronization indicator to the external memory.
However, Vishni discloses write the user data stored in the buffer memory to the external memory without writing the data synchronization indicator to the external memory [(Paragraph 0019 and their related text) wherein Vishni teaches that the write cache 126 is maintained in volatile memory. Thus, loss of power may result in loss of data in the write cache 126. Since data in the write cache 126 is associated with commands indicated as complete, to keep an accurate record of data written to the non-volatile memory 104 (not just to the write cache 126), the accessing device 150 may occasionally issue a flush command 174. The flush command 174 instructs the data storage device 102 to write all data that is stored in the write cache 126 to the non-volatile memory 104. After the data in the write cache 126 is written to the non-volatile memory 104, the data storage device 102 may generate an output indicating completion of the flush command 174. For example, the data storage device 102 may provide a committed indication 176. The committed indication 176 may indicate to the accessing device 150 that all data associated with write commands previously identified in the completion queue 156 has been written to the non-volatile memory 104. In a particular embodiment, the committed indication 176 corresponds to a completed indication associated with a flush command. To illustrate, in the NVMe specification, flush commands and write commands each follow the same process flow. Thus, the flush command may be submitted to one of the submission queues 152 and copied to the data storage device 102 as a pending command. When the flush command is executed (e.g., when all data in the write cache 126 has been written to the non-volatile memory 104), the controller 106 may indicate the flush command as complete by updating a completion queue associated with the flush command to correspond to the claimed limitation].
Kawaguchi and Vishni are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Kawaguchi and Lo before him or her, to modify the method of Kawaguchi to include the allocation operations of Kavanagh because it will enhance system performance.
The motivation for doing so would be [“improving efficiency of use of the storage capacity of the non-volatile memory” (Paragraph 0004 by Vishni)].
Kawaguchi does not appear to explicitly disclose wherein the processor is configured to separately manage the user data written to the external memory based on the data synchronization indicator.
However, Edgington discloses wherein the processor is configured to separately manage the user data written to the external memory based on the data synchronization indicator [(Column 4, lines 24-31 and Column 6, lines 10-27 and their related text) wherein Edgington teaches that the header is used to write a commit marker when the page has been successfully fully programmed or written to. The commit marker can be used to indicate whether a programming operation has been successfully completed or not. The marker is written after a programming operation is completed successfully. For flash memory, after the cells are flashed, or erased, the process of writing to the cells is referred to as programming; If the page does not contain any data, then at box 217, the page is marked as dirty. Note that, only the first empty page found in the managed device is marked dirty with the approach described in FIG. 2, and the following page becomes the first free page. At box 219, it is determined whether this page is the last page. If it is not, then at box 221, the next page is marked as a free page and at box 223, the process ends. On the other hand if this page with no data is the last page, then at box 225, there is no free page and the process ends at box 223. If a page in the scan does contain data, then the process next checks the header for a commit marker at box 227. In this example, after a page is successfully and completely written, then a commit marker is written into the header. As an alternative, there is a commit marker only for an entire block. This saves time when writing to each page and because a power loss is a rare event, there is rarely any impact on system recovery when there is a power loss to correspond to the claimed limitation].
Kawaguchi/Kavanagh and Edgington are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Kawaguchi and Edgington before him or her, to modify the method of Kawaguchi to include the commit marker indicator of Edgington because it will enhance system performance.
The motivation for doing so would be [“better memory life cycles by reducing the number of writes. It also helps avoid hardware errors especially for NAND type flash memory devices” (Column 2, lines 20-23 by Edgington)].
Therefore, it would have been obvious to combine Kawaguchi/Kavanagh and Edgington to obtain the invention as specified in the instant claim.
a(2) CLAIMS ALLOWED IN THE APPLICATION
Per the instant office action, claims 6-10, 13 and 15-16, but would be allowable if claims are rewritten in an independent form.
The reason for allowance of claims 6-10 is that the prior art of record, neither anticipates, nor renders obvious the recited combination as a whole; including:
for claim 6, the limitations of “wherein in a recovery operation resulting from a sudden power-off, the controller copies, to a temporary storage block among the plurality of storage blocks, user data stored in a data area of a target page among the one or more pages when the target page includes a spare area where the data synchronization indicator is stored”.
The reason for allowance of claim 13 is that the prior art of record, neither anticipates, nor renders obvious the recited combination as a whole; including:
for claim 13, the limitations of “wherein in a recovery operation resulting from a sudden power-off, the processor determines whether to copy the user data stored in a target storage block of the external memory to another storage block of the external memory based on whether the user data is written to the external memory together with the data synchronization indicator”.
The reason for allowance of claims 15-16 is that the prior art of record, neither anticipates, nor renders obvious the recited combination as a whole; including:
for claim 15, the limitations of “wherein in a recovery operation resulting from a sudden power-off, the method further comprises: reading a spare area of a target page corresponding to a word line which was activated just before the occurrence of the sudden power-off, wherein the target page stores at least a portion of the user data; and copying user data stored in a data area of the target page to a temporary storage block of the second memory when the data synchronization indicator is stored in the spare area of the target page”.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Mohamed Gebril whose telephone number is (571)270-1857 and email address is mohamed.gebril @uspto.gov. The examiner can normally be reached on Monday-Friday, 8:00am-5:00pm.ALT. Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jared Rutz can be reached on 571-272-5535. The fax phone number for the organization where this application or proceeding is assigned is 571-270-2857.
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/MOHAMED M GEBRIL/Primary Examiner, Art Unit 2135
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