The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-16 are presented for examination in this application (18/612,942) filed on March 21, 2024.
The Examiner cites particular sections in the references as applied to the claims below for the convenience of the applicant(s). Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant(s) fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
Claims 1-16 are pending for consideration.
Drawings
The drawings submitted on March 21, 2024 have been considered and accepted.
Information Disclosure Statement
Acknowledgment is made of the information disclosure statements filed on March 21, 2024. U.S. patents and Foreign Patents have been considered.
Claim Rejections - 35 U.S.C. 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 2 is rejected under 35 U.S.C. 112 (b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as claims recite “at least one of the one or more pages”, where it is unclear if this at least one of the one or more pages is the same as the at least one of the one or more pages included in a target storage block or different.
Claim 4 is rejected under 35 U.S.C. 112 (b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as claims recite “the data areas of the at least one of the one or more pages”, where it is unclear if this at least one of the one or more pages is the same as the at least one of the one or more pages included in a target storage block of claim 2 or different.
Claim 11 recites “the spare areas”, where there is an insufficient antecedent basis for this limitation in the claim, claim further recites “to which the user data is written”, where it is unclear if the user data is stored at the location or the data synchronization indicator as in claim 2.
Claim 14 is rejected under 35 U.S.C. 112 (a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as claims recite “writing a data synchronization indicator to a spare area of the page”, specification recites “ the controller 120 may not write the data synchronization indicator DSI to the spare areas SA of the pages PG. Alternatively, the controller 120 may write to the spare areas SA of the pages PG a value that is different from the data synchronization indicator DSI written when the data synchronization command is received”, (Paragraph 0113) where the writing is performed to the spare areas of multiple pages not a single page as claim and no recitation of the specification of writing into the spare area of a single page.
All dependent claims are rejected as having the same deficiencies as the claims they depend from.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 14 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Kawaguchi et al. (US PGPUB 2018/0246808 hereinafter referred to as Kawaguchi).
As per independent claim 1, Kawaguchi discloses a storage device comprising: a first memory; a second memory; and a controller configured to write user data to the first memory [(Paragraphs 0029-0033; FIG. 1-3 and related text) wherein Kawaguchi teaches where FIG. 3 illustrates the overall configuration of an information processing apparatus of the present embodiment. The information processing apparatus includes a PCI (Peripheral Component Interconnect) bus 1, a processor 2 mounted on a PCI card connected to the PCI bus 1, and memories (MEM) 31-34 mounted on the PCI card and connected to the processor 2. The PCI bus 1 is a standard PCI Express, and the memories are also standard memorie to correspond to the claimed limitation] in response to a write command from an external device, and write the user data stored in the first memory to the second memory [(Paragraphs 0029-0033; FIG. 1-3 and related text) wherein Kawaguchi teaches where the PCI receiving unit 21 that receives data from the outside writes data to the memories (MEM) 31-34 via the memory space (first memory space) consisting of the last level caches (LLC) 231-234, that is, the last level caches (LLC) 231-234, and writes a flag for synchronizing data writing, to the communication register space (second memory space) consisting of the communication registers (CR) 221-224, as described below. However, in the present invention, as illustrated in FIG. 10, data may be written to the communication registers (CR) 221-224 (first memory space), and a flag may be written to the last level caches 231-234 (second memory space). Further, data and a flag may be written to the last level caches 231-234 (first memory space and the second memory space), or data and a flag may be written to the communication registers (CR) 221-224 (first memory space and the second memory space) to correspond to the claimed limitation], wherein when a data synchronization command is received from the external device, the controller writes the user data with a data synchronization indicator to the second memory [(Paragraphs 0029-0033 and 0047; FIG. 1-3 and related text) wherein Kawaguchi teaches where data may be written to the communication registers (CR) 221-224 (first memory space), and a flag may be written to the last level caches 231-234 (second memory space). Further, data and a flag may be written to the last level caches 231-234 (first memory space and the second memory space), or data and a flag may be written to the communication registers (CR) 221-224 (first memory space and the second memory space; further Kawaguchi discloses where data is transferred from the outside of the PCI and synchronization is established will be described as an example. As described above with reference to FIG. 10, any combinations of write destinations of data body and a flag are possible. In this example, the case where data body is written to the memory space and a flag for synchronization is written to the communication register space to correspond to the claimed limitation].
As for independent claim 14, the applicant is directed to the rejections to claim 1 set forth above, as they are rejected based on the same rationale.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 5 and 11 is rejected under 35 U.S.C. 103(a) as being disclosed by Kawaguchi, as applied to claim1, and further in view of Yamamoto et al. (US PGPUB 2013/0318196 hereinafter referred to as Yamamoto).
As per dependent claim 2, Kawaguchi discloses the storage device according to claim 1.
Kawaguchi does not appear to explicitly disclose wherein the second memory includes at least one memory device including a plurality of word lines, a plurality of bit lines, and a plurality of storage blocks; and wherein the controller writes the user data to data areas of one or more pages included in a target storage block among the plurality of storage blocks and write the data synchronization indicator to a spare area of at least one of the one or more pages upon receiving the data synchronization command.
However, Yamamoto discloses wherein the second memory includes at least one memory device including a plurality of word lines, a plurality of bit lines, and a plurality of storage blocks; and wherein the controller writes the user data to data areas of one or more pages included in a target storage block among the plurality of storage blocks and write the data synchronization indicator to a spare area of at least one of the one or more pages upon receiving the data synchronization command [(Paragraphs 0111- 0113 and 0122; Figs.1 and 4 and their related text) wherein the allocation restriction 2006 of the logical volume for storing data, which is read/written by the host 110 (hereinafter, host volume), may also be restricted. In this example, it is supposed that an allocation restriction 2006 is specified such that a real page, which is allocated to a cache volume from among multiple real pages based on a flash package group 280, not be allocated to a host volume; the storage controller 200 may release the relevant virtual page by moving the segment being used by the virtual page corresponding to this flag 2008 to another virtual page (that is, moving the data in the real page allocated to the virtual page corresponding to this flag 2008 to another real page, and, in addition, allocating this other real page to another virtual page). However, in this example, the storage controller 200 refrains from allocating a new segment included in this virtual page, waits for the previously allocated segment to be released, and releases the relevant virtual page to correspond to the claimed limitation].
Kawaguchi and Yamamoto are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Kawaguchi and Yamamoto before him or her, to modify the method of Kawaguchi to include the allocation operations of Yamamoto because it will enhance system performance.
The motivation for doing so would be [“an empty page is used as the cache area. For this reason, the cache capacity can be expanded relatively easily by dynamically allocating pages to the cache volume for the purpose of enhancing the hit ratio. Alternatively, in a case where the hit ratio is not improved much even though the cache capacity has been increased, the cache capacity can be decreased relatively easily by releasing a page from the cache volume” (Paragraph 0083 by Yamamoto)].
Therefore, it would have been obvious to combine Kawaguchi and Yamamoto to obtain the invention as specified in the instant claim.
As per dependent claim 5, Kawaguchi discloses wherein, when the data synchronization indicator is written to the spare area of the at least one of the one or more pages, the controller transmits a data synchronization response signal to the external device [(Paragraphs 0029-0033, 0037 and 0044; FIG. 1-3 and related text) wherein Kawaguchi teaches where the last level caches (LLC) 231-234 have synchronization establishment determination units 2312-2342. The synchronization establishment determination units 2312-2342 each have a function of, when receiving a synchronization command issued by the PCI receiving unit 21, returning a synchronization command reply at the time of writing the write data, held by each of the last level caches (LLC) 231-234, to the memories (MEM) 31-34, that is, at the time when the global visibility is established, as described below. When the global visibility is established, visibility of a preceding write command is guaranteed, when viewed from the processor core. This means that the last level caches (LLC) 231-234 each transmit a response representing that writing of write data is guaranteed, to the PCI receiving unit 21; further Kawaguchi teaches when synchronization between both spaces is established, the synchronization command receiving unit 212 determines that synchronization is completed, and transmits a reply to the special FENCE command to the processor core (CORE) 241-244 via the last level cache (LLC) 231-234 to correspond to the claimed limitation].
As per dependent claim 11, Yamamoto discloses wherein parity information is written to the spare areas of the one or more pages to which the user data is written [(Paragraphs 0112 and 0140-0141; FIG. 1 and 11 and related text) wherein Yamamoto teaches where the logical volume RAID group type 2003 specifies the RAID type of the relevant logical volume, such as RAID 0, RAID 1, and so forth. In a case where the parity data of the capacity of one storage unit is stored in the capacities of N storage units as in RAID 5; The processor 260 generates new parity data in the buffer 275 to correspond to the claimed limitation].
Claim 3 is rejected under 35 U.S.C. 103(a) as being disclosed by Kawaguchi/Yamamoto, as applied to claim 2, and further in view of Lo et al. (US 8,984,247 hereinafter referred to as Lo).
As per dependent claim 3, Kawaguchi discloses the storage device according to claim 2.
Kawaguchi does not appear to explicitly disclose wherein the controller writes the data synchronization indicator to a spare area of a last page among the one or more pages to which the user data is written, the last page representing a page on which a program operation is performed most recently among the one or more pages.
However, Lo discloses wherein the controller writes the data synchronization indicator to a spare area of a last page among the one or more pages to which the user data is written, the last page representing a page on which a program operation is performed most recently among the one or more pages [(Column 6, lines 30-40; Figs. 4A-4C and their related text) wherein Lo teaches that the storage configuration of FIG. 4C, it can be seen that the most recently copied page 21C is the 28.sup.th (P.sub.tot) page (i.e., P.sub.27) written starting with page table page T.sub.0 written at page P.sub.0, including 6 table pages and 22 log pages. For the embodiment 400C depicted in FIG. 4C, the following equation may be used to calculate the oldest valid table page (P): P=P.sub.current-((T.sub.cnt-1).times.SegSize+(P.sub.tot% SegSize)); wherein P.sub.current is the location of the current pointer for data storage (e.g., the pointer may currently be pointing at P.sub.28, the page subsequent to the last written page; SegSize is the number of table pages saved per iteration plus the number of log pages saved per iteration to correspond to the claimed limitation].
Kawaguchi and Lo are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Kawaguchi and Lo before him or her, to modify the method of Kawaguchi to include the table data operations of Lo because it will enhance system performance.
The motivation for doing so would be [“increase the efficiency of table data reconstruction (e.g., mapping data, invalid table data, etc.) at power-up, the performance of which is often critical in applications such as solid-state storage devices” (Column 2, lines 50-55 by Lo)].
Therefore, it would have been obvious to combine Kawaguchi and Lo to obtain the invention as specified in the instant claim.
Claim 4 is rejected under 35 U.S.C. 103(a) as being disclosed by Kawaguchi/Yamamoto, as applied to claim 2, and further in view of Kavanagh et al. (US PGPUB 2019/0034452 hereinafter referred to as Kavanagh).
As per dependent claim 4, Kawaguchi discloses the storage device according to claim 2.
Kawaguchi does not appear to explicitly disclose wherein, when a total size of the user data stored in the first memory before receiving the data synchronization command is equal to or larger than a preset value, the controller writes the user data stored in the first memory to the data areas of the one or more pages.
However, Kavanagh discloses wherein, when a total size of the user data stored in the first memory before receiving the data synchronization command is equal to or larger than a preset value, the controller writes the user data stored in the first memory to the data areas of the one or more pages [(Paragraph 0176; Figs. 5A and their related text) wherein Kavanagh teaches that the requestor 2 uses the information about the value of the allocation counter 504 before the allocation counter 504 was updated based on the request 510 to determine whether requestor 2 should be responsible for rolling the file. For example, requestor 2 may determine that the allocation counter 504 was greater than the file size (i.e., 52 is greater than 50) before receiving requestor 2's request 510, and that the allocation counter 504 is also greater than the file size (i.e., 57 is greater than 50) after receiving requestor 2's request 510, and should not therefore be responsible for swapping the data store 500 for a new data store. Requestor 2 instead determines that it should wait until a new file is available before the data storage system can allocate space to store the 5 bytes associated with request 510 to correspond to the claimed limitation].
Kawaguchi and Kavanagh are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Kawaguchi and Lo before him or her, to modify the method of Kawaguchi to include the allocation operations of Kavanagh because it will enhance system performance.
The motivation for doing so would be [“eliminating file rolling conflicts which can corrupt the data or severely slow down the system” (Paragraph 0013 by Kavanagh)].
Therefore, it would have been obvious to combine Kawaguchi and Kavanagh to obtain the invention as specified in the instant claim.
Claim 12 is rejected under 35 U.S.C. 103(a) as being disclosed by Kawaguchi, and further in view of Kavanagh et al. (US PGPUB 2019/0034452 hereinafter referred to as Kavanagh).
As per dependent claim 12, Kawaguchi discloses a controller comprising: a buffer memory [(Paragraphs 0029-0033; FIG. 1-3 and related text) wherein Kawaguchi teaches where FIG. 3 illustrates the overall configuration of an information processing apparatus of the present embodiment. The information processing apparatus includes a PCI (Peripheral Component Interconnect) bus 1, a processor 2 mounted on a PCI card connected to the PCI bus 1, and memories (MEM) 31-34 mounted on the PCI card and connected to the processor 2. The PCI bus 1 is a standard PCI Express, and the memories are also standard memories to correspond to the claimed limitation]; and a processor configured to write user data to the buffer memory in response to a write command [(Paragraphs 0029-0033; FIG. 1-3 and related text) wherein Kawaguchi teaches where the PCI receiving unit 21 that receives data from the outside writes data to the memories (MEM) 31-34 via the memory space (first memory space) consisting of the last level caches (LLC) 231-234, that is, the last level caches (LLC) 231-234, and writes a flag for synchronizing data writing, to the communication register space (second memory space) consisting of the communication registers (CR) 221-224, as described below. However, in the present invention, as illustrated in FIG. 10, data may be written to the communication registers (CR) 221-224 (first memory space), and a flag may be written to the last level caches 231-234 (second memory space). Further, data and a flag may be written to the last level caches 231-234 (first memory space and the second memory space), or data and a flag may be written to the communication registers (CR) 221-224 (first memory space and the second memory space) to correspond to the claimed limitation], write the user data stored in the buffer memory to an external memory together with a data synchronization indicator when a data synchronization command is received [(Paragraphs 0029-0033 and 0047; FIG. 1-3 and related text) wherein Kawaguchi teaches where data may be written to the communication registers (CR) 221-224 (first memory space), and a flag may be written to the last level caches 231-234 (second memory space). Further, data and a flag may be written to the last level caches 231-234 (first memory space and the second memory space), or data and a flag may be written to the communication registers (CR) 221-224 (first memory space and the second memory space; further Kawaguchi discloses where data is transferred from the outside of the PCI and synchronization is established will be described as an example. As described above with reference to FIG. 10, any combinations of write destinations of data body and a flag are possible. In this example, the case where data body is written to the memory space and a flag for synchronization is written to the communication register space to correspond to the claimed limitation].
Kawaguchi does not appear to explicitly disclose write the user data stored in the buffer memory to the external memory without the data synchronization indicator when a total size of the user data stored in the buffer memory is equal to or larger than a preset value before the data synchronization command is received.
However, Kavanagh discloses write the user data stored in the buffer memory to the external memory without the data synchronization indicator when a total size of the user data stored in the buffer memory is equal to or larger than a preset value before the data synchronization command is received [(Paragraph 0176; Figs. 5A and their related text) wherein Kavanagh teaches that the requestor 2 uses the information about the value of the allocation counter 504 before the allocation counter 504 was updated based on the request 510 to determine whether requestor 2 should be responsible for rolling the file. For example, requestor 2 may determine that the allocation counter 504 was greater than the file size (i.e., 52 is greater than 50) before receiving requestor 2's request 510, and that the allocation counter 504 is also greater than the file size (i.e., 57 is greater than 50) after receiving requestor 2's request 510, and should not therefore be responsible for swapping the data store 500 for a new data store. Requestor 2 instead determines that it should wait until a new file is available before the data storage system can allocate space to store the 5 bytes associated with request 510 to correspond to the claimed limitation].
Kawaguchi and Kavanagh are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Kawaguchi and Lo before him or her, to modify the method of Kawaguchi to include the allocation operations of Kavanagh because it will enhance system performance.
The motivation for doing so would be [“eliminating file rolling conflicts which can corrupt the data or severely slow down the system” (Paragraph 0013 by Kavanagh)].
Therefore, it would have been obvious to combine Kawaguchi and Kavanagh to obtain the invention as specified in the instant claim.
a(2) CLAIMS ALLOWED IN THE APPLICATION
Per the instant office action, claims 6-10 and 15-16, but would be allowable if claims are amended to overcome the 112 rejections.
The reason for allowance of claims 6-10 is that the prior art of record, neither anticipates, nor renders obvious the recited combination as a whole; including:
for claim 6, the limitations of “wherein in a recovery operation resulting from a sudden power-off, the controller copies, to a temporary storage block among the plurality of storage blocks, user data stored in a data area of a target page among the one or more pages when the target page includes a spare area where the data synchronization indicator is stored”.
The reason for allowance of claim 13 is that the prior art of record, neither anticipates, nor renders obvious the recited combination as a whole; including:
for claim 13, the limitations of “wherein in a recovery operation resulting from a sudden power-off, the processor determines whether to copy the user data stored in a target storage block of the external memory to another storage block of the external memory based on whether the user data is written to the external memory together with the data synchronization indicator”.
The reason for allowance of claims 15-16 is that the prior art of record, neither anticipates, nor renders obvious the recited combination as a whole; including:
for claim 15, the limitations of “wherein in a recovery operation resulting from a sudden power-off, the method further comprises: reading a spare area of a target page corresponding to a word line which was activated just before the occurrence of the sudden power-off, wherein the target page stores at least a portion of the user data; and copying user data stored in a data area of the target page to a temporary storage block of the second memory when the data synchronization indicator is stored in the spare area of the target page”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jared Ian Rutz whose telephone number is (571)272-5535. The examiner can normally be reached on Monday-Friday, 8:00 AM to 4:00 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jared Rutz can be reached on 571-272-5535. The fax phone number for the organization where this application or proceeding is assigned is 571-270-2857.
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/MOHAMED M GEBRIL/Primary Examiner, Art Unit 2135