DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/23/2025 has been entered.
This Action is in response to communications filed 12/23/2025.
Claim 21 is cancelled.
Claim 22 is newly added.
Claims 1-2, 9-10, and 17 have been amended.
Claims 1-20 and 22 are pending.
Claims 1-20 and 22 are rejected.
Response to Amendment
The Examiner notes claim 2 appears to include amendments not properly documented. Specifically, the previous entered filing of record dated 06/30/2025, claim 2 recited the limitation “the third memory die is coupled to the memory controller circuitry via a second controller.” The currently filed version of claim 2 now recites “a third memory die associated with the first identifier and [[and]] coupled to the memory controller via a second channel” wherein the “channel” is not clearly indicated as an amendment to the claim. For the current action and purposes of compact prosecution, the limitation is interpreted as including “the second channel” as opposed to “the second controller” and corresponding rejections are revised in view of the amendment made the limitation.
Response to Arguments
In Remarks filed on 12/23/2025, Applicant substantially argues:
The applied references fail to disclose the amended limitations of claim 1, and similarly amended claims 9 and 17, as discussed during the interview conducted on 12/08/2025. Applicant’s arguments filed have been fully considered but are moot in view of the current rejections made in response to Applicant’s amendments.
The applied references fail to disclose the limitations of claims 2-8, 10-16, and 10-20 by virtue of dependency on respective independent claims 1, 9, and 17 for the reasons identified above. Applicant’s arguments filed have been fully considered but are moot in view of the current rejections made in response to Applicant’s amendments.
Newly added claim 22 is addressed for the first time in the current action.
All arguments by the applicant are believed to be covered in the body of the office action; thus, this action constitutes a complete response to the issues raised in the remarks dated December 23, 2025.
Claim Objections
Claim 2 is objected to because of the following informalities:
In view of the amendments filed 12/23/2025, claim 2 recites a typographical error regarding duplicate recitation in the limitation “the memory system of claim 1 further comprising: a third memory die associated with the first identifier, and and coupled to the memory controller circuitry via a second channel”.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103(a) are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-20 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Keeth (US 2022/0121393) in view of Palmer (US 2022/0229580) and further in view of Webb et al. (US 2015/0378814).
Regarding claim 1, Keeth discloses, in the italicized portions, a memory system comprising: a first memory die group comprising a first memory die, wherein the first memory die is associated with a first channel and a first identifier; a first temperature sensor associated with the first memory die; a second memory die group comprising a second memory die, wherein the second memory die is associated with the first channel and a second identifier (Figure 1A, stack of DRAM dies 122, Paragraph [0026] Memory sub-channels each connecting to one or more memory die); a second temperature sensor associated with the second memory die; and memory controller circuitry coupled to the first memory die, the first temperature sensor, the second memory die, and the second temperature sensor (Figure 9, refresh controller 916, Paragraph [0073]), wherein the memory controller circuitry is configured to: send a first request for first temperature information to the first memory die via the first channel and using the first identifier and a second request for second information to the second memory die via the first channel and using the second identifier; receive the first temperature information corresponding to a first temperature of the first memory die from the first temperature sensor via the first channel and using the first identifier; receive the second temperature information corresponding to a second temperature of the second memory die from the second temperature sensor via the first channel and using the second identifier ([0076] As a result, the refresh controller 916 may refresh such regions at a different, quicker, rate than other regions are refreshed. In another example, BIST logic 318 may identify a performance metric that a memory die, or a portion of a memory die, is operating at a temperature different than other portions of the multiple memory devices.); output a first refresh signal to the first memory die based on a first refresh rate for the first memory die, wherein the first refresh rate is based on the first temperature information; and output a second refresh signal to the second memory die based on a second refresh rate for the second memory die, wherein the second refresh rate is based on the second temperature information, and wherein the second refresh rate differs from the first refresh rate ([0076] For example, in a stack of memory devices, a memory device within the stack may operate at relatively elevated temperature relative to more outwardly placed devices. In other examples, and elevated temperature may result from an abnormally high number of memory region accesses. Because such elevated temperatures may promote undesirable leakage from the storage device, in response to BIST logic 318 identifying and elevated temperature region, the refresh rate may be increased to overcome the potential increased leakage.). Herein Keeth teaches the plurality of memory dies in communication with a memory controller, via a plurality of memory sub-channels, which controls the refresh operations performed by the memory device based on monitored temperature metrics of respective memory dies or portions thereof. Specifically, Keeth identifies the refresh rate of respective portions based on the temperature also takes into account the position within the stack as interior portions may exhibit higher temperatures than more outwardly positioned portions. In this case, the refresh rates of a first memory die and second memory die would be recognized as being different based on the positioning. Keeth does not explicitly disclose the elements of the first and second temperature sensors associated with the first and second memory dies which send the respective temperature information to the memory controller or using respective first and second identifiers to request from the memory dies. Regarding the respective temperature sensors, Palmer discloses in Paragraph [0062] “The memory system 210 may support a temperature tracking mechanism for one or more memory devices 240 to support temperature compensations on read operations. For example, the storage controller 230, a memory device 240, or both, may include a temperature sensor 275. In some cases, the storage controller 230 may include a temperature sensor 275-a and one or more memory devices 240 may include respective temperature sensors 275-b (e.g., at one or more NAND dies, as described with reference to FIG. 1). The temperature sensors 275 may perform temperature readings for the memory system 210 or a specific memory device 240.” Herein Palmer explicitly discloses that each NAND die may include a respective temperature sensor for transmitting temperature data. As additionally discussed in Paragraph [0066], the memory system uses the temperature data to perform mitigation procedures for the data to improve data retention accuracy which would involve performing refresh operations. As such, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide temperature sensors at each of the memory dies in order to obtain corresponding temperature information to then control data retention operations including managing refresh rates as discussed in Keeth to maintain the accuracy of data stored therein by the respective memory die (Palmer [0067]). Regarding the use of respective first and second identifiers to request first and second memory dies associated with the first channel, Webb discloses in Paragraphs [0026-27] “[0026] Topology includes whether EN hub(s) are attached to the controller channel port(s) Ch 0, . . . , Ch n, a number of EN hub(s) in each chain, a number of interface ports on each attached EN hub and a storage capacity of each attached NVM device. The initialize chain command may be further configured to assign a unique identifier to each EN hub, identify each interface port and/or to assign a volume address to each NVM die… [0027] In operation, memory accesses may be initiated by selecting an EN hub and/or selecting an interface port on a selected EN hub. For example, the EN hub logic 108 may send a select hub and/or select port command to an EN hub assembly that includes the selected EN hub. In another example, the EN hub logic may send a select volume command and/or a control signal that corresponds to an encoded chip enable identifier. The command may be followed by e.g., the unique EN hub identifier, interface port number and volume address of a target NVM die. Memory access operations may then be sent that comply and/or are compatible with an NVM interface specification and/or protocol.” Herein Webb discloses accessing specific memory dies along particular channels using identifiers which uniquely identify the target NVM die. In this manner, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the communication structure as discussed in Webb in the context of Keeth and Palmer for managing memory die operation as Webb further discloses managing groups of memory targets thereby reduces the number of pins necessary to connect between the controller and memory targets (Webb [0030]). Keeth, Palmer, and Webb are analogous art because they are from the same field of endeavor of managing data retention.
Regarding claim 2, Keeth and Webb in combination further discloses the memory system of claim 1 further comprising: a third memory die (Figure 1A, stack of DRAM dies 122) associated with the first identifier, and and coupled to the memory controller circuitry via a second channel (Keeth [0073] As such, the buffer die 900 can allow the connected device to provide better performance or use the freed-up resources to provide additional functionality. In certain examples, the refresh controller 916 can refresh a certain block of memory cells such as a rank of memory or a bank of memory. A rank of memory is typically associated with a chip select or chip ID signal. Webb [0026-27]. Herein Keeth teaches the plurality of DRAM die connected to control logic via a plurality of channels. Furthermore, Keeth identifies different ranks of memory may be associated with different ID signals thereby differentiating between different groups of memory which may communicate along different channels to the memory controller. Additionally, Webb discloses each memory die along each channel is associated with a unique identifier which may be applied to groups of memory targets.
Regarding claim 3, Keeth, Palmer, and Webb in combination further disclose the memory system of claim 2, wherein the memory controller circuitry is further configured to receive third temperature information corresponding to a third temperature of the third memory die, and wherein the first refresh rate is further based on the third temperature information, and wherein the first refresh rate is further for the third memory die (Keeth Paragraph [0076], BIST logic 318 using a performance metric of a portion of memory to control the refresh rate). Herein Keeth notes use of performance metrics to adjust the refresh rate of the associated memory which includes basing it on temperature. Additionally, Paragraphs [0102] and [0110] identify ranks of memory comprising a plurality of portions of a plurality of memory die. In this case, the refresh rate applied to one rank of memory is subject to the temperature information of each portion which form the rank and the refresh rate is applied to all portions. Palmer in Paragraphs [0089-90] additionally supports memory die specific operations being applied based on temperature.
Regarding claim 4, Keeth, Palmer, and Webb in combination further disclose the memory system of claim 3, wherein the memory controller circuitry is further configured to: output the first refresh signal to the third memory die (Keeth [0073] and [0076]). Herein Keeth discloses the refresh controller coordinating refresh operations for ranks of memory, which may be formed by a plurality of die or portions, based on a refresh rate respective to each grouping.
Regarding claim 5, Keeth, Palmer, and Webb in combination further disclose the memory system of claim 2, wherein the memory controller circuitry is further configured to: receive third temperature information from the third memory die; and determine a third refresh rate for the third memory die based on the third temperature information (Keeth [0073] and [0076]). Herein Keeth discloses refresh rates for a memory die may be determined based on a respective performance metric of the memory die including temperature. In this case, each memory die may be subject to a respective refresh rate based on the monitored operation temperature. Palmer in Paragraphs [0089-90] additionally supports memory die specific operations being applied based on temperature.
Regarding claim 6, Keeth, Palmer, and Webb in combination further disclose the memory system of claim 5, wherein the memory controller circuitry is further configured to: output a third refresh signal to the third memory die based on the third refresh rate (Keeth [0073] and [0076]). Herein Keeth discloses refresh rates for a memory die may be determined based on a respective performance metric of the memory die including temperature. In this case, each memory die may be subject to a respective refresh rate based on the monitored operation temperature. As noted in the rejection of claim 5, Palmer supports memory die specific operations.
Regarding claim 7, Keeth further discloses the memory system of claim 1, wherein the first temperature of the first memory die is greater than the second temperature of the second memory die, and wherein the first refresh rate is greater than the second refresh rate ([0076] As a result, the refresh controller 916 may refresh such regions at a different, quicker, rate than other regions are refreshed. In another example, BIST logic 318 may identify a performance metric that a memory die, or a portion of a memory die, is operating at a temperature different than other portions of the multiple memory devices. For example, in a stack of memory devices, a memory device within the stack may operate at relatively elevated temperature relative to more outwardly placed devices. In other examples, and elevated temperature may result from an abnormally high number of memory region accesses. Because such elevated temperatures may promote undesirable leakage from the storage device, in response to BIST logic 318 identifying and elevated temperature region, the refresh rate may be increased to overcome the potential increased leakage.). Herein Keeth explicitly recites that a memory region, or die, with a relatively elevated temperature may result in a higher refresh rate. Conversely, the lower temperature memory region, or die, will experience a lower refresh rate.
Regarding claim 8, Keeth further discloses the memory system of claim 1, wherein the first memory die and the second memory die are vertically stacked on each other (Figure 8A, DRAM dies 810 stacked vertically). Herein Keeth identifies the orientation of the DRAM dies as being stacked vertically.
Regarding claim 9, Keeth discloses, in the italicized portions, a memory controller configured to: send a first request for first temperature information to a first memory die of a first memory die group via a first channel and using a first identifier and a second request for second information to a second memory die of a second memory group via the first channel and using a second identifier; receive the first temperature information corresponding to a first temperature of the first memory die from a first temperature sensor associated with the first memory die via the first channel and using the first identifier; receive the second temperature information corresponding to a second temperature of the second memory die from a second temperature sensor associated with the second memory die via the first channel and using the second identifier (Figure 9, refresh controller 916, Paragraph [0073] and [0076] and Figure 1A and [0026]); output a first refresh signal to the first memory die based on a first refresh rate for the first memory die, wherein the first refresh rate is based on the first temperature information; and output a second refresh signal to the second memory die based on a second refresh rate for the second memory die, wherein the second refresh rate is based on the second temperature information, and wherein the second refresh rate differs from the first refresh rate ([0076]). Herein Keeth teaches the plurality of memory dies in communication with a memory controller which controls the refresh operations performed by the memory device based on monitored temperature metrics of respective memory dies or portions thereof. Keeth does not explicitly disclose the elements of the first and second temperature sensors associated with the first and second memory dies which send the respective temperature information to the memory controller or using respective first and second identifiers to request from the memory dies. Regarding the respective temperature sensors, Palmer discloses in Paragraph [0062] that each NAND die may include a respective temperature sensor for transmitting temperature data. As additionally discussed in Paragraph [0066], the memory system uses the temperature data to perform mitigation procedures for the data to improve data retention accuracy which would involve performing refresh operations. Regarding the use of respective first and second identifiers to request first and second memory dies associated with the first channel, Webb discloses in Paragraphs [0026-27] accessing specific memory dies along particular channels using identifiers which uniquely identify the target NVM die. Claim 9 is rejected on a similar basis as claim 1.
Regarding claim 10, Keeth and Webb in combination further disclose the memory controller of claim 9, wherein the memory controller is coupled to a third memory die via a second channel (Keeth Figure 1A, stack of DRAM dies 122), wherein the third memory die is associated with the first identifier (Keeth [0073] and Webb [0026-27]). Claim 10 is rejected on a similar basis as claim 2.
Regarding claim 11, Keeth and Palmer further disclose the memory controller of claim 10 further configured to receive third temperature information corresponding to a third temperature of the third memory die, and wherein the first refresh rate is further based on the third temperature information, and wherein the first refresh rate is further for the third memory die (Keeth [0076], BIST logic 318 using a performance metric of a portion of memory to control the refresh rate). Herein Keeth notes use of performance metrics to adjust the refresh rate of the associated memory which includes basing it on temperature. Additionally, Paragraphs [0102] and [0110] identify ranks of memory comprising a plurality of portions of a plurality of memory die. In this case, the refresh rate applied to one rank of memory is subject to the temperature information of each portion which form the rank and the refresh rate is applied to all portions. Palmer in Paragraphs [0089-90] additionally supports memory die specific operations being applied based on temperature.
Regarding claim 12, Keeth further discloses the memory controller of claim 11 further configured to: output the first refresh signal to the third memory die ([0073] and [0076]). Herein Keeth discloses the refresh controller coordinating refresh operations for ranks of memory based on a refresh rate respective to each portion which involves communicating to the memory portions along the channels. In this case, when the first and third memory die operating temperature reading contribute to the refresh rate determination, both dies may be subjected to the same refresh rate determination while the second die operating temperature results in a respective refresh rate being applied.
Regarding claim 13, Keeth and Palmer further disclose the memory controller of claim 10 further configured to: receive third temperature information from the third memory die; and determine a third refresh rate for the third memory die based on the third temperature information (Keeth [0073] and [0076]). Herein Keeth discloses refresh rates for a memory die may be determined based on a respective performance metric of the memory die including temperature. In this case, the formation may comprise each memory die as subjected to a respective refresh rate based on the monitored operation temperature. Palmer in Paragraphs [0089-90] additionally supports memory die specific operations being applied based on temperature.
Regarding claim 14, Keeth and Palmer further disclose the memory controller of claim 13 further configured to: output a third refresh signal to the third memory die based on the third refresh rate (Keeth [0073] and [0076]). Herein Keeth discloses refresh rates for a memory die may be determined based on a respective performance metric of the memory die including temperature. In this case, each memory die may be subject to a respective refresh rate based on the monitored operation temperature. As noted in the rejection of claim 13, Palmer supports memory die specific operations.
Regarding claim 15, Keeth further discloses the memory controller of claim 9, wherein the first temperature of the first memory die is greater than the second temperature of the second memory die, and wherein the first refresh rate is greater than the second refresh rate ([0076]). Claim 15 is rejected on a similar basis as claim 7.
Regarding claim 16, Keeth further discloses the memory controller of claim 9, wherein the first memory die and the second memory die are vertically stacked on each other (Figure 8A, DRAM dies 810 stacked vertically). Claim 16 is rejected on a similar basis as claim 8.
Regarding claim 17, Keeth teaches a method comprising: sending, from a memory controller, a first request for first temperature information to a first memory die of a first memory die group via a first channel and using a first identifier and a second request for second information to a second memory die of a second memory group via the first channel and using a second identifier; receiving, at the memory controller, the first temperature information corresponding to a first temperature of the first memory die from a first temperature sensor associated with the first memory die via the first channel and using the first identifier; receiving, at the memory controller, the second temperature information corresponding to a second temperature of the second memory die from a second temperature sensor associated with the second memory die via the first channel and using the second identifier (Figure 9, refresh controller 916, Paragraph [0073] and [0076] and Figure 1A and [0026]); outputting, from the memory controller. a first refresh signal to the first memory die based on a first refresh rate for the first memory die, wherein the first refresh rate is based on the first temperature information; and outputting, from the memory controller, a second refresh signal to the second memory die based on a second refresh rate for the second memory die, wherein the second refresh rate is based on the second temperature information, wherein the second refresh rate differs from the first refresh rate ([0076]). Herein Keeth teaches the plurality of memory dies in communication with a memory controller which controls the refresh operations performed by the memory device based on monitored temperature metrics of respective memory dies or portions thereof. Keeth does not explicitly disclose the elements of the first and second temperature sensors associated with the first and second memory dies which send the respective temperature information to the memory controller or using respective first and second identifiers to request from the memory dies. Regarding the respective temperature sensors, Palmer discloses in Paragraph [0062] that each NAND die may include a respective temperature sensor for transmitting temperature data. As additionally discussed in Paragraph [0066], the memory system uses the temperature data to perform mitigation procedures for the data to improve data retention accuracy which would involve performing refresh operations. Regarding the use of respective first and second identifiers to request first and second memory dies associated with the first channel, Webb discloses in Paragraphs [0026-27] accessing specific memory dies along particular channels using identifiers which uniquely identify the target NVM die. Claim 17 is rejected on a similar basis as claim 1.
Regarding claim 18, Keeth and Palmer further disclose the method of claim 17 further comprising receiving third temperature information corresponding to a temperature of a third memory die, and wherein the first refresh rate is further determined based on the third temperature information, and wherein the first refresh rate is further for the third memory die (Keeth [0076], BIST logic 318 using a performance metric of a portion of memory to control the refresh rate). Claim 18 is rejected on a similar basis as claim 11.
Regarding claim 19, Keeth further discloses the method of claim 17 further comprising: outputting the first refresh signal to a third memory die ([0073] and [0076]). Claim 19 is rejected on a similar basis as claim 12.
Regarding claim 20, Keeth and Palmer further disclose the method of claim 17 further comprising: receiving third temperature information from a third memory die; and outputting a third refresh signal to the third memory die based on a third refresh rate for the third memory die, wherein the third refresh rate is based on the third temperature information (Keeth [0073] and [0076]). Claim 20 is rejected on a similar basis as claims 13 and 14.
Regarding claim 22, Keeth and Webb in combination further disclose the memory system of claim 1, wherein the request for the first temperature information and the second temperature information is sent via a first bitstream comprising bits associated with the first identifier, the second identifier, and the first channel, and the first temperature information and the second temperature information are sent via bits of a second bitstream (Webb [0043-47]). Herein Webb further discloses stream interfaces for communicating between controllers and the NVM device including the associated memory dies. In order to designate a particular memory target, Webb uses identifiers for each particular NVM die subject to an access operation and therefore the command and corresponding information is transferred along the appropriate stream which connects the controller to the devices. As noted in Paragraph [0016] the terms of upstream and downstream refer to the direction of communication with respect to the controller which the Examiner determines as analogous to the first and second bitstreams for communicating the requests to the NVM dies and for receiving responses of the temperature information from the NVM dies.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDER J YOON whose telephone number is (408)918-7629. The examiner can normally be reached on Monday-Friday 8am-3pm ET. The examiner’s email is alexander.yoon2@uspto.gov.
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/ALEXANDER YOON/
Examiner, Art Unit 2135
/JARED I RUTZ/Supervisory Patent Examiner, Art Unit 2135