Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is in response to the amendment filed on 06/09/2026.
Claims 1-4, 6-11, 13-18 and 20 amended by the applicants.
Claims 1-20 are pending.
Examiner’s Note
Please note that Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirely as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Claim Rejections – 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter.
Claim 1, this claim is within at least one of the four categories of patent eligible subject matter as it is directing to a system claim under Step 1.
1. A system, comprising:
a processor, the processor comprising:
a first computer-readable memory; and
a second computer-readable memory,
the processor being configured to:
receive an instruction comprising a first portion and a second portion, wherein the first portion comprises a breakpoint bit;
store the first portion in the first computer-readable memory;
store the second portion in the second computer-readable memory;
determine that the breakpoint bit is set, and
based on determining that the breakpoint bit is set, report an error.
Regarding claim 1, the limitations “determine that the breakpoint bit is set, and based on determining that the breakpoint bit is set” as drafted, are functions that, under its broadest reasonable interpretation, recite the abstract idea of a mental process. For example, a person is capable of determine if a breakpoint bit is set to find out the program’s logic and behavior with the aid of pen and paper to identify any errors may occur during the run of the program. Therefore, these limitations encompass a human mind carrying out the function through observation, evaluation judgment and /or opinion, or even with the aid of pen and paper. Thus, these limitations recite and falls within the “Mental Processes” grouping of abstract ideas under Prong 1.
Under Prong 2, the additional elements “A system,” “a processor,” “a first computer-readable memory; and a second computer-readable memory, the processor being configured to,” “the first computer-readable memory,” “second computer-readable memory” is recited at a high-level of generality such that it amounts no more than mere instructions to store and executing/applying program instructions which merely using generic computing equipment to execute software tools to perform the abstract idea. See MPEP 2106.05(f). For the additional elements “receive an instruction comprising a first portion and a second portion, wherein the first portion comprises a breakpoint bit,” “store the first portion,” “store the second portion” do nothing more than to add insignificant extra solution activity to the judicial exception of merely gathering/receiving/storing/reporting data for further analysis. See MPEP § 2106.05(h).
Under Step 2B, the claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “A system,” “a processor,” “a first computer-readable memory; and a second computer-readable memory, the processor being configured to,” “the first computer-readable memory,” “second computer-readable memory” amount to no more than mere instructions, or generic computer and/or computer components to carry out the exception, thus, cannot amount to an inventive concept. See MPEP 2105.06(f). For the additional elements “receive an instruction comprising a first portion and a second portion, wherein the first portion comprises a breakpoint bit,” “store the first portion,” “store the second portion” the courts have recognized storing and reporting information in memory as a well‐understood, routine, and conventional functions in a merely generic manner (e.g., at a high level of generality) or an insignificant extra-solution activity. See MPEP 2106.05(d). Accordingly, the claims are not patent eligible under 35 USC 101.
2. The system of claim 1, wherein the first computer-readable memory comprises a first portion of a level one cache, and the second computer-readable memory comprises a second portion of the level one cache.
The limitation for this claim amounts to no more than mere instructions to apply the exception using generic computer and/or mere computer components to carry out the exception under prong 2.
3. The system of claim 1, wherein the processor comprises a first memory management unit configured to: perform the converting of the virtual address of the instruction and the loading of the instruction, and wherein the second portion comprises an opcode and an operand of the instruction.
The limitations for this claim further recite an additional insignificant extra solution activity under prong 2.
The limitations “the processor comprises a first memory management unit configured to” amount to no more than mere instructions to apply the exception using generic computer and/or mere computer components to carry out the exception under prong 2.
4. The system of claim 1, wherein the processor comprises a second memory management unit configured to: convert a virtual address of the breakpoint bit to a second physical address; and load the breakpoint bit from the second physical address into the second computer-readable memory.
The limitations for this claim further recite an additional insignificant extra solution activity under prong 2.
The limitations “the processor comprises a second memory management unit configured to” and “into the second computer-readable memory” amount to no more than mere instructions to apply the exception using generic computer and/or mere computer components to carry out the exception under prong 2.
5. The system of claim 1, wherein: the processor comprises a second memory management unit configured to convert a virtual address of the breakpoint bit to a second physical address;
the processor comprises an address conversion cache for breakpoint bits; and the converting of the virtual address of the breakpoint bit to the second physical address comprises converting the virtual address of the breakpoint bit to the second physical address based on data stored in the address conversion cache for breakpoint bits.
The limitations “convert a virtual address of the breakpoint bit to a second physical address” and “an address conversion cache for breakpoint bits; and the converting of the virtual address of the breakpoint bit to the second physical address comprises converting the virtual address of the breakpoint bit to the second physical address based on data stored in the address conversion cache for breakpoint bits” for this claim further recite an additional insignificant extra solution activity under prong 2.
The limitations “the processor comprises a second memory management unit configured to” and “the processor comprises” amount to no more than mere instructions to apply the exception using generic computer and/or mere computer components to carry out the exception under prong 2.
6. The system of claim 1, wherein: the processor comprises a second memory management unit configured to convert a virtual address of the breakpoint bit to a second physical address; and the processor is further configured to: determine that debug mode is enabled; and based on determining that debug mode is enabled, load the breakpoint bit from the second physical address into the second computer-readable memory.
The limitation “convert a virtual address of the breakpoint bit to a second physical address” “from the second physical address” for this claim further recite an additional insignificant extra solution activity under prong 2.
The limitation “the processor comprises a second memory management unit configured to” “the processor is further configured to” “into the second computer-readable memory” amount to no more than mere instructions to apply the exception using generic computer and/or mere computer components to carry out the exception under prong 2.
The limitation “determine that debug mode is enabled; and based on determining that debug mode is enabled, load the breakpoint bit” for this claim further recite an additional mental process under prong 1.
7. The system of claim 1, wherein: the processor comprises a second memory management unit configured to convert a virtual address of the breakpoint bit to a second physical address; and the processor is further configured to: determine, based on a debug control register of the processor, that debug mode is enabled; and based on determining that debug mode is enabled, load the breakpoint bit from the second physical address into the second computer-readable memory.
The limitation “convert a virtual address of the breakpoint bit to a second physical address” “from the second physical address into the second computer-readable memory” for this claim further recite an additional insignificant extra solution activity under prong 2.
The limitation “the processor comprises a second memory management unit configured to” “the processor is further configured to” amount to no more than mere instructions to apply the exception using generic computer and/or mere computer components to carry out the exception under prong 2.
The limitation “determine, based on a debug control register…, that debug mode is enabled; and based on determining that debug mode is enabled, load the breakpoint bit” for this claim further recite an additional mental process under prong 1.
Claim 8, this claim is within at least one of the four categories of patent eligible subject matter as it is directing to a method claim under Step 1.
8. A method, comprising:
receiving an instruction comprising a first portion and a second portion, wherein the first portion comprises a breakpoint bit,
storing first portion in a first computer-readable memory of a processor;
storing the second portion in a second computer-readable memory of the processor;
determining, by the processor, that the breakpoint bit is set; and
in response to determining that the breakpoint bit is set, reporting an error.
Regarding claim 8, the limitations “determine that the breakpoint bit is set, and in response to determining that the breakpoint bit is set” as drafted, are functions that, under its broadest reasonable interpretation, recite the abstract idea of a mental process. For example, a person is capable of determine if a breakpoint bit is set to find out the program’s logic and behavior with the aid of pen and paper to identify any errors may occur during the run of the program. Therefore, these limitations encompass a human mind carrying out the function through observation, evaluation judgment and /or opinion, or even with the aid of pen and paper. Thus, these limitations recite and falls within the “Mental Processes” grouping of abstract ideas under Prong 1.
Under Prong 2, the additional elements “a first computer-readable memory of a processor,” “a second computer-readable memory of the processor” and “by the processor” are recited at a high-level of generality such that it amounts no more than mere instructions to store and executing/applying program instructions which merely using generic computing equipment to execute software tools to perform the abstract idea. See MPEP 2106.05(f). For the additional elements “receiving an instruction comprising a first portion and a second portion, wherein the first portion comprises a breakpoint bit,” “storing first portion,” “storing the second portion” and “reporting an error” do nothing more than to add insignificant extra solution activity to the judicial exception of merely gathering/ receiving/ storing / reporting data for further analysis. See MPEP § 2106.05(h).
Under Step 2B, the claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “a first computer-readable memory of a processor,” “a second computer-readable memory of the processor” and “by the processor” amount to no more than mere instructions, or generic computer and/or computer components to carry out the exception, thus, cannot amount to an inventive concept. See MPEP 2105.06(f). For the additional elements “receiving an instruction comprising a first portion and a second portion, wherein the first portion comprises a breakpoint bit,” “storing first portion,” “storing the second portion” and “reporting an error” the courts have recognized storing and reporting information in memory as a well‐understood, routine, and conventional functions in a merely generic manner (e.g., at a high level of generality) or an insignificant extra-solution activity. See MPEP 2106.05(d). Accordingly, the claims are not patent eligible under 35 USC 101.
9. The method of claim 8, wherein the first computer- readable memory is a first portion of a level one cache, and the second computer- readable memory is a second portion of the level one cache.
The limitation for this claim amounts to no more than mere instructions to apply the exception using generic computer and/or mere computer components to carry out the exception under prong 2.
10. The method of claim 8, wherein the processor comprises a first memory management unit configured to perform the converting of the virtual address of the instruction and the loading of the instruction, and wherein the second portion comprises an opcode and an operand of the instruction.
The limitation “the processor comprises a first memory management unit” for this claim amounts to no more than mere instructions to apply the exception using generic computer and/or mere computer components to carry out the exception under prong 2.
The limitations “converting of the virtual address of the instruction and the loading of the instruction, and wherein the second portion comprises an opcode and an operand of the instruction” for this claim further recite an additional insignificant extra solution activity under prong 2.
11. The method of claim 8, wherein the processor comprises a second memory management unit, and the method further comprises: converting, by the second memory management unit, a virtual address of the breakpoint bit to a second physical address; and loading, by the second memory management unit, the breakpoint bit from the second physical address into the second computer-readable memory.
The limitation “the processor comprises a second memory management unit” “by the second memory management unit,” “into the second computer-readable memory” for this claim amounts to no more than mere instructions to apply the exception using generic computer and/or mere computer components to carry out the exception under prong 2.
The limitations “converting… a virtual address of the breakpoint bit to a second physical address; and loading… the breakpoint bit from the second physical address” for this claim further recite an additional insignificant extra solution activity under prong 2.
12. The method of claim 8, wherein: the processor comprises a second memory management unit; the method further comprises converting, by the second memory management unit, a virtual address of the breakpoint bit to a second physical address; the processor comprises an address conversion cache for breakpoint bits; and the converting of the virtual address of the breakpoint bit to the second physical address comprises converting the virtual address of the breakpoint bit to the second physical address based on data stored in the address conversion cache for breakpoint bits.
The limitations “the method further comprises converting… virtual address of the breakpoint bit to a second physical address; an address conversion cache for breakpoint bits; and the converting of the virtual address of the breakpoint bit to the second physical address comprises converting the virtual address of the breakpoint bit to the second physical address based on data stored in the address conversion cache for breakpoint bits” for this claim further recite an additional insignificant extra solution activity under prong 2.
The limitations “the processor comprises a second memory management unit…” and “the processor comprises” amount to no more than mere instructions to apply the exception using generic computer and/or mere computer components to carry out the exception under prong 2.
13. The method of claim 8, wherein: the processor comprises a second memory management unit; and the method further comprises: converting, by the second memory management unit, a virtual address of the breakpoint bit to a second physical address; determining, by the processor, that debug mode is enabled; and based on determining that debug mode is enabled, loading the breakpoint bit from the second physical address into the second computer-readable memory.
The limitation “convert a virtual address of the breakpoint bit to a second physical address” “from the second physical address into the second computer-readable memory” for this claim further recite an additional insignificant extra solution activity under prong 2.
The limitation “the processor comprises a second memory management unit” “by the second memory management unit” “by the processor” amount to no more than mere instructions to apply the exception using generic computer and/or mere computer components to carry out the exception under prong 2.
The limitation “determining that that debug mode is enabled; and based on determining that debug mode is enabled, loading the breakpoint bit from the second physical address” for this claim further recite an additional mental process under prong 1.
14. The method of claim 8, wherein: the processor comprises a second memory management unit; and the method further comprises: converting, by the second memory management unit, a virtual address of the breakpoint bit to a second physical address; determining, by the processor, based on a debug control register of the processor, that debug mode is enabled; and based on determining that debug mode is enabled, loading the breakpoint bit from the second physical address into the second computer-readable memory.
The limitation “convert a virtual address of the breakpoint bit to a second physical address” “from the second physical address into the second computer-readable memory” for this claim further recite an additional insignificant extra solution activity under prong 2.
The limitation “the processor comprises a second memory management unit” “by the second memory management unit” “by the processor” “into the second memory” amount to no more than mere instructions to apply the exception using generic computer and/or mere computer components to carry out the exception under prong 2.
The limitation “determining, …, based on a debug control register of the processor, that debug mode is enabled; and based on determining that debug mode is enabled, loading the breakpoint bit from the second physical address” for this claim further recite an additional mental process under prong 1.
Claim 15, this claim is within at least one of the four categories of patent eligible subject matter as it is directing to a system claim under Step 1.
15. A system, comprising:
a processing circuit; and
a first computer-readable memory and a second computer-readable memory,
the processing circuit is configured to:
receive an instruction comprising a first portion and a second portion, wherein the first portion comprises a breakpoint bit store the first portion in the first computer-readable memory;
store the second portion in the second computer-readable memory;
determine that the breakpoint bit is set and
in response to determining that the breakpoint bit is set, to report an error.
Regarding claim 15, the limitations “determine that the breakpoint bit is set, and in response to determining that the breakpoint bit is set” as drafted, are functions that, under its broadest reasonable interpretation, recite the abstract idea of a mental process. For example, a person is capable of determine if a breakpoint bit is set to find out the program’s logic and behavior with the aid of pen and paper to identify any errors may occur during the run of the program. Therefore, these limitations encompass a human mind carrying out the function through observation, evaluation judgment and /or opinion, or even with the aid of pen and paper. Thus, these limitations recite and falls within the “Mental Processes” grouping of abstract ideas under Prong 1.
Under Prong 2, the additional elements “A system, comprising: a processing circuit; and a first computer-readable memory and a second computer-readable memory” and “the processing circuit is configured to” are recited at a high-level of generality such that it amounts no more than mere instructions to store and executing/applying program instructions which merely using generic computing equipment to execute software tools to perform the abstract idea. See MPEP 2106.05(f). For the additional elements “receive an instruction comprising a first portion and a second portion, wherein the first portion comprises a breakpoint bit store the first portion” “store the second portion” “to report an error” do nothing more than to add insignificant extra solution activity to the judicial exception of merely gathering/receiving storing/reporting data for further analysis. See MPEP § 2106.05(h).
Under Step 2B, the claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “A system, comprising: a processing circuit; and a first computer-readable memory and a second computer-readable memory” and “the processing circuit is configured to” amount to no more than mere instructions, or generic computer and/or computer components to carry out the exception, thus, cannot amount to an inventive concept. See MPEP 2105.06(f). For the additional elements “receive an instruction comprising a first portion and a second portion, wherein the first portion comprises a breakpoint bit store the first portion” “store the second portion” “to report an error” the courts have recognized storing and reporting information in memory as a well‐understood, routine, and conventional functions in a merely generic manner (e.g., at a high level of generality) or an insignificant extra-solution activity. See MPEP 2106.05(d). Accordingly, the claims are not patent eligible under 35 USC 101.
16. The system of claim 15, wherein the first computer- readable memory is a first portion of a level one cache, and the second computer- readable memory is a second portion of the level on cache.
The limitation for this claim amounts to no more than mere instructions to apply the exception using generic computer and/or mere computer components to carry out the exception under prong 2.
17. The system of claim 15, wherein the processing circuit comprises a first memory management unit configured to perform the converting of the virtual address of the instruction and the loading of the instruction, and wherein the second portion comprises an opcode and an operand of the instruction.
The limitations “converting of the virtual address of the instruction and the loading of the instruction, and wherein the second portion comprises an opcode and an operand of the instruction” for this claim further recite an additional insignificant extra solution activity under prong 2.
The limitations “wherein the processing circuit comprises a first memory management unit” amount to no more than mere instructions to apply the exception using generic computer and/or mere computer components to carry out the exception under prong 2.
18. The system of claim 15, wherein the processing circuit comprises a second memory management unit configured to: convert a virtual address of the breakpoint bit to a second physical address; and load the breakpoint bit from the second physical address into the second computer-readable memory.
The limitations “convert a virtual address of the breakpoint bit to a second physical address; and load the breakpoint bit from the second physical address” for this claim further recite an additional insignificant extra solution activity under prong 2.
The limitations “the processing circuit comprises a second memory management unit” and “into the second computer-readable memory” amount to no more than mere instructions to apply the exception using generic computer and/or mere computer components to carry out the exception under prong 2.
19. The system of claim 15, wherein: the processing circuit comprises a second memory management unit configured to convert a virtual address of the breakpoint bit to a second physical address; the processing circuit comprises an address conversion cache for breakpoint bits; and the converting of the virtual address of the breakpoint bit to the second physical address comprises converting the virtual address of the breakpoint bit to the second physical address based on data stored in the address conversion cache for breakpoint bits.
The limitations “conversion cache for breakpoint bits; and the converting of the virtual address of the breakpoint bit to the second physical address comprises converting the virtual address of the breakpoint bit to the second physical address based on data stored in the address conversion cache for breakpoint bits” for this claim further recite an additional insignificant extra solution activity under prong 2.
The limitations “convert a virtual address of the breakpoint bit to a second physical address” “the processing circuit comprises a second memory management unit” and “the processing circuit comprises an address” amount to no more than mere instructions to apply the exception using generic computer and/or mere computer components to carry out the exception under prong 2.
20. The system of claim 15, wherein: the processing circuit comprises a second memory management unit configured to convert a virtual address of the breakpoint bit to a second physical address; and the processing circuit is further configured to: determine that debug mode is enabled; and based on determining that debug mode is enabled, load the breakpoint bit from the second physical address into the second computer-readable memory.
The limitation “convert a virtual address of the breakpoint bit to a second physical address” for this claim further recite an additional insignificant extra solution activity under prong 2.
The limitation “the processing circuit comprises a second memory management unit” “the processing circuit is further configured to” “into the second computer-readable memory” amount to no more than mere instructions to apply the exception using generic computer and/or mere computer components to carry out the exception under prong 2.
The limitation “determine that debug mode is enabled; and based on determining that debug mode is enabled, load the breakpoint bit from the second physical address” for this claim further recite an additional mental process under prong 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, 8-11 and 15-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over USPN 20110047314 to Pogor et al. in view of USPN 6052801 to Hammond et al.
Per claim 1:
Pogor discloses:
1. A system, comprising:
a processor (Paragraph [0008] “a microprocessor”), the processor comprising:
a first computer-readable memory (Paragraph [0008] “first storage for storing”); and
a second computer-readable memory (Paragraph [0008] “second storage for storing”),
the processor being configured to (Paragraph [0008] “a microprocessor configured to perform a breakpoint check”):
receive an instruction comprising a first portion and a second portion (Paragraph [0024] “receives a load instruction and computes a load virtual address 234 from the address operands received along with the load instruction”),
wherein the first portion comprises a breakpoint bit (Paragraph [0009] “performing a first piece breakpoint check associated with the first piece of data”);
store the first portion in the first computer-readable memory (Paragraph [0009] “a first piece of the data (i.e., instructions) being within a first cache line”);
store the second portion in the second computer-readable memory(Paragraph [0009] “a second piece of the data (i.e., instructions) being within a second cache line”);
determine that the breakpoint bit is set (Paragraph [0008] “microprocessor configured to perform a breakpoint check on a cache line-crossing load/store operation”).
Pogor does not explicitly disclose based on determining that the breakpoint bit is set, report an error.
However, Hammond discloses in an analogous computer system based on determining that the breakpoint bit is set, report an error (Col. 5, lines 57-58 “output node 260 to report the address received at node 210 is inside the breakpoint address range”; Col. 6-7, line 66 to line 2 “breakpoints are detected and reported prior to instruction execution (commonly referred to as "faults")”).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention was made to incorporate the method of based on determining that the breakpoint bit is set, report an error as taught by Hammond into the method of detecting errors as taught by Pogor. The modification would be obvious because of one of ordinary skill in the art would be motivated to add/incorporate the features of based on determining that the breakpoint bit is set, report an error to provide an efficient technique for detecting and reporting errors so as to avoid any future unexcepted events as suggested by Hammond (col. 2, lines 13-27).
Per claim 2:
Pogor discloses:
2. The system of claim 1, wherein the first computer-readable memory comprises a first portion of a level one cache, and the second computer-readable memory comprises a second portion of the level one cache (Paragraph [0012] “a first cache line and a second piece of the data is within a second cache line”).
Per claim 3:
Pogor discloses:
3. The system of claim 1, wherein the processor comprises a first memory management unit configured to perform the converting of the virtual address of the instruction and the loading of the instruction, (Paragraph [0009] “the first storage with a load/store physical address translated (i.e., converted) from the load/store virtual address”) and wherein the second portion (Paragraph [0014] “a load operation and second storage for storing an indicator”) comprises an opcode and an operand of the instruction (Paragraph [0024] “a load instruction and computes a load virtual address 234 from the address operands received along with the load instruction”).
Per claim 4:
Pogor discloses:
4. The system of claim 1, wherein the processor comprises a second memory management unit configured to:
convert a virtual address of the breakpoint bit to a second physical address (Paragraph [0021] “translation functions between virtual addresses and physical addresses… implementing data breakpoints 16”); and
load the breakpoint bit from the second physical address into the second computer-readable memory (Paragraph [0021] “cache memory is accessed and the breakpoint check is performed for the load/store operation in no more than two passes through the load/store unit pipeline”).
Per claim 5:
Pogor discloses:
5. The system of claim 1, wherein:
the processor comprises a second memory management unit configured to convert a virtual address of the breakpoint bit to a second physical address (Paragraph [0022] “when the load pipeline processes the first piece (i.e., performs the breakpoint check on the first piece virtual address, generates the physical address, accesses the cache, and replaces the virtual address in the load queue entry address field with the physical address)”);
the processor comprises an address conversion cache for breakpoint bits (Paragraph [0022] “saves in the load queue entry a hit_page indication of whether the virtual page bits of the first piece (i.e., the bits of the virtual address that must be translated to obtain the physical page)”); and
the converting of the virtual address of the breakpoint bit to the second physical address comprises converting the virtual address of the breakpoint bit to the second physical address based on data stored in the address conversion cache for breakpoint bits (Paragraph [0022] “a virtual memory system, the virtual page address bits are the bits that must be translated from a virtual memory page address to a physical memory page address”).
Claims 8-11 is/are the method claim corresponding to apparatus/system claims 1-12 respectively and rejected under the same rational set forth in connection with the rejection of claims 1-12 respectively, as noted above.
Claims 15-19 is/are the apparatus/system claim corresponding to method claims 1-5 respectively and rejected under the same rational set forth in connection with the rejection of claims 1-5 respectively, as noted above.
Allowable Subject Matter
Claims 6-7, 13-14 and 20 objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Please note that applicants must overcome the 101 rejections above in order for these claims to be allowed.
Response to Arguments
Applicant's arguments filed 06/09/2026 have been fully considered but they are not persuasive.
In response to applicants’ arguments that Pogor merely discloses that the first storage is for storing an address associated with an operation and the second storage is for storing an indicator indicating whether there is a match between an address of the operation and an address of the breakpoint. As discussed and agreed during the interview of May 20, 2026, Pogor fails to disclose "receive an instruction comprising a first portion and a second portion, wherein the first portion comprises a breakpoint bit," "store the first portion in the first computer-readable memory," and "store the second portion in the second computer- readable memory," as recited in the amended claim 1.
Examiner respectfully disagrees. First of all, there was no agreement reached during the interview. Second, Pogor teaches the amended limitations as argued above, see the rejection above. Pogor discloses receives a load instruction and computes a load virtual address 234 from the address operands received along with the load instruction, where a first piece breakpoint check associated with the first piece of data then a first piece of the data (i.e., instructions) being within a first cache line and a second piece of the data (i.e., instructions) being within a second cache line, see paragraph [0009 and 0024]. Pogor clearly teaches first and second memories along with first and second portions of instructions which defines breakpoint bit (i.e., check).
Applicants have not provided any arguments related to reference Hammond therefore not response is given at this time.
In response to applicants’ argument with respect to rejection under 101 that according to Example 47 published in "July 2024 Subject Matter Eligibility Examples," claim 3 of Example 47 is eligible (Step 2A, Prong Two: YES), because claim 3 "recites the additional elements of (d) detecting a source address associated with the one or more malicious network packets, (e) dropping the one or more malicious network packets, and (f) blocking future traffic from the source address." The example states that "[t]he additional elements in steps (d)-(f), when considered in combination, integrate the abstract idea into a practical application because the claim improves the functioning of a computer or technical field. See MPEP 2106.04(d)(1) and 2106.05(a)." Similarly, claim 1 of the present application recites a method for identifying errors in code and loading instructions efficiently and without a restriction on the number of debug registers for debugging, which includes "receive an instruction comprising a first portion and a second portion, wherein the first portion comprises a breakpoint bit," "store the first portion in the first computer-readable memory," "store the second portion in the second computer-readable memory," "determine that the breakpoint bit is set," and "based on determining that the breakpoint bit is set, report an error." The additional elements, including storing the breakpoint bit, as a different portion of the instruction, in a different computer-readable memory from the other portion of the instruction, may render no limitation on the number of debug registers for the debug operation and be able to load the instruction to the computer-readable memory when executing.
Examiner respectfully disagrees. It may be true that the invention is directed towards identifying errors in code and loading instructions efficiently and without a restriction on the number of debug registers for debugging. However, none of the independent claims recite these features, it is noted that the features upon which applicant relies (i.e., loading instructions efficiently and without a restriction on the number of debug registers for debugging) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Further, the amended feature of claims receive… store… store… do nothing more than to add insignificant extra solution activity to the judicial exception of merely gathering/storing/reporting data for further analysis. See MPEP § 2106.05(h).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Satish Rampuria whose telephone number is 571-272-3732. The examiner can normally be reached on Monday-Friday from 8:30 AM to 5:00 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chat Do, can be reached at telephone number 571-272-3721. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Satish Rampuria/Primary Examiner, Art Unit 2193
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