DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Ding et al. (US Pat Pub# 2015/0256216) in view of Alon et al. (US Pat Pub# 2015/0333781).
Regarding claim 1, Ding teaches a transmitting device comprising a digital predistorter circuit 405 (Fig. 4) configured to pre-compensate an input baseband signal in one of a plurality of digital predistortion modes according to a selection signal (Abstract, Fig.4, and Sections 0004-0006 and 0021-0025, digital predistorter baseband circuit to compensate the input signal of a plurality of harmonic frequencies and switch modes etc.); a power amplifier 420 (Fig. 4) configured to amplify the pre-compensated baseband signal and output the amplified baseband signal as an output signal of an allocated band (Abstract, Fig.4, and Sections 0004-0006 and 0021-0025, amplifying the pre-compensate signal outputting the baseband signal etc.); and a digital predistortion mode selector circuit configured to determine the one of the plurality of digital predistortion modes corresponding to the allocated band using a feedback signal obtained from the output signal, and set the digital predistorter circuit to the one of the determined modes (Abstract, Fig.4, and Sections 0004-0006 and 0021-0025, digital predistorter baseband circuit to compensate the input signal of a plurality of harmonic frequencies and switch modes etc.). Ding fails to specifically teach a multi-mode digital predistorter circuit.
Alon teaches a transmitting device comprising a multi-mode digital predistorter circuit (Section 0006, multiple modes of a digital predistorter circuit).
Therefore, it would have been obvious at the time of the invention to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate a multi-mode digital predistorter circuit as taught by Alon into Ding’s device in order to improve efficiency and performance.
Regarding claim 9, the combination including Ding teaches wherein the digital predistortion mode selector circuit comprises a performance evaluation circuit configured to evaluate performance of the multi-mode digital predistorter circuit by analyzing the feedback signal; and an algorithm selector configured to determine the one of the plurality of digital predistortion modes according to the performance evaluation result and set an operation mode of the multi-mode digital predistorter circuit to the one of the plurality of digital predistortion modes (Abstract, Fig.4, and Sections 0004-0006 and 0021-0025, digital predistorter baseband circuit to compensate the input signal of a plurality of harmonic frequencies and switch modes etc.).
Regarding claim 10, the combination including Ding teaches wherein the digital predistortion mode selector circuit determines the operation mode while varying the bias setting or a frequency band of the power amplifier (Abstract, Fig.4, and Sections 0004-0006 and 0021-0025, operation mode while varying the frequencies etc.).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Ding et al. (US Pat Pub# 2015/0256216) in view of Alon et al. (US Pat Pub# 2015/0333781) and further in view of Sanchez et al. (US Pat Pub# 2022/0200618).
Regarding claim 2, Ding in view of Alon teaches the limitations in claim 1. Ding and Alon fail to teach a memoryless polynomial mode, a memory polynomial mode, and a dynamic deviation reduction mode.
Sanchez teaches wherein the plurality of digital predistortion modes include a memoryless polynomial mode (Section 0022, memoryless polynomial), a memory polynomial mode (Sections 0022, 0025, and 0032, memory polynomial mode), and a dynamic deviation reduction mode (Section 0032, dynamic deviation reduction).
Allowable Subject Matter
Claims 3-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance: Regarding claim 11, the prior art of record, Ding (US 2015/0256216) teaches a predistortion method of a digital predistorter to compensate for nonlinearity of a power amplifier evaluating the performance of the digital predistorter in each of a plurality of digital predistortion modes (Abstract, Fig.4, and Sections 0004-0006 and 0021-0025); selecting one of the plurality of digital predistortion modes based on the evaluated performance (Abstract, Fig.4, and Sections 0004-0006 and 0021-0025); and setting the digital predistorter to any one of the selected modes (Abstract, Fig.4, and Sections 0004-0006 and 0021-0025).
Sanchez (US 2022/0200618) teaches a memoryless polynomial mode and a memory polynomial mode (Sections 0022, 0025, and 0032); a dynamic deviation reduction mode (Sections 0022, 0025, and 0032).
The prior art of record fails to teach a predistortion method of a digital predistorter to compensate for nonlinearity of a power amplifier evaluating the performance of the digital predistorter in each of a plurality of digital predistortion modes; selecting one of the plurality of digital predistortion modes based on the evaluated performance; and setting the digital predistorter to any one of the selected modes, wherein the digital predistorter comprises first kernel processing circuitry configured to process an input baseband signal in one of a memoryless polynomial mode and a memory polynomial mode in response to a first enable signal; second kernel processing circuitry configured to perform an operation of a dynamic deviation reduction mode on the input baseband signal in response to a second enable signal; and an adder configured to add a first term signal output from the first kernel processing circuitry and a second term signal output from the second kernel processing circuitry to provide a pre-compensated baseband signal in the dynamic deviation reduction mode.
The prior art of record fails to teach the claimed subject matter as claimed and substantially connected in claims 11-17.
Regarding claim 18, the prior art of record, Ding (US 2015/0256216) teaches digital predistorter to pre-compensate for nonlinearity in a power amplifier (Abstract, Fig.4, and Sections 0004-0006 and 0021-0025).
Sanchez (US 2022/0200618) teaches a memoryless polynomial mode and a memory polynomial mode (Sections 0022, 0025, and 0032); a dynamic deviation reduction mode (Sections 0022, 0025, and 0032).
The prior art of record fails to teach a digital predistorter to pre-compensate for nonlinearity in a power amplifier, comprising first kernel processing circuitry configured to process an input baseband signal in one of a memoryless polynomial mode and a memory polynomial mode in response to a first enable signal; second kernel processing circuitry configured to perform an operation in a dynamic deviation reduction mode on the input baseband signal in response to a second enable signal; an adder configured to add a first term signal output from the first kernel processing circuitry and a second term signal output from the second kernel processing circuitry to provide a pre-compensated baseband signal in the dynamic deviation reduction mode; and a selector configured to select one of the first term signal and an output of the adder in response to a selection signal, wherein the first term signal corresponds to Math.k=0K-1.Math.m=0M-1αk,m.Math.x(n-m).Math.kx(n-m), where a.sub.k,m represents a polynomial coefficient of a diagonal term, M is a maximum order of memory length, K is a non-linear order, and m is a memory depth, and the second term signal corresponds to .Math.k=1K-1.Math.l=1L-1bk,l.Math.x(n).Math.2(k-1)x2(n)x*(n-1), where b.sub.k,l is a polynomial coefficient of an off-diagonal term, and x*(n−1) is a complex conjugate of x(n−1).
The prior art of record fails to teach the claimed subject matter as claimed and substantially connected in claims 18-20.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDREW WENDELL whose telephone number is (571)272-0557. The examiner can normally be reached Monday-Friday 8:30AM-5PM.
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/ANDREW WENDELL/Primary Examiner, Art Unit 2648 4/10/2026
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