DETAILED ACTION
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
Claims 1-10 are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because claim 1 includes the claim limitation(s) “an inspection unit receiving…, and comparing grayscale of the image…. ”, herein “an inspection unit receiving……” perform{ing} certain functions as a generic placeholder that is coupled with functional language, and the terms which precede without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structures of system, such as defined in Fig. 6 of the Specification, “Inspection unit 50” is coupled/connected with “Thermal Imager 30” .Thus, the respective “…Inspection unit…”, recited in claims 1-10, associated with functions of “receiving the image…, and comparing…”, and “detecting grayscales of the image…” are considered as being implemented by computer hardware, such as a processor, as performing the claimed functions, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10 are rejected under 35 U.S.C. 103 as being unpatentable over KIM (US 20240170445 A1), and in view of BENDJUS (WO 2023017029 A1), and further in view of Enachescu (US 20030137318 A1).
Re Claim 1, KIM discloses a method for detecting semiconductor defects using temperature difference contrast (see KIM: e.g., Fig. 1, reproduced below:
PNG
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802
702
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and see: “measuring a temperature change on the surface of the second semiconductor die to which the heat is applied to inspect a state of the bonding interface.” In abstract, and, “the embodiments relate to an apparatus for inspecting defects in a semiconductor package” in [0002], and [0004]-[0005]; and,
--FIG. 4 represents a thermal image obtained by a thermal imaging camera capturing a portion ‘A’ of FIG. 2, and a graph illustrating temperature distribution across a specific area of the thermal image,…
FIG. 6 is a graph showing a difference in die surface temperature according to presence or absence of a void in a region of interest obtained according to the heating method of FIGS. 5A to 5C, in accordance with embodiments.
[0028] Referring to FIGS. 1 to 6, a defect inspection apparatus for a semiconductor package 10 may include a stage 20, a heater 30 and a camera 40. In addition, the defect inspection apparatus 10 may further include a controller 50 connected to the stage 20, the heater 30 and the camera 40 to control their operations.--, in [0027]-[0028]);
comprising the steps of:
obtaining an image of a first surface or a second surface of a standard
semiconductor (see KIM: e.g., -- FIG. 6 is a graph showing a difference in die surface temperature according to presence or absence of a void in a region of interest obtained according to the heating method of FIGS. 5A to 5C--, in [0027]-[0028]);
KIM however does not explicitly disclose obtaining an image of a second surface of a semiconductor,
BENDJUS discloses obtaining an image of a second surface of a semiconductor, (see BENDJUS: e.g., Fig. 1, and, -- the LSP method can also be used to detect the connection defects of both surfaces of the substrate, i.e. the semiconductor element surface and the free ceramic substrate surface. For some substrate structures with thin metallization layers, due to the high transmission of the ceramic (e.g. AI2O3 and AIN), an additional second optical measurement setup with white light illumination (or infrared illumination) can also be used for measurements from the back of the substrate in order to detect the connection errors from the ceramic side of a To recognize substrate on which no semiconductor element is present. With the help of image processing methods, the connection errors open to the ceramic layer can also be recognized from the static white light images. A prerequisite for the latter is an exposed ceramic substrate.-- ,in page 5/33 of including the English translation version of WO 2023017029 A1 {as provided as NPL with this Office Action}, and, -- FIG. 1 shows a measurement system for carrying out an LSP,… a digital camera as an optical sensor 4, which in this example is combined with a lens 5, and a thermal excitation source 6 in the form of a lasers. The illumination laser device 2 emits laser beams, which are irradiated through the optical lens system 3 and impinge on the surface of a semiconductor element 1a to illuminate the same…. The first measuring module can be aligned either with the surface of the semiconductor element 1a or with the surface of the substrate 1c. The second measurement module is an additional measurement setup with a circular LED module 9 and a digital camera 7, which is combined with a lens 8.--, in pages 6-7/33 of including the English translation version of WO 2023017029 A1 {as provided as NPL with this Office Action; and “compared with the results obtained in advance for defect-free and defect-afflicted similar material connections in order to decide whether specified quality criteria of the tested material connection have been achieved or not.”, in claim 1});
KIM and BENDJUS are combinable as they are in the same field of endeavor: thermal images processing to detect defects in semiconductors. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify KIM’s method using BENDJUS’s teachings by including obtaining an image of a second surface of a semiconductor to KIM’s obtaining image of a standard semiconductor in order to detect the defects of both surfaces of the substrate (see BENDJUS: e.g., Fig. 1 in pages 5, 6-7/33 of including the English translation version of WO 2023017029 A1 {as provided as NPL with this Office Action, and claim 1);
KIM as modified by BENDJUS further disclose applying a heat source to part or all of a first surface of a target semiconductor for the part or all of the first surface of the target semiconductor to absorb heat from the heat source (see KIM: e.g., Fig. 1, reproduced below:
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802
702
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Greyscale
and see: “measuring a temperature change on the surface of the second semiconductor die to which the heat is applied to inspect a state of the bonding interface.” In abstract, and, “the embodiments relate to an apparatus for inspecting defects in a semiconductor package” in [0002], and [0004]-[0005]; and,
--FIG. 4 represents a thermal image obtained by a thermal imaging camera capturing a portion ‘A’ of FIG. 2, and a graph illustrating temperature distribution across a specific area of the thermal image,…
FIG. 6 is a graph showing a difference in die surface temperature according to presence or absence of a void in a region of interest obtained according to the heating method of FIGS. 5A to 5C, in accordance with embodiments.
[0028] Referring to FIGS. 1 to 6, a defect inspection apparatus for a semiconductor package 10 may include a stage 20, a heater 30 and a camera 40. In addition, the defect inspection apparatus 10 may further include a controller 50 connected to the stage 20, the heater 30 and the camera 40 to control their operations.--, in [0027]-[0028]);
the heat source stopping heating part or all of the first surface of the target
semiconductor, and part or all of the first surface of the target semiconductor completely diffusing heat in a direction towards part or all of a second surface of the target semiconductor (see KIM: e.g., --a heater configured to apply heat to a surface of the second semiconductor die on the stage, which is opposite to a bonding interface of the first semiconductor die and the second semiconductor die; and a camera configured to measure a temperature change on the surface of the second semiconductor die to which the heat is applied to check a state of the bonding interface.
[0007] According to embodiments, there is provided a method of manufacturing a semiconductor package using the defect inspection apparatus. The method may include: providing a first semiconductor die on a stage; bonding a second semiconductor die to the first semiconductor die to each other; applying heat to a surface of the second semiconductor die, which is opposite to a bonding interface of the first semiconductor die and the second semiconductor die; and measuring a temperature change on the surface of the second semiconductor die to which the heat is applied to inspect a state of the bonding interface.
[0008] According to embodiments, the inspecting the state of the bonding interface may include determining whether a void exists between the first semiconductor die and the second semiconductor die by the measuring the temperature change.--, in [0006]-[0008]; and,
--[0037] Heat radiated from the heat source onto the upper surface of the upper semiconductor die D3 may diffuse in a depth direction of the die stack DS. In the process of heat diffusion, a heat transfer path may vary according to the presence or absence of a void at the bonding interface formed in the stacking step. This is because the thermal diffusivity at the void is relatively small compared to the thermal diffusivity at a completely bonded interface. Thus, heat may spread (diffuse) not in a direction where the void exists but bypasses the void. For example, thermal diffusivity of silicon is 0.895 [cm.sup.2/s], and thermal diffusivity of air is 0.213 [cm.sup.2/s]. If a thickness of bonded semiconductor dies is sufficiently thin, a temperature singularity may occur on a surface of the upper semiconductor die D3 irradiated with heat due to the change in the heat transfer path around the void. Accordingly, while the stage 20 moves, the thermal imaging camera may measure a temperature change of the surface of the upper semiconductor die within a region of interest (ROI), and thus, it may be possible to inspect whether a void is generated at the bonding interface in the previous bonding process.--, in [0037]-[0039]);
a thermal imager sensing temperatures of part or all of the first surface of the
target semiconductor or temperatures of part or all of the second surface to
obtain an image of the first surface or the second surface of the target
semiconductor (see KIM: e.g., --[0036] As illustrated in FIGS. 3 and 4, after bonding the upper semiconductor die D3 to the lower semiconductor die D2 by performing each stacking step (e.g., three-layer stacking step), heat may be applied to the upper surface of the upper semiconductor die D3 through the heat source of the heater 30, and the upper surface of the upper semiconductor die D3 may be observed through the thermal imaging camera, to obtain a thermal image representing temperature distribution of upper surface of the upper semiconductor die D3 according to the presence or absence of voids, i.e., air gaps.--, in [0036]-[0039]); and
an inspection unit receiving the image of the first surface or the second surface of the standard semiconductor and the image of the first surface or the second surface of the target semiconductor, and comparing the image of the first surface or the second surface of the standard semiconductor with the image of the first surface or the second surface of the target semiconductor to determine whether the target semiconductor having defects (see KIM: e.g., --[0036] As illustrated in FIGS. 3 and 4, after bonding the upper semiconductor die D3 to the lower semiconductor die D2 by performing each stacking step (e.g., three-layer stacking step), heat may be applied to the upper surface of the upper semiconductor die D3 through the heat source of the heater 30, and the upper surface of the upper semiconductor die D3 may be observed through the thermal imaging camera, to obtain a thermal image representing temperature distribution of upper surface of the upper semiconductor die D3 according to the presence or absence of voids, i.e., air gaps.
--[0037] Heat radiated from the heat source onto the upper surface of the upper semiconductor die D3 may diffuse in a depth direction of the die stack DS. In the process of heat diffusion, a heat transfer path may vary according to the presence or absence of a void at the bonding interface formed in the stacking step. This is because the thermal diffusivity at the void is relatively small compared to the thermal diffusivity at a completely bonded interface. Thus, heat may spread (diffuse) not in a direction where the void exists but bypasses the void. For example, thermal diffusivity of silicon is 0.895 [cm.sup.2/s], and thermal diffusivity of air is 0.213 [cm.sup.2/s]. If a thickness of bonded semiconductor dies is sufficiently thin, a temperature singularity may occur on a surface of the upper semiconductor die D3 irradiated with heat due to the change in the heat transfer path around the void. Accordingly, while the stage 20 moves, the thermal imaging camera may measure a temperature change of the surface of the upper semiconductor die within a region of interest (ROI), and thus, it may be possible to inspect whether a void is generated at the bonding interface in the previous bonding process.
[0038] In example embodiments, the defect inspection apparatus 10 may apply heat in the form of a sinusoidal wave to the upper surface of the upper semiconductor die D3 on the lower semiconductor die D2. As shown in FIGS. 5A to 5C, while the stage 20 reciprocally moves within a preset distance based on a specific position, the heater 30 over the stage 20 may irradiate a light (L) to a specific position on the upper surface of the upper semiconductor die D3. For example, the specific position may be a virtual line passing through a center of the upper semiconductor die D3 in a direction parallel to the Y direction, and the preset distance may be a distance T of a portion of the upper semiconductor die D3.
[0039] Referring to FIG. 6, a graph G1 in a solid-line curve shows heat (power (W)) in the form of a sinusoidal wave applied to both a first upper semiconductor die without a void in a bonding interface of a lower semiconductor die therebelow and a second upper semiconductor die with a void in a bonding surface of a lower semiconductor die therebelow, and a graph G2 in a dashed-line curve is a surface temperature difference (ΔT, ° C.) between a surface temperature (T #1) of the first upper semiconductor die and a surface temperature (T #2) of the second upper semiconductor die in a region of interest (ROI). The temperature difference (ΔT) may be a difference value between a temperature (T #1) in the die without a void and a temperature (T #2) in the die with a void. For example, several semiconductor dies D may be positioned within the region of interest (ROI), and there may be some dies with voids and other dies without voids within the region of interest (ROI). Compared to the die without a void, the die with voids does not spread heat well due to the thermal resistance of the voids, so the temperature (T #2) in the die with a void may increase, which is different from the temperature (T #1) of the die without a void. In other words, the larger the temperature difference, the easier the IR Camera can detect the die with voids. As the stage 20 periodically moves from side to side, the temperature difference appearing on the surface of the upper semiconductor dies shows a specific cycle because the heat source entering vicinity of the void does not reach a steady state and is in a transient state. At this time, if a position where the temperature difference is the largest is extracted, void inspection can be effectively performed.--, in [0036]-[0039]);
KIM as modified by BENDJUS however still do not explicitly disclose comparing grayscale of the images in determining whether the target semiconductor having defects,
ENACHESCU discloses comparing grayscale of the images in determining whether the target semiconductor having defects (see ENACHESCU: e.g., -- Described are methods and systems for providing improved defect detection and analysis using infrared thermography. Test vectors heat features of a device under test to produce thermal characteristics useful in identifying defects. The test vectors are timed to enhance the thermal contrast between defects and the surrounding features, enabling IR imaging equipment to acquire improved thermographic images. In some embodiments, a combination of AC and DC test vectors maximize power transfer to expedite heating, and therefore testing. Mathematical transformations applied to the improved images further enhance defect detection and analysis. Some defects produce image artifacts, or "defect artifacts," that obscure the defects, rendering difficult the task of defect location. Some embodiments employ defect-location algorithms that analyze defect artifacts to precisely locate corresponding defects.--, in abstract, Fig. 9, and, -- Subsequent processing automatically locates the defect data within the defect artifacts to produce a list of defect coordinates. In one embodiment, composite image 905 is an IR composite image of the type discussed above; however, many other types of images depict subjects of interest surrounded by artifacts of those subjects. Algorithms in accordance with the invention can be used to localize such subjects. For example, images obtained from visual optics and/or nuclear-type experiments depict subjects and subject-artifacts.
[0077] The above-referenced Bovik reference describes a connection between gray-level and binary morphology that is used in some embodiments to distinguish defects from their associated artifacts.--, in [0076]-[0080], and [0100]);
KIM (as modified by BENDJUS) and ENACHESCU are combinable as they are in the same field of endeavor: thermal images processing to detect defects in semiconductors. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify KIM (as modified by BENDJUS)’s method using ENACHESCU’s teachings by including comparing grayscale of the images in determining whether the target semiconductor having defects to KIM (as modified by BENDJUS)’s detecting defects in order to provide defect detection and analysis using infrared thermography based on thermal characteristics in identifying defects (see ENACHESCU: e.g., Fig. 9 in abstract, [0076]-[0078] and [0100]).
Re Claim 2, KIM as modified by BENDJUS and ENACHESCU further disclose wherein the step of obtaining an image of a first surface or a second surface of a standard semiconductor further includes: the heat source heating part or all of the first surface of the standard semiconductor, and the part or all of first surface of the standard semiconductor absorbing heat from the heat source; the heat source stopping heating part or all of the first surface of the standard semiconductor, and part or all of the first surface of the standard semiconductor diffusing heat in a direction towards part or all of the second surface of the standard semiconductor; and the thermal imager sensing the temperatures of part or all of the first surface of the standard semiconductor or the temperatures of part or all of the second surface to obtain an image of the first surface or the second surface of the standard semiconductor (see KIM: e.g., --a heater configured to apply heat to a surface of the second semiconductor die on the stage, which is opposite to a bonding interface of the first semiconductor die and the second semiconductor die; and a camera configured to measure a temperature change on the surface of the second semiconductor die to which the heat is applied to check a state of the bonding interface.
[0007] According to embodiments, there is provided a method of manufacturing a semiconductor package using the defect inspection apparatus. The method may include: providing a first semiconductor die on a stage; bonding a second semiconductor die to the first semiconductor die to each other; applying heat to a surface of the second semiconductor die, which is opposite to a bonding interface of the first semiconductor die and the second semiconductor die; and measuring a temperature change on the surface of the second semiconductor die to which the heat is applied to inspect a state of the bonding interface.
[0008] According to embodiments, the inspecting the state of the bonding interface may include determining whether a void exists between the first semiconductor die and the second semiconductor die by the measuring the temperature change.--, in [0006]-[0008]; and,
--[0036] As illustrated in FIGS. 3 and 4, after bonding the upper semiconductor die D3 to the lower semiconductor die D2 by performing each stacking step (e.g., three-layer stacking step), heat may be applied to the upper surface of the upper semiconductor die D3 through the heat source of the heater 30, and the upper surface of the upper semiconductor die D3 may be observed through the thermal imaging camera, to obtain a thermal image representing temperature distribution of upper surface of the upper semiconductor die D3 according to the presence or absence of voids, i.e., air gaps.
--[0037] Heat radiated from the heat source onto the upper surface of the upper semiconductor die D3 may diffuse in a depth direction of the die stack DS. In the process of heat diffusion, a heat transfer path may vary according to the presence or absence of a void at the bonding interface formed in the stacking step. This is because the thermal diffusivity at the void is relatively small compared to the thermal diffusivity at a completely bonded interface. Thus, heat may spread (diffuse) not in a direction where the void exists but bypasses the void. For example, thermal diffusivity of silicon is 0.895 [cm.sup.2/s], and thermal diffusivity of air is 0.213 [cm.sup.2/s]. If a thickness of bonded semiconductor dies is sufficiently thin, a temperature singularity may occur on a surface of the upper semiconductor die D3 irradiated with heat due to the change in the heat transfer path around the void. Accordingly, while the stage 20 moves, the thermal imaging camera may measure a temperature change of the surface of the upper semiconductor die within a region of interest (ROI), and thus, it may be possible to inspect whether a void is generated at the bonding interface in the previous bonding process.
[0038] In example embodiments, the defect inspection apparatus 10 may apply heat in the form of a sinusoidal wave to the upper surface of the upper semiconductor die D3 on the lower semiconductor die D2. As shown in FIGS. 5A to 5C, while the stage 20 reciprocally moves within a preset distance based on a specific position, the heater 30 over the stage 20 may irradiate a light (L) to a specific position on the upper surface of the upper semiconductor die D3. For example, the specific position may be a virtual line passing through a center of the upper semiconductor die D3 in a direction parallel to the Y direction, and the preset distance may be a distance T of a portion of the upper semiconductor die D3.
[0039] Referring to FIG. 6, a graph G1 in a solid-line curve shows heat (power (W)) in the form of a sinusoidal wave applied to both a first upper semiconductor die without a void in a bonding interface of a lower semiconductor die therebelow and a second upper semiconductor die with a void in a bonding surface of a lower semiconductor die therebelow, and a graph G2 in a dashed-line curve is a surface temperature difference (ΔT, ° C.) between a surface temperature (T #1) of the first upper semiconductor die and a surface temperature (T #2) of the second upper semiconductor die in a region of interest (ROI). The temperature difference (ΔT) may be a difference value between a temperature (T #1) in the die without a void and a temperature (T #2) in the die with a void. For example, several semiconductor dies D may be positioned within the region of interest (ROI), and there may be some dies with voids and other dies without voids within the region of interest (ROI). Compared to the die without a void, the die with voids does not spread heat well due to the thermal resistance of the voids, so the temperature (T #2) in the die with a void may increase, which is different from the temperature (T #1) of the die without a void. In other words, the larger the temperature difference, the easier the IR Camera can detect the die with voids. As the stage 20 periodically moves from side to side, the temperature difference appearing on the surface of the upper semiconductor dies shows a specific cycle because the heat source entering vicinity of the void does not reach a steady state and is in a transient state. At this time, if a position where the temperature difference is the largest is extracted, void inspection can be effectively performed.--, in [0036]-[0039]; also see BENDJUS: e.g., Fig. 1, and, -- the LSP method can also be used to detect the connection defects of both surfaces of the substrate, i.e. the semiconductor element surface and the free ceramic substrate surface. For some substrate structures with thin metallization layers, due to the high transmission of the ceramic (e.g. AI2O3 and AIN), an additional second optical measurement setup with white light illumination (or infrared illumination) can also be used for measurements from the back of the substrate in order to detect the connection errors from the ceramic side of a To recognize substrate on which no semiconductor element is present. With the help of image processing methods, the connection errors open to the ceramic layer can also be recognized from the static white light images. A prerequisite for the latter is an exposed ceramic substrate.-- ,in page 5/33 of including the English translation version of WO 2023017029 A1 {as provided as NPL with this Office Action}, and, -- FIG. 1 shows a measurement system for carrying out an LSP,… a digital camera as an optical sensor 4, which in this example is combined with a lens 5, and a thermal excitation source 6 in the form of a lasers. The illumination laser device 2 emits laser beams, which are irradiated through the optical lens system 3 and impinge on the surface of a semiconductor element 1a to illuminate the same…. The first measuring module can be aligned either with the surface of the semiconductor element 1a or with the surface of the substrate 1c. The second measurement module is an additional measurement setup with a circular LED module 9 and a digital camera 7, which is combined with a lens 8.--, in pages 6-7/33 of including the English translation version of WO 2023017029 A1 {as provided as NPL with this Office Action; and “compared with the results obtained in advance for defect-free and defect-afflicted similar material connections in order to decide whether specified quality criteria of the tested material connection have been achieved or not.”, in claim 1}).
Re Claim 3, KIM as modified by BENDJUS and Enachescu further disclose wherein the step of sensing the temperatures of part or all of the first surface of the standard semiconductor or the temperatures of part or all of the second surface of the standard semiconductor by the thermal imager further includes: the thermal imager continuously capturing an image of the temperatures of part or all of the first surface of the standard semiconductor or an image of the temperatures of part or all of the second surface of the standard semiconductor to sense a change of the temperatures of part or all of the first surface of the standard semiconductor or a change of the temperatures of part or all of the second surface of the standard semiconductor (see KIM: e.g., --a heater configured to apply heat to a surface of the second semiconductor die on the stage, which is opposite to a bonding interface of the first semiconductor die and the second semiconductor die; and a camera configured to measure a temperature change on the surface of the second semiconductor die to which the heat is applied to check a state of the bonding interface.
[0007] According to embodiments, there is provided a method of manufacturing a semiconductor package using the defect inspection apparatus. The method may include: providing a first semiconductor die on a stage; bonding a second semiconductor die to the first semiconductor die to each other; applying heat to a surface of the second semiconductor die, which is opposite to a bonding interface of the first semiconductor die and the second semiconductor die; and measuring a temperature change on the surface of the second semiconductor die to which the heat is applied to inspect a state of the bonding interface.
[0008] According to embodiments, the inspecting the state of the bonding interface may include determining whether a void exists between the first semiconductor die and the second semiconductor die by the measuring the temperature change.--, in [0006]-[0008]; and,
--[0036] As illustrated in FIGS. 3 and 4, after bonding the upper semiconductor die D3 to the lower semiconductor die D2 by performing each stacking step (e.g., three-layer stacking step), heat may be applied to the upper surface of the upper semiconductor die D3 through the heat source of the heater 30, and the upper surface of the upper semiconductor die D3 may be observed through the thermal imaging camera, to obtain a thermal image representing temperature distribution of upper surface of the upper semiconductor die D3 according to the presence or absence of voids, i.e., air gaps.
--[0037] Heat radiated from the heat source onto the upper surface of the upper semiconductor die D3 may diffuse in a depth direction of the die stack DS. In the process of heat diffusion, a heat transfer path may vary according to the presence or absence of a void at the bonding interface formed in the stacking step. This is because the thermal diffusivity at the void is relatively small compared to the thermal diffusivity at a completely bonded interface. Thus, heat may spread (diffuse) not in a direction where the void exists but bypasses the void. For example, thermal diffusivity of silicon is 0.895 [cm.sup.2/s], and thermal diffusivity of air is 0.213 [cm.sup.2/s]. If a thickness of bonded semiconductor dies is sufficiently thin, a temperature singularity may occur on a surface of the upper semiconductor die D3 irradiated with heat due to the change in the heat transfer path around the void. Accordingly, while the stage 20 moves, the thermal imaging camera may measure a temperature change of the surface of the upper semiconductor die within a region of interest (ROI), and thus, it may be possible to inspect whether a void is generated at the bonding interface in the previous bonding process.
[0038] In example embodiments, the defect inspection apparatus 10 may apply heat in the form of a sinusoidal wave to the upper surface of the upper semiconductor die D3 on the lower semiconductor die D2. As shown in FIGS. 5A to 5C, while the stage 20 reciprocally moves within a preset distance based on a specific position, the heater 30 over the stage 20 may irradiate a light (L) to a specific position on the upper surface of the upper semiconductor die D3. For example, the specific position may be a virtual line passing through a center of the upper semiconductor die D3 in a direction parallel to the Y direction, and the preset distance may be a distance T of a portion of the upper semiconductor die D3.
[0039] Referring to FIG. 6, a graph G1 in a solid-line curve shows heat (power (W)) in the form of a sinusoidal wave applied to both a first upper semiconductor die without a void in a bonding interface of a lower semiconductor die therebelow and a second upper semiconductor die with a void in a bonding surface of a lower semiconductor die therebelow, and a graph G2 in a dashed-line curve is a surface temperature difference (ΔT, ° C.) between a surface temperature (T #1) of the first upper semiconductor die and a surface temperature (T #2) of the second upper semiconductor die in a region of interest (ROI). The temperature difference (ΔT) may be a difference value between a temperature (T #1) in the die without a void and a temperature (T #2) in the die with a void. For example, several semiconductor dies D may be positioned within the region of interest (ROI), and there may be some dies with voids and other dies without voids within the region of interest (ROI). Compared to the die without a void, the die with voids does not spread heat well due to the thermal resistance of the voids, so the temperature (T #2) in the die with a void may increase, which is different from the temperature (T #1) of the die without a void. In other words, the larger the temperature difference, the easier the IR Camera can detect the die with voids. As the stage 20 periodically moves from side to side, the temperature difference appearing on the surface of the upper semiconductor dies shows a specific cycle because the heat source entering vicinity of the void does not reach a steady state and is in a transient state. At this time, if a position where the temperature difference is the largest is extracted, void inspection can be effectively performed.--, in [0036]-[0039]; also see BENDJUS: e.g., Fig. 1, and, -- the LSP method can also be used to detect the connection defects of both surfaces of the substrate, i.e. the semiconductor element surface and the free ceramic substrate surface. For some substrate structures with thin metallization layers, due to the high transmission of the ceramic (e.g. AI2O3 and AIN), an additional second optical measurement setup with white light illumination (or infrared illumination) can also be used for measurements from the back of the substrate in order to detect the connection errors from the ceramic side of a To recognize substrate on which no semiconductor element is present. With the help of image processing methods, the connection errors open to the ceramic layer can also be recognized from the static white light images. A prerequisite for the latter is an exposed ceramic substrate.-- ,in page 5/33 of including the English translation version of WO 2023017029 A1 {as provided as NPL with this Office Action}, and, -- FIG. 1 shows a measurement system for carrying out an LSP,… a digital camera as an optical sensor 4, which in this example is combined with a lens 5, and a thermal excitation source 6 in the form of a lasers. The illumination laser device 2 emits laser beams, which are irradiated through the optical lens system 3 and impinge on the surface of a semiconductor element 1a to illuminate the same…. The first measuring module can be aligned either with the surface of the semiconductor element 1a or with the surface of the substrate 1c. The second measurement module is an additional measurement setup with a circular LED module 9 and a digital camera 7, which is combined with a lens 8.--, in pages 6-7/33 of including the English translation version of WO 2023017029 A1 {as provided as NPL with this Office Action; and “compared with the results obtained in advance for defect-free and defect-afflicted similar material connections in order to decide whether specified quality criteria of the tested material connection have been achieved or not.”, in claim 1}).
Re Claim 4, KIM as modified by BENDJUS and Enachescu further disclose wherein the step of determining whether the target semiconductor having defects further includes: compared with the image of the first surface or the second surface of the standard semiconductor, the inspection unit detecting grayscale of the image of at least one point area of the first surface of the target semiconductor to be darker or grayscale of the image of at least one point area of the second surface of the target semiconductor to be lighter, so as to determine that the target semiconductor to be defective and the defect to be at least one conductive wire breakage (see KIM: e.g., --a heater configured to apply heat to a surface of the second semiconductor die on the stage, which is opposite to a bonding interface of the first semiconductor die and the second semiconductor die; and a camera configured to measure a temperature change on the surface of the second semiconductor die to which the heat is applied to check a state of the bonding interface.
[0007] According to embodiments, there is provided a method of manufacturing a semiconductor package using the defect inspection apparatus. The method may include: providing a first semiconductor die on a stage; bonding a second semiconductor die to the first semiconductor die to each other; applying heat to a surface of the second semiconductor die, which is opposite to a bonding interface of the first semiconductor die and the second semiconductor die; and measuring a temperature change on the surface of the second semiconductor die to which the heat is applied to inspect a state of the bonding interface.
[0008] According to embodiments, the inspecting the state of the bonding interface may include determining whether a void exists between the first semiconductor die and the second semiconductor die by the measuring the temperature change.--, in [0006]-[0008]; and,
--[0036] As illustrated in FIGS. 3 and 4, after bonding the upper semiconductor die D3 to the lower semiconductor die D2 by performing each stacking step (e.g., three-layer stacking step), heat may be applied to the upper surface of the upper semiconductor die D3 through the heat source of the heater 30, and the upper surface of the upper semiconductor die D3 may be observed through the thermal imaging camera, to obtain a thermal image representing temperature distribution of upper surface of the upper semiconductor die D3 according to the presence or absence of voids, i.e., air gaps.
--[0037] Heat radiated from the heat source onto the upper surface of the upper semiconductor die D3 may diffuse in a depth direction of the die stack DS. In the process of heat diffusion, a heat transfer path may vary according to the presence or absence of a void at the bonding interface formed in the stacking step. This is because the thermal diffusivity at the void is relatively small compared to the thermal diffusivity at a completely bonded interface. Thus, heat may spread (diffuse) not in a direction where the void exists but bypasses the void. For example, thermal diffusivity of silicon is 0.895 [cm.sup.2/s], and thermal diffusivity of air is 0.213 [cm.sup.2/s]. If a thickness of bonded semiconductor dies is sufficiently thin, a temperature singularity may occur on a surface of the upper semiconductor die D3 irradiated with heat due to the change in the heat transfer path around the void. Accordingly, while the stage 20 moves, the thermal imaging camera may measure a temperature change of the surface of the upper semiconductor die within a region of interest (ROI), and thus, it may be possible to inspect whether a void is generated at the bonding interface in the previous bonding process.
[0038] In example embodiments, the defect inspection apparatus 10 may apply heat in the form of a sinusoidal wave to the upper surface of the upper semiconductor die D3 on the lower semiconductor die D2. As shown in FIGS. 5A to 5C, while the stage 20 reciprocally moves within a preset distance based on a specific position, the heater 30 over the stage 20 may irradiate a light (L) to a specific position on the upper surface of the upper semiconductor die D3. For example, the specific position may be a virtual line passing through a center of the upper semiconductor die D3 in a direction parallel to the Y direction, and the preset distance may be a distance T of a portion of the upper semiconductor die D3.
[0039] Referring to FIG. 6, a graph G1 in a solid-line curve shows heat (power (W)) in the form of a sinusoidal wave applied to both a first upper semiconductor die without a void in a bonding interface of a lower semiconductor die therebelow and a second upper semiconductor die with a void in a bonding surface of a lower semiconductor die therebelow, and a graph G2 in a dashed-line curve is a surface temperature difference (ΔT, ° C.) between a surface temperature (T #1) of the first upper semiconductor die and a surface temperature (T #2) of the second upper semiconductor die in a region of interest (ROI). The temperature difference (ΔT) may be a difference value between a temperature (T #1) in the die without a void and a temperature (T #2) in the die with a void. For example, several semiconductor dies D may be positioned within the region of interest (ROI), and there may be some dies with voids and other dies without voids within the region of interest (ROI). Compared to the die without a void, the die with voids does not spread heat well due to the thermal resistance of the voids, so the temperature (T #2) in the die with a void may increase, which is different from the temperature (T #1) of the die without a void. In other words, the larger the temperature difference, the easier the IR Camera can detect the die with voids. As the stage 20 periodically moves from side to side, the temperature difference appearing on the surface of the upper semiconductor dies shows a specific cycle because the heat source entering vicinity of the void does not reach a steady state and is in a transient state. At this time, if a position where the temperature difference is the largest is extracted, void inspection can be effectively performed.--, in [0036]-[0039]; also see BENDJUS: e.g., Fig. 1, and, -- the LSP method can also be used to detect the connection defects of both surfaces of the substrate, i.e. the semiconductor element surface and the free ceramic substrate surface. For some substrate structures with thin metallization layers, due to the high transmission of the ceramic (e.g. AI2O3 and AIN), an additional second optical measurement setup with white light illumination (or infrared illumination) can also be used for measurements from the back of the substrate in order to detect the connection errors from the ceramic side of a To recognize substrate on which no semiconductor element is present. With the help of image processing methods, the connection errors open to the ceramic layer can also be recognized from the static white light images. A prerequisite for the latter is an exposed ceramic substrate.-- ,in page 5/33 of including the English translation version of WO 2023017029 A1 {as provided as NPL with this Office Action}, and, -- FIG. 1 shows a measurement system for carrying out an LSP,… a digital camera as an optical sensor 4, which in this example is combined with a lens 5, and a thermal excitation source 6 in the form of a lasers. The illumination laser device 2 emits laser beams, which are irradiated through the optical lens system 3 and impinge on the surface of a semiconductor element 1a to illuminate the same…. The first measuring module can be aligned either with the surface of the semiconductor element 1a or with the surface of the substrate 1c. The second measurement module is an additional measurement setup with a circular LED module 9 and a digital camera 7, which is combined with a lens 8.--, in pages 6-7/33 of including the English translation version of WO 2023017029 A1 {as provided as NPL with this Office Action; and “compared with the results obtained in advance for defect-free and defect-afflicted similar material connections in order to decide whether specified quality criteria of the tested material connection have been achieved or not.”, in claim 1}, further see ENACHESCU: e.g., -- Described are methods and systems for providing improved defect detection and analysis using infrared thermography. Test vectors heat features of a device under test to produce thermal characteristics useful in identifying defects. The test vectors are timed to enhance the thermal contrast between defects and the surrounding features, enabling IR imaging equipment to acquire improved thermographic images. In some embodiments, a combination of AC and DC test vectors maximize power transfer to expedite heating, and therefore testing. Mathematical transformations applied to the improved images further enhance defect detection and analysis. Some defects produce image artifacts, or "defect artifacts," that obscure the defects, rendering difficult the task of defect location. Some embodiments employ defect-location algorithms that analyze defect artifacts to precisely locate corresponding defects.--, in abstract, Fig. 9, and, -- Subsequent processing automatically locates the defect data within the defect artifacts to produce a list of defect coordinates. In one embodiment, composite image 905 is an IR composite image of the type discussed above; however, many other types of images depict subjects of interest surrounded by artifacts of those subjects. Algorithms in accordance with the invention can be used to localize such subjects. For example, images obtained from visual optics and/or nuclear-type experiments depict subjects and subject-artifacts.
[0077] The above-referenced Bovik reference describes a connection between gray-level and binary morphology that is used in some embodiments to distinguish defects from their associated artifacts.--, in [0076]-[0080], and [0100]).
Re Claim 5, KIM as modified by BENDJUS and Enachescu further disclose wherein the step of determining whether the target semiconductor having defects further includes: compared with the image of the first surface or the second surface of the standard semiconductor, the inspection unit detecting grayscale of the image of the first surface of the target semiconductor having at least one less point area or grayscale of the image of the second surface of the target semiconductor having at least one less point area, so as to determine that the target semiconductor to be defective and the defect to be at least one erroneous conductive wire or assembly misalignment (see KIM: e.g., --a heater configured to apply heat to a surface of the second semiconductor die on the stage, which is opposite to a bonding interface of the first semiconductor die and the second semiconductor die; and a camera configured to measure a temperature change on the surface of the second semiconductor die to which the heat is applied to check a state of the bonding interface.
[0007] According to embodiments, there is provided a method of manufacturing a semiconductor package using the defect inspection apparatus. The method may include: providing a first semiconductor die on a stage; bonding a second semiconductor die to the first semiconductor die to each other; applying heat to a surface of the second semiconductor die, which is opposite to a bonding interface of the first semiconductor die and the second semiconductor die; and measuring a temperature change on the surface of the second semiconductor die to which the heat is applied to inspect a state of the bonding interface.
[0008] According to embodiments, the inspecting the state of the bonding interface may include determining whether a void exists between the first semiconductor die and the second semiconductor die by the measuring the temperature change.--, in [0006]-[0008]; and,
--[0036] As illustrated in FIGS. 3 and 4, after bonding the upper semiconductor die D3 to the lower semiconductor die D2 by performing each stacking step (e.g., three-layer stacking step), heat may be applied to the upper surface of the upper semiconductor die D3 through the heat source of the heater 30, and the upper surface of the upper semiconductor die D3 may be observed through the thermal imaging camera, to obtain a thermal image representing temperature distribution of upper surface of the upper semiconductor die D3 according to the presence or absence of voids, i.e., air gaps.
--[0037] Heat radiated from the heat source onto the upper surface of the upper semiconductor die D3 may diffuse in a depth direction of the die stack DS. In the process of heat diffusion, a heat transfer path may vary according to the presence or absence of a void at the bonding interface formed in the stacking step. This is because the thermal diffusivity at the void is relatively small compared to the thermal diffusivity at a completely bonded interface. Thus, heat may spread (diffuse) not in a direction where the void exists but bypasses the void. For example, thermal diffusivity of silicon is 0.895 [cm.sup.2/s], and thermal diffusivity of air is 0.213 [cm.sup.2/s]. If a thickness of bonded semiconductor dies is sufficiently thin, a temperature singularity may occur on a surface of the upper semiconductor die D3 irradiated with heat due to the change in the heat transfer path around the void. Accordingly, while the stage 20 moves, the thermal imaging camera may measure a temperature change of the surface of the upper semiconductor die within a region of interest (ROI), and thus, it may be possible to inspect whether a void is generated at the bonding interface in the previous bonding process.
[0038] In example embodiments, the defect inspection apparatus 10 may apply heat in the form of a sinusoidal wave to the upper surface of the upper semiconductor die D3 on the lower semiconductor die D2. As shown in FIGS. 5A to 5C, while the stage 20 reciprocally moves within a preset distance based on a specific position, the heater 30 over the stage 20 may irradiate a light (L) to a specific position on the upper surface of the upper semiconductor die D3. For example, the specific position may be a virtual line passing through a center of the upper semiconductor die D3 in a direction parallel to the Y direction, and the preset distance may be a distance T of a portion of the upper semiconductor die D3.
[0039] Referring to FIG. 6, a graph G1 in a solid-line curve shows heat (power (W)) in the form of a sinusoidal wave applied to both a first upper semiconductor die without a void in a bonding interface of a lower semiconductor die therebelow and a second upper semiconductor die with a void in a bonding surface of a lower semiconductor die therebelow, and a graph G2 in a dashed-line curve is a surface temperature difference (ΔT, ° C.) between a surface temperature (T #1) of the first upper semiconductor die and a surface temperature (T #2) of the second upper semiconductor die in a region of interest (ROI). The temperature difference (ΔT) may be a difference value between a temperature (T #1) in the die without a void and a temperature (T #2) in the die with a void. For example, several semiconductor dies D may be positioned within the region of interest (ROI), and there may be some dies with voids and other dies without voids within the region of interest (ROI). Compared to the die without a void, the die with voids does not spread heat well due to the thermal resistance of the voids, so the temperature (T #2) in the die with a void may increase, which is different from the temperature (T #1) of the die without a void. In other words, the larger the temperature difference, the easier the IR Camera can detect the die with voids. As the stage 20 periodically moves from side to side, the temperature difference appearing on the surface of the upper semiconductor dies shows a specific cycle because the heat source entering vicinity of the void does not reach a steady state and is in a transient state. At this time, if a position where the temperature difference is the largest is extracted, void inspection can be effectively performed.--, in [0036]-[0039]; also see BENDJUS: e.g., Fig. 1, and, -- the LSP method can also be used to detect the connection defects of both surfaces of the substrate, i.e. the semiconductor element surface and the free ceramic substrate surface. For some substrate structures with thin metallization layers, due to the high transmission of the ceramic (e.g. AI2O3 and AIN), an additional second optical measurement setup with white light illumination (or infrared illumination) can also be used for measurements from the back of the substrate in order to detect the connection errors from the ceramic side of a To recognize substrate on which no semiconductor element is present. With the help of image processing methods, the connection errors open to the ceramic layer can also be recognized from the static white light images. A prerequisite for the latter is an exposed ceramic substrate.-- ,in page 5/33 of including the English translation version of WO 2023017029 A1 {as provided as NPL with this Office Action}, and, -- FIG. 1 shows a measurement system for carrying out an LSP,… a digital camera as an optical sensor 4, which in this example is combined with a lens 5, and a thermal excitation source 6 in the form of a lasers. The illumination laser device 2 emits laser beams, which are irradiated through the optical lens system 3 and impinge on the surface of a semiconductor element 1a to illuminate the same…. The first measuring module can be aligned either with the surface of the semiconductor element 1a or with the surface of the substrate 1c. The second measurement module is an additional measurement setup with a circular LED module 9 and a digital camera 7, which is combined with a lens 8.--, in pages 6-7/33 of including the English translation version of WO 2023017029 A1 {as provided as NPL with this Office Action; and “compared with the results obtained in advance for defect-free and defect-afflicted similar material connections in order to decide whether specified quality criteria of the tested material connection have been achieved or not.”, in claim 1}, further see ENACHESCU: e.g., -- Described are methods and systems for providing improved defect detection and analysis using infrared thermography. Test vectors heat features of a device under test to produce thermal characteristics useful in identifying defects. The test vectors are timed to enhance the thermal contrast between defects and the surrounding features, enabling IR imaging equipment to acquire improved thermographic images. In some embodiments, a combination of AC and DC test vectors maximize power transfer to expedite heating, and therefore testing. Mathematical transformations applied to the improved images further enhance defect detection and analysis. Some defects produce image artifacts, or "defect artifacts," that obscure the defects, rendering difficult the task of defect location. Some embodiments employ defect-location algorithms that analyze defect artifacts to precisely locate corresponding defects.--, in abstract, Fig. 9, and, -- Subsequent processing automatically locates the defect data within the defect artifacts to produce a list of defect coordinates. In one embodiment, composite image 905 is an IR composite image of the type discussed above; however, many other types of images depict subjects of interest surrounded by artifacts of those subjects. Algorithms in accordance with the invention can be used to localize such subjects. For example, images obtained from visual optics and/or nuclear-type experiments depict subjects and subject-artifacts.
[0077] The above-referenced Bovik reference describes a connection between gray-level and binary morphology that is used in some embodiments to distinguish defects from their associated artifacts.--, in [0076]-[0080], and [0100]).
Re Claim 6, KIM as modified by BENDJUS and Enachescu further disclose wherein the step of determining whether the target semiconductor having defects further includes: compared with the image of the first surface or the second surface of the standard semiconductor, the inspection unit detecting grayscale of the image of the first surface of the target semiconductor having at least one more point area or grayscale of the image of the second surface of the target semiconductor having at least one more point area, so as to determine that the target semiconductor to be defective and the defect to be at least one erroneous conductive wire or assembly misalignment (see KIM: e.g., --a heater configured to apply heat to a surface of the second semiconductor die on the stage, which is opposite to a bonding interface of the first semiconductor die and the second semiconductor die; and a camera configured to measure a temperature change on the surface of the second semiconductor die to which the heat is applied to check a state of the bonding interface.
[0007] According to embodiments, there is provided a method of manufacturing a semiconductor package using the defect inspection apparatus. The method may include: providing a first semiconductor die on a stage; bonding a second semiconductor die to the first semiconductor die to each other; applying heat to a surface of the second semiconductor die, which is opposite to a bonding interface of the first semiconductor die and the second semiconductor die; and measuring a temperature change on the surface of the second semiconductor die to which the heat is applied to inspect a state of the bonding interface.
[0008] According to embodiments, the inspecting the state of the bonding interface may include determining whether a void exists between the first semiconductor die and the second semiconductor die by the measuring the temperature change.--, in [0006]-[0008]; and,
--[0036] As illustrated in FIGS. 3 and 4, after bonding the upper semiconductor die D3 to the lower semiconductor die D2 by performing each stacking step (e.g., three-layer stacking step), heat may be applied to the upper surface of the upper semiconductor die D3 through the heat source of the heater 30, and the upper surface of the upper semiconductor die D3 may be observed through the thermal imaging camera, to obtain a thermal image representing temperature distribution of upper surface of the upper semiconductor die D3 according to the presence or absence of voids, i.e., air gaps.
--[0037] Heat radiated from the heat source onto the upper surface of the upper semiconductor die D3 may diffuse in a depth direction of the die stack DS. In the process of heat diffusion, a heat transfer path may vary according to the presence or absence of a void at the bonding interface formed in the stacking step. This is because the thermal diffusivity at the void is relatively small compared to the thermal diffusivity at a completely bonded interface. Thus, heat may spread (diffuse) not in a direction where the void exists but bypasses the void. For example, thermal diffusivity of silicon is 0.895 [cm.sup.2/s], and thermal diffusivity of air is 0.213 [cm.sup.2/s]. If a thickness of bonded semiconductor dies is sufficiently thin, a temperature singularity may occur on a surface of the upper semiconductor die D3 irradiated with heat due to the change in the heat transfer path around the void. Accordingly, while the stage 20 moves, the thermal imaging camera may measure a temperature change of the surface of the upper semiconductor die within a region of interest (ROI), and thus, it may be possible to inspect whether a void is generated at the bonding interface in the previous bonding process.
[0038] In example embodiments, the defect inspection apparatus 10 may apply heat in the form of a sinusoidal wave to the upper surface of the upper semiconductor die D3 on the lower semiconductor die D2. As shown in FIGS. 5A to 5C, while the stage 20 reciprocally moves within a preset distance based on a specific position, the heater 30 over the stage 20 may irradiate a light (L) to a specific position on the upper surface of the upper semiconductor die D3. For example, the specific position may be a virtual line passing through a center of the upper semiconductor die D3 in a direction parallel to the Y direction, and the preset distance may be a distance T of a portion of the upper semiconductor die D3.
[0039] Referring to FIG. 6, a graph G1 in a solid-line curve shows heat (power (W)) in the form of a sinusoidal wave applied to both a first upper semiconductor die without a void in a bonding interface of a lower semiconductor die therebelow and a second upper semiconductor die with a void in a bonding surface of a lower semiconductor die therebelow, and a graph G2 in a dashed-line curve is a surface temperature difference (ΔT, ° C.) between a surface temperature (T #1) of the first upper semiconductor die and a surface temperature (T #2) of the second upper semiconductor die in a region of interest (ROI). The temperature difference (ΔT) may be a difference value between a temperature (T #1) in the die without a void and a temperature (T #2) in the die with a void. For example, several semiconductor dies D may be positioned within the region of interest (ROI), and there may be some dies with voids and other dies without voids within the region of interest (ROI). Compared to the die without a void, the die with voids does not spread heat well due to the thermal resistance of the voids, so the temperature (T #2) in the die with a void may increase, which is different from the temperature (T #1) of the die without a void. In other words, the larger the temperature difference, the easier the IR Camera can detect the die with voids. As the stage 20 periodically moves from side to side, the temperature difference appearing on the surface of the upper semiconductor dies shows a specific cycle because the heat source entering vicinity of the void does not reach a steady state and is in a transient state. At this time, if a position where the temperature difference is the largest is extracted, void inspection can be effectively performed.--, in [0036]-[0039]; also see BENDJUS: e.g., Fig. 1, and, -- the LSP method can also be used to detect the connection defects of both surfaces of the substrate, i.e. the semiconductor element surface and the free ceramic substrate surface. For some substrate structures with thin metallization layers, due to the high transmission of the ceramic (e.g. AI2O3 and AIN), an additional second optical measurement setup with white light illumination (or infrared illumination) can also be used for measurements from the back of the substrate in order to detect the connection errors from the ceramic side of a To recognize substrate on which no semiconductor element is present. With the help of image processing methods, the connection errors open to the ceramic layer can also be recognized from the static white light images. A prerequisite for the latter is an exposed ceramic substrate.-- ,in page 5/33 of including the English translation version of WO 2023017029 A1 {as provided as NPL with this Office Action}, and, -- FIG. 1 shows a measurement system for carrying out an LSP,… a digital camera as an optical sensor 4, which in this example is combined with a lens 5, and a thermal excitation source 6 in the form of a lasers. The illumination laser device 2 emits laser beams, which are irradiated through the optical lens system 3 and impinge on the surface of a semiconductor element 1a to illuminate the same…. The first measuring module can be aligned either with the surface of the semiconductor element 1a or with the surface of the substrate 1c. The second measurement module is an additional measurement setup with a circular LED module 9 and a digital camera 7, which is combined with a lens 8.--, in pages 6-7/33 of including the English translation version of WO 2023017029 A1 {as provided as NPL with this Office Action; and “compared with the results obtained in advance for defect-free and defect-afflicted similar material connections in order to decide whether specified quality criteria of the tested material connection have been achieved or not.”, in claim 1}, further see ENACHESCU: e.g., -- Described are methods and systems for providing improved defect detection and analysis using infrared thermography. Test vectors heat features of a device under test to produce thermal characteristics useful in identifying defects. The test vectors are timed to enhance the thermal contrast between defects and the surrounding features, enabling IR imaging equipment to acquire improved thermographic images. In some embodiments, a combination of AC and DC test vectors maximize power transfer to expedite heating, and therefore testing. Mathematical transformations applied to the improved images further enhance defect detection and analysis. Some defects produce image artifacts, or "defect artifacts," that obscure the defects, rendering difficult the task of defect location. Some embodiments employ defect-location algorithms that analyze defect artifacts to precisely locate corresponding defects.--, in abstract, Fig. 9, and, -- Subsequent processing automatically locates the defect data within the defect artifacts to produce a list of defect coordinates. In one embodiment, composite image 905 is an IR composite image of the type discussed above; however, many other types of images depict subjects of interest surrounded by artifacts of those subjects. Algorithms in accordance with the invention can be used to localize such subjects. For example, images obtained from visual optics and/or nuclear-type experiments depict subjects and subject-artifacts.
[0077] The above-referenced Bovik reference describes a connection between gray-level and binary morphology that is used in some embodiments to distinguish defects from their associated artifacts.--, in [0076]-[0080], and [0100]).
Re Claim 7, KIM as modified by BENDJUS and Enachescu further disclose wherein the step of determining whether the target semiconductor is defective further includes: compared with the image of the first surface or the second surface of the standard semiconductor, the inspection unit detecting grayscale of the image of at least one block area of the first surface of the target semiconductor to be darker or grayscale of the image of at least one block area of the second surface of the target semiconductor to be lighter, so as to determine that the target semiconductor to be defective and the defect to be at least one non-conductive wire material to be damaged or erroneous material proportion (see KIM: e.g., --a heater configured to apply heat to a surface of the second semiconductor die on the stage, which is opposite to a bonding interface of the first semiconductor die and the second semiconductor die; and a camera configured to measure a temperature change on the surface of the second semiconductor die to which the heat is applied to check a state of the bonding interface.
[0007] According to embodiments, there is provided a method of manufacturing a semiconductor package using the defect inspection apparatus. The method may include: providing a first semiconductor die on a stage; bonding a second semiconductor die to the first semiconductor die to each other; applying heat to a surface of the second semiconductor die, which is opposite to a bonding interface of the first semiconductor die and the second semiconductor die; and measuring a temperature change on the surface of the second semiconductor die to which the heat is applied to inspect a state of the bonding interface.
[0008] According to embodiments, the inspecting the state of the bonding interface may include determining whether a void exists between the first semiconductor die and the second semiconductor die by the measuring the temperature change.--, in [0006]-[0008]; and,
--[0036] As illustrated in FIGS. 3 and 4, after bonding the upper semiconductor die D3 to the lower semiconductor die D2 by performing each stacking step (e.g., three-layer stacking step), heat may be applied to the upper surface of the upper semiconductor die D3 through the heat source of the heater 30, and the upper surface of the upper semiconductor die D3 may be observed through the thermal imaging camera, to obtain a thermal image representing temperature distribution of upper surface of the upper semiconductor die D3 according to the presence or absence of voids, i.e., air gaps.
--[0037] Heat radiated from the heat source onto the upper surface of the upper semiconductor die D3 may diffuse in a depth direction of the die stack DS. In the process of heat diffusion, a heat transfer path may vary according to the presence or absence of a void at the bonding interface formed in the stacking step. This is because the thermal diffusivity at the void is relatively small compared to the thermal diffusivity at a completely bonded interface. Thus, heat may spread (diffuse) not in a direction where the void exists but bypasses the void. For example, thermal diffusivity of silicon is 0.895 [cm.sup.2/s], and thermal diffusivity of air is 0.213 [cm.sup.2/s]. If a thickness of bonded semiconductor dies is sufficiently thin, a temperature singularity may occur on a surface of the upper semiconductor die D3 irradiated with heat due to the change in the heat transfer path around the void. Accordingly, while the stage 20 moves, the thermal imaging camera may measure a temperature change of the surface of the upper semiconductor die within a region of interest (ROI), and thus, it may be possible to inspect whether a void is generated at the bonding interface in the previous bonding process.
[0038] In example embodiments, the defect inspection apparatus 10 may apply heat in the form of a sinusoidal wave to the upper surface of the upper semiconductor die D3 on the lower semiconductor die D2. As shown in FIGS. 5A to 5C, while the stage 20 reciprocally moves within a preset distance based on a specific position, the heater 30 over the stage 20 may irradiate a light (L) to a specific position on the upper surface of the upper semiconductor die D3. For example, the specific position may be a virtual line passing through a center of the upper semiconductor die D3 in a direction parallel to the Y direction, and the preset distance may be a distance T of a portion of the upper semiconductor die D3.
[0039] Referring to FIG. 6, a graph G1 in a solid-line curve shows heat (power (W)) in the form of a sinusoidal wave applied to both a first upper semiconductor die without a void in a bonding interface of a lower semiconductor die therebelow and a second upper semiconductor die with a void in a bonding surface of a lower semiconductor die therebelow, and a graph G2 in a dashed-line curve is a surface temperature difference (ΔT, ° C.) between a surface temperature (T #1) of the first upper semiconductor die and a surface temperature (T #2) of the second upper semiconductor die in a region of interest (ROI). The temperature difference (ΔT) may be a difference value between a temperature (T #1) in the die without a void and a temperature (T #2) in the die with a void. For example, several semiconductor dies D may be positioned within the region of interest (ROI), and there may be some dies with voids and other dies without voids within the region of interest (ROI). Compared to the die without a void, the die with voids does not spread heat well due to the thermal resistance of the voids, so the temperature (T #2) in the die with a void may increase, which is different from the temperature (T #1) of the die without a void. In other words, the larger the temperature difference, the easier the IR Camera can detect the die with voids. As the stage 20 periodically moves from side to side, the temperature difference appearing on the surface of the upper semiconductor dies shows a specific cycle because the heat source entering vicinity of the void does not reach a steady state and is in a transient state. At this time, if a position where the temperature difference is the largest is extracted, void inspection can be effectively performed.--, in [0036]-[0039]; also see BENDJUS: e.g., Fig. 1, and, -- the LSP method can also be used to detect the connection defects of both surfaces of the substrate, i.e. the semiconductor element surface and the free ceramic substrate surface. For some substrate structures with thin metallization layers, due to the high transmission of the ceramic (e.g. AI2O3 and AIN), an additional second optical measurement setup with white light illumination (or infrared illumination) can also be used for measurements from the back of the substrate in order to detect the connection errors from the ceramic side of a To recognize substrate on which no semiconductor element is present. With the help of image processing methods, the connection errors open to the ceramic layer can also be recognized from the static white light images. A prerequisite for the latter is an exposed ceramic substrate.-- ,in page 5/33 of including the English translation version of WO 2023017029 A1 {as provided as NPL with this Office Action}, and, -- FIG. 1 shows a measurement system for carrying out an LSP,… a digital camera as an optical sensor 4, which in this example is combined with a lens 5, and a thermal excitation source 6 in the form of a lasers. The illumination laser device 2 emits laser beams, which are irradiated through the optical lens system 3 and impinge on the surface of a semiconductor element 1a to illuminate the same…. The first measuring module can be aligned either with the surface of the semiconductor element 1a or with the surface of the substrate 1c. The second measurement module is an additional measurement setup with a circular LED module 9 and a digital camera 7, which is combined with a lens 8.--, in pages 6-7/33 of including the English translation version of WO 2023017029 A1 {as provided as NPL with this Office Action; and “compared with the results obtained in advance for defect-free and defect-afflicted similar material connections in order to decide whether specified quality criteria of the tested material connection have been achieved or not.”, in claim 1}, further see ENACHESCU: e.g., -- Described are methods and systems for providing improved defect detection and analysis using infrared thermography. Test vectors heat features of a device under test to produce thermal characteristics useful in identifying defects. The test vectors are timed to enhance the thermal contrast between defects and the surrounding features, enabling IR imaging equipment to acquire improved thermographic images. In some embodiments, a combination of AC and DC test vectors maximize power transfer to expedite heating, and therefore testing. Mathematical transformations applied to the improved images further enhance defect detection and analysis. Some defects produce image artifacts, or "defect artifacts," that obscure the defects, rendering difficult the task of defect location. Some embodiments employ defect-location algorithms that analyze defect artifacts to precisely locate corresponding defects.--, in abstract, Fig. 9, and, -- Subsequent processing automatically locates the defect data within the defect artifacts to produce a list of defect coordinates. In one embodiment, composite image 905 is an IR composite image of the type discussed above; however, many other types of images depict subjects of interest surrounded by artifacts of those subjects. Algorithms in accordance with the invention can be used to localize such subjects. For example, images obtained from visual optics and/or nuclear-type experiments depict subjects and subject-artifacts.
[0077] The above-referenced Bovik reference describes a connection between gray-level and binary morphology that is used in some embodiments to distinguish defects from their associated artifacts.--, in [0076]-[0080], and [0100]).
Re Claim 8, KIM as modified by BENDJUS and Enachescu further disclose wherein the step of sensing temperatures of part or all of the first surface of the target semiconductor or temperatures of part or all of the second surface of the target semiconductor by the thermal imager further includes: the thermal imager continuously capturing the image of part or all of the first surface of the target semiconductor or the image of part or all of the second surface of the target semiconductor to sense a temperature change of part or all of the first surface of the target semiconductor or a temperature change of part or all of the second surface of the target semiconductor (see KIM: e.g., --a heater configured to apply heat to a surface of the second semiconductor die on the stage, which is opposite to a bonding interface of the first semiconductor die and the second semiconductor die; and a camera configured to measure a temperature change on the surface of the second semiconductor die to which the heat is applied to check a state of the bonding interface.
[0007] According to embodiments, there is provided a method of manufacturing a semiconductor package using the defect inspection apparatus. The method may include: providing a first semiconductor die on a stage; bonding a second semiconductor die to the first semiconductor die to each other; applying heat to a surface of the second semiconductor die, which is opposite to a bonding interface of the first semiconductor die and the second semiconductor die; and measuring a temperature change on the surface of the second semiconductor die to which the heat is applied to inspect a state of the bonding interface.
[0008] According to embodiments, the inspecting the state of the bonding interface may include determining whether a void exists between the first semiconductor die and the second semiconductor die by the measuring the temperature change.--, in [0006]-[0008]; and,
--[0036] As illustrated in FIGS. 3 and 4, after bonding the upper semiconductor die D3 to the lower semiconductor die D2 by performing each stacking step (e.g., three-layer stacking step), heat may be applied to the upper surface of the upper semiconductor die D3 through the heat source of the heater 30, and the upper surface of the upper semiconductor die D3 may be observed through the thermal imaging camera, to obtain a thermal image representing temperature distribution of upper surface of the upper semiconductor die D3 according to the presence or absence of voids, i.e., air gaps.
--[0037] Heat radiated from the heat source onto the upper surface of the upper semiconductor die D3 may diffuse in a depth direction of the die stack DS. In the process of heat diffusion, a heat transfer path may vary according to the presence or absence of a void at the bonding interface formed in the stacking step. This is because the thermal diffusivity at the void is relatively small compared to the thermal diffusivity at a completely bonded interface. Thus, heat may spread (diffuse) not in a direction where the void exists but bypasses the void. For example, thermal diffusivity of silicon is 0.895 [cm.sup.2/s], and thermal diffusivity of air is 0.213 [cm.sup.2/s]. If a thickness of bonded semiconductor dies is sufficiently thin, a temperature singularity may occur on a surface of the upper semiconductor die D3 irradiated with heat due to the change in the heat transfer path around the void. Accordingly, while the stage 20 moves, the thermal imaging camera may measure a temperature change of the surface of the upper semiconductor die within a region of interest (ROI), and thus, it may be possible to inspect whether a void is generated at the bonding interface in the previous bonding process.
[0038] In example embodiments, the defect inspection apparatus 10 may apply heat in the form of a sinusoidal wave to the upper surface of the upper semiconductor die D3 on the lower semiconductor die D2. As shown in FIGS. 5A to 5C, while the stage 20 reciprocally moves within a preset distance based on a specific position, the heater 30 over the stage 20 may irradiate a light (L) to a specific position on the upper surface of the upper semiconductor die D3. For example, the specific position may be a virtual line passing through a center of the upper semiconductor die D3 in a direction parallel to the Y direction, and the preset distance may be a distance T of a portion of the upper semiconductor die D3.
[0039] Referring to FIG. 6, a graph G1 in a solid-line curve shows heat (power (W)) in the form of a sinusoidal wave applied to both a first upper semiconductor die without a void in a bonding interface of a lower semiconductor die therebelow and a second upper semiconductor die with a void in a bonding surface of a lower semiconductor die therebelow, and a graph G2 in a dashed-line curve is a surface temperature difference (ΔT, ° C.) between a surface temperature (T #1) of the first upper semiconductor die and a surface temperature (T #2) of the second upper semiconductor die in a region of interest (ROI). The temperature difference (ΔT) may be a difference value between a temperature (T #1) in the die without a void and a temperature (T #2) in the die with a void. For example, several semiconductor dies D may be positioned within the region of interest (ROI), and there may be some dies with voids and other dies without voids within the region of interest (ROI). Compared to the die without a void, the die with voids does not spread heat well due to the thermal resistance of the voids, so the temperature (T #2) in the die with a void may increase, which is different from the temperature (T #1) of the die without a void. In other words, the larger the temperature difference, the easier the IR Camera can detect the die with voids. As the stage 20 periodically moves from side to side, the temperature difference appearing on the surface of the upper semiconductor dies shows a specific cycle because the heat source entering vicinity of the void does not reach a steady state and is in a transient state. At this time, if a position where the temperature difference is the largest is extracted, void inspection can be effectively performed.--, in [0036]-[0039]; also see BENDJUS: e.g., Fig. 1, and, -- the LSP method can also be used to detect the connection defects of both surfaces of the substrate, i.e. the semiconductor element surface and the free ceramic substrate surface. For some substrate structures with thin metallization layers, due to the high transmission of the ceramic (e.g. AI2O3 and AIN), an additional second optical measurement setup with white light illumination (or infrared illumination) can also be used for measurements from the back of the substrate in order to detect the connection errors from the ceramic side of a To recognize substrate on which no semiconductor element is present. With the help of image processing methods, the connection errors open to the ceramic layer can also be recognized from the static white light images. A prerequisite for the latter is an exposed ceramic substrate.-- ,in page 5/33 of including the English translation version of WO 2023017029 A1 {as provided as NPL with this Office Action}, and, -- FIG. 1 shows a measurement system for carrying out an LSP,… a digital camera as an optical sensor 4, which in this example is combined with a lens 5, and a thermal excitation source 6 in the form of a lasers. The illumination laser device 2 emits laser beams, which are irradiated through the optical lens system 3 and impinge on the surface of a semiconductor element 1a to illuminate the same…. The first measuring module can be aligned either with the surface of the semiconductor element 1a or with the surface of the substrate 1c. The second measurement module is an additional measurement setup with a circular LED module 9 and a digital camera 7, which is combined with a lens 8.--, in pages 6-7/33 of including the English translation version of WO 2023017029 A1 {as provided as NPL with this Office Action; and “compared with the results obtained in advance for defect-free and defect-afflicted similar material connections in order to decide whether specified quality criteria of the tested material connection have been achieved or not.”, in claim 1}).
Re Claim 9, KIM as modified by BENDJUS and Enachescu further disclose wherein the heat source applies heat for less than 0.1 second at a temperature greater than 50°C (see KIM: e.g., --a heater configured to apply heat to a surface of the second semiconductor die on the stage, which is opposite to a bonding interface of the first semiconductor die and the second semiconductor die; and a camera configured to measure a temperature change on the surface of the second semiconductor die to which the heat is applied to check a state of the bonding interface.
[0007] According to embodiments, there is provided a method of manufacturing a semiconductor package using the defect inspection apparatus. The method may include: providing a first semiconductor die on a stage; bonding a second semiconductor die to the first semiconductor die to each other; applying heat to a surface of the second semiconductor die, which is opposite to a bonding interface of the first semiconductor die and the second semiconductor die; and measuring a temperature change on the surface of the second semiconductor die to which the heat is applied to inspect a state of the bonding interface.
[0008] According to embodiments, the inspecting the state of the bonding interface may include determining whether a void exists between the first semiconductor die and the second semiconductor die by the measuring the temperature change.--, in [0006]-[0008]; and,
--[0036] As illustrated in FIGS. 3 and 4, after bonding the upper semiconductor die D3 to the lower semiconductor die D2 by performing each stacking step (e.g., three-layer stacking step), heat may be applied to the upper surface of the upper semiconductor die D3 through the heat source of the heater 30, and the upper surface of the upper semiconductor die D3 may be observed through the thermal imaging camera, to obtain a thermal image representing temperature distribution of upper surface of the upper semiconductor die D3 according to the presence or absence of voids, i.e., air gaps.
--[0037] Heat radiated from the heat source onto the upper surface of the upper semiconductor die D3 may diffuse in a depth direction of the die stack DS. In the process of heat diffusion, a heat transfer path may vary according to the presence or absence of a void at the bonding interface formed in the stacking step. This is because the thermal diffusivity at the void is relatively small compared to the thermal diffusivity at a completely bonded interface. Thus, heat may spread (diffuse) not in a direction where the void exists but bypasses the void. For example, thermal diffusivity of silicon is 0.895 [cm.sup.2/s], and thermal diffusivity of air is 0.213 [cm.sup.2/s]. If a thickness of bonded semiconductor dies is sufficiently thin, a temperature singularity may occur on a surface of the upper semiconductor die D3 irradiated with heat due to the change in the heat transfer path around the void. Accordingly, while the stage 20 moves, the thermal imaging camera may measure a temperature change of the surface of the upper semiconductor die within a region of interest (ROI), and thus, it may be possible to inspect whether a void is generated at the bonding interface in the previous bonding process.
[0038] In example embodiments, the defect inspection apparatus 10 may apply heat in the form of a sinusoidal wave to the upper surface of the upper semiconductor die D3 on the lower semiconductor die D2. As shown in FIGS. 5A to 5C, while the stage 20 reciprocally moves within a preset distance based on a specific position, the heater 30 over the stage 20 may irradiate a light (L) to a specific position on the upper surface of the upper semiconductor die D3. For example, the specific position may be a virtual line passing through a center of the upper semiconductor die D3 in a direction parallel to the Y direction, and the preset distance may be a distance T of a portion of the upper semiconductor die D3.
[0039] Referring to FIG. 6, a graph G1 in a solid-line curve shows heat (power (W)) in the form of a sinusoidal wave applied to both a first upper semiconductor die without a void in a bonding interface of a lower semiconductor die therebelow and a second upper semiconductor die with a void in a bonding surface of a lower semiconductor die therebelow, and a graph G2 in a dashed-line curve is a surface temperature difference (ΔT, ° C.) between a surface temperature (T #1) of the first upper semiconductor die and a surface temperature (T #2) of the second upper semiconductor die in a region of interest (ROI). The temperature difference (ΔT) may be a difference value between a temperature (T #1) in the die without a void and a temperature (T #2) in the die with a void. For example, several semiconductor dies D may be positioned within the region of interest (ROI), and there may be some dies with voids and other dies without voids within the region of interest (ROI). Compared to the die without a void, the die with voids does not spread heat well due to the thermal resistance of the voids, so the temperature (T #2) in the die with a void may increase, which is different from the temperature (T #1) of the die without a void. In other words, the larger the temperature difference, the easier the IR Camera can detect the die with voids. As the stage 20 periodically moves from side to side, the temperature difference appearing on the surface of the upper semiconductor dies shows a specific cycle because the heat source entering vicinity of the void does not reach a steady state and is in a transient state. At this time, if a position where the temperature difference is the largest is extracted, void inspection can be effectively performed.--, in [0036]-[0039]; also see BENDJUS: e.g., Fig. 1, and, -- the LSP method can also be used to detect the connection defects of both surfaces of the substrate, i.e. the semiconductor element surface and the free ceramic substrate surface. For some substrate structures with thin metallization layers, due to the high transmission of the ceramic (e.g. AI2O3 and AIN), an additional second optical measurement setup with white light illumination (or infrared illumination) can also be used for measurements from the back of the substrate in order to detect the connection errors from the ceramic side of a To recognize substrate on which no semiconductor element is present. With the help of image processing methods, the connection errors open to the ceramic layer can also be recognized from the static white light images. A prerequisite for the latter is an exposed ceramic substrate.-- ,in page 5/33 of including the English translation version of WO 2023017029 A1 {as provided as NPL with this Office Action}, and, -- FIG. 1 shows a measurement system for carrying out an LSP,… a digital camera as an optical sensor 4, which in this example is combined with a lens 5, and a thermal excitation source 6 in the form of a lasers. The illumination laser device 2 emits laser beams, which are irradiated through the optical lens system 3 and impinge on the surface of a semiconductor element 1a to illuminate the same…. The first measuring module can be aligned either with the surface of the semiconductor element 1a or with the surface of the substrate 1c. The second measurement module is an additional measurement setup with a circular LED module 9 and a digital camera 7, which is combined with a lens 8.--, in pages 6-7/33 of including the English translation version of WO 2023017029 A1 {as provided as NPL with this Office Action; and “compared with the results obtained in advance for defect-free and defect-afflicted similar material connections in order to decide whether specified quality criteria of the tested material connection have been achieved or not.”, in claim 1}).
Re Claim 10, KIM as modified by BENDJUS and Enachescu further disclose wherein the heat source is a surface light source or a point light source (see KIM: e.g., Fig. 1, reproduced below:
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and see: “measuring a temperature change on the surface of the second semiconductor die to which the heat is applied to inspect a state of the bonding interface.” In abstract, and, “the embodiments relate to an apparatus for inspecting defects in a semiconductor package” in [0002], and [0004]-[0005]; and,
--FIG. 4 represents a thermal image obtained by a thermal imaging camera capturing a portion ‘A’ of FIG. 2, and a graph illustrating temperature distribution across a specific area of the thermal image,…
FIG. 6 is a graph showing a difference in die surface temperature according to presence or absence of a void in a region of interest obtained according to the heating method of FIGS. 5A to 5C, in accordance with embodiments.
[0028] Referring to FIGS. 1 to 6, a defect inspection apparatus for a semiconductor package 10 may include a stage 20, a heater 30 and a camera 40. In addition, the defect inspection apparatus 10 may further include a controller 50 connected to the stage 20, the heater 30 and the camera 40 to control their operations.--, in [0027]-[0028]).
Conclusion
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/WEI WEN YANG/Primary Examiner, Art Unit 2662