DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on 02/27/2026 has been entered and considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 5, 6, and 8-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (U.S. Pub. No. 2015/0325213) in view of Kim (U.S. Pub. No. 2023/0316993).
As to claim 1, Lee teaches an electronic device (display device 10), comprising:
a display controller (200), comprising an interface (210), wherein the display controller provides a synchronization signal through the interface (the display controller 200 provides synch signals HS and VS via the interface as can be seen in Fig. 3);
a multiplexer (selection unit 220 has at least one multiplexer shown in Fig. 4); and
a processor (processor 100 and signal MCC processing the components of the display driver integrated driver 200), wherein when the processor needs to reduce power consumption of the display controller (the processor 100 is connected to the display driver integrated circuit 200 and therefore controlling this unit, [0052], lines 1-4), the processor controls the multiplexer to output the clock signal as the output signal (the processor comprising of element 100 outputs signals to the unit 200 and the processor selection signal MCC controls the selection of the signals in unit 200, [0053], lines 7-12).
The prior art reference of Lee teaches a clock signal CLK but does not teach a clock generator and outputting one of the synchronization or clock signals.
Kim teaches a clock generator (268), generating a clock signal ([0139], lines 7-8);
a multiplexer (266) outputting either the synchronization signal or the clock signal as an output signal (as can be seen in Fig. 14, either the clock signal or the Vsync is outputted to unit 261, [0150], lines 1-6);
Therefore, it would have been obvious to one of ordinary skilled in the art at the time the invention was filed to have added the clock generator and multiplexer components of Kim to the electronic device of Lee because a precision of LED driving may be improved through hybrid scheme LED driving in which PWM driving and PAM driving are distinguished based on reference current, PWM single driving, or PAM single driving, and noise generated in an LED driving process may be reduced.
As to claim 2, Lee teaches the output signal (the output signal, which could be a clock signal via the multiplexer inside the selection unit 220) is provided to a display driver integrated circuit (the selection unit 220 is a part of the display driver integrated circuit, therefore the output from the multiplexer MUX1 is provided to a component 230 of the display driver integrated circuit as shown in figures 3 and 4); wherein the display driver integrated circuit is configured to drive a display panel (Figure 1 shows the output of the display driver integrated circuit is ultimately outputted to the display panel 500).
As to claim 5, Lee teaches the processor (100 and selection signal MCC) needs to reduce the power consumption of the display controller ([0053], line 7-12), the display controller operates in a deactivated mode to reduce the power consumption (the deactivated mode is when the display is displaying the time, [0053], lines 3-7); wherein when the display controller is in the deactivated mode (displaying the time),
The prior art reference of Lee does not mention outputting the synchronization signal or the clock signal.
Kim teaches the display controller stops generating the synchronization signal (the multiplexer 266 outputs either a vertical synchronization signal or an internal clock signal).
Therefore, it would have been obvious to one of ordinary skilled in the art at the time the invention was filed to have added the clock generator and multiplexer components of Kim to the electronic device of Lee because a precision of LED driving may be improved through hybrid scheme LED driving in which PWM driving and PAM driving are distinguished based on reference current, PWM single driving, or PAM single driving, and noise generated in an LED driving process may be reduced.
As to claim 6, Lee teaches the display controller (200), the clock generator (although not shown, but the DT signal inputted into the selection unit 220, Fig. 3), the multiplexer (multiplexer MUX1 to MUX3 inside the selection unit 220), and the processor (processor 100 and selection signal MCC) are integrated in a package (as can be seen in Fig. 1, these units are all a part of the display device 10).
Lee does not mention a clock generator,
Kim teaches a clock generator (268, generating a clock signal [0139], lines 7-8).
Therefore, it would have been obvious to one of ordinary skilled in the art at the time the invention was filed to have added the clock generator and multiplexer components of Kim to the electronic device of Lee because a precision of LED driving may be improved through hybrid scheme LED driving in which PWM driving and PAM driving are distinguished based on reference current, PWM single driving, or PAM single driving, and noise generated in an LED driving process may be reduced.
As to claim 8, Lee teaches the synchronization signal is a horizontal synchronization signal (the data packet DP may include the image data and a horizontal synchronization signal, [0051].
As to claim 9, Lee teaches the interface is a mobile industry processor interface ([0054]).
As to claim 10, Lee teaches when the processor needs to reduce the power consumption of the display controller (selecting the MCC signal to output the DT signal, [0053], lines 7-12), the processor operates in an Always On Display (AOD) mode or a Home Screen Idle mode (the display of time on the screen can be interpreted as both always on display, which the display is displaying a time or a home screen idle mode, which it is not displaying anything other than a time, [0053], lines 3-7).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (U.S. Pub. No. 2015/0325213) in view of Kim (U.S. Pub. No. 2023/0316993), and further in view of Wang (U.S. 2012/0300211).
As to claim 7, Lee and Kim teach all of the limitations of claim 1, wherein Lee teaches a display controller 200 and a processor 100 and signal selection MCC that are all a part of display device 10 package.
Lee and Kim do not teach the clock generator and the package are integrated on a PCB.
Wang teaches the display controller (Fig. 3, 29) and the processor (27) are integrated in a package (the two components of 27 and 29 are a part of a package), and the clock generator (26) and the package (package of the controller 29 and processor 27) are integrated on a PCB ([0019]).
Therefore, it would have been obvious to one of ordinary skilled in the art at the time the invention was filed to have added the PCB of Wang to the display controller 200 of Lee as modified by Kim because the PCB can form circuits that can function as timing generator, a driver, and a signal processor, [0019].
Response to Arguments
Applicant's arguments filed 02/27/2026 have been fully considered but they are not persuasive.
Applicant on page 8 of the remarks argues that Lee and Kim fail to disclose that “a multiplexer outputs either the synchronization signal or the clock signal as an output signal, and that when the processor needs to reduce power consumption of the display controller, the processor controls the multiplexer to output the clock signal as the output signal.”
Applicant further argues and disagrees that the office action analogizes synch signals HS and VS of Lee to the synchronization signal of the invention and the selection unit 220 in Figs. 3 and 4 to the multiplexer. Applicant further illustrates the multiplexers shown in Fig. 4 and the teachings in paragraphs [0075] and [0076]. Wherein the multiplexers do not disclose a multiplexer outputting either the synchronization signal or the clock signal as an output signal” as recited in claim 1.
Examiner would like to point out that the prior art reference of Lee teaches the electronic device, which is the display device 10 has s display controller that comprises a multiplexer as shown in Fig. 4, since at least one of the multiplexers can output the synchronization signals HS and VS, therefore this multiplexer of Lee reads on the limitation of “a multiplexer” as recited in claim 1.
Applicant on page 10 of the remarks argues that the office action analogizes the display driver integrated circuit 200 of Lee to the display controller of the invention, and alleges that paragraphs [0052] and [0053] of Lee have disclosed the limitation of “when the processor needs to reduce power consumption of the display controller, the processor controls the multiplexer to output the clock signal as the output signal” as recited in claim 1. Applicant further argues that paragraphs [0052] and [0053] of Lee are silent on the feature of “reducing the power consumption of the display driver integrated circuit 200 and Lee fails to disclose the limitation of “a multiplexer, outputting either the synchronization signal or the clock signal as an output signal” as recited in claim 1.
Examiner would like to point out that the prior art reference of Lee in paragraph [0053] clearly teaches the reduction in power during the self-clock display mode as “the DDI 200, in the self-clock display mode, may reduce power consumption by calculating internally the time to be displayed and outputting the time to be displayed to the display panel 500 as the display data DDTA without interfacing with the application processor 100.” The multiplexer 221 can output a clock signal DT and the multiplexer 225 can output a synchronization signal. Therefore, a clock signal is outputted when the power reduction is performed and the multiplexers of Lee read on the multiplexer of the recited claim 1.
Applicant on page 11 argues that the multiplexer in Fig. 14 of Kim wherein paragraph [0151] of Kim states “the multiplexer 266 which determines the type of signal supplied to the digital logical operation circuit 261 may select the PWM clock signal supplied externally or the PWM clock signal supplied internally.” This indicates that Kim is silent on the limitation of “a multiplexer, outputting either the synchronization signal or the clock signal as an output signal” as recited in claim 1.
Examiner respectfully disagrees because the prior art reference of Kim is to teach a single multiplexer has two inputs of a synchronization signal and a clock signal as illustrated in Fig. 14, rather than having three multiplexers as illustrated in Fig. 4 of Lee. The multiplexer of Kim is arranged in a display controller, therefore, the multiplexer of Kim may be added to the display controller of Lee or replace a multiplexer of Lee. The prior art reference of Lee also outputs either a clock signal or a synchronization signal by the multiplexers of one of the elements of the display controller 220.
Therefore, the combination of the prior art references of Lee and Kim teach all of the limitations of claim 1.
Allowable Subject Matter
Claims 11-14 and 16-20 are allowed.
Claims 3 and 4 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 3 is objected to because the prior art references do not teach the mode in which when the processor does not need to reduce the power consumption of the display controller, the processor controls the multiplexer to output the synchronization signal as the output signal; wherein the synchronization signal generated by the display controller synchronizes the display controller with the display driver integrated circuit.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Inquiry
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PEGEMAN KARIMI whose telephone number is (571)270-1712. The examiner can normally be reached Monday-Friday; 9:00am-4:00pm EST.
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/PEGEMAN KARIMI/Primary Examiner, Art Unit 2623