DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-24 and 25 in the reply filed on 06/09/2026 is acknowledged.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claims 12 and 13 are objected to because of the following informalities:
12. The device according to claim 1, wherein a plurality of wiring layers including a wiring layer where the wiring pattern is arranged
13. The device according to claim 1, wherein a plurality of wiring layers including a wiring layer where the wiring pattern is arranged
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 5-8, 12, 14 and 25 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kobayashi US 2013/0105667.
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Kobayashi US 2013/0105667
Regarding claim 1, Kobayashi in [0037]-[0136] and Figs. 1A-9B discloses a semiconductor device comprising:
a substrate 101 [0086] 404 [0119];
a pad 313 [0044] Fig. 9A used to connect an external terminal;
an interlayer insulating film 124-127 [0119], which is arranged between a main surface of the substrate 101, 404 and the pad 313 and where a wiring pattern 322 is arranged; and
an insulating film 104 [0113] Figs. 4 and 9A arranged so as to cover a peripheral portion of the pad 313, wherein
an opening portion 100 [0044] configured to connect the pad 313 to the external terminal is provided in the insulating film 104,
the pad 313 and the wiring pattern 322 are electrically connected via a plug 110, Fig. 4 [0079] and in contact with both the pad 313 and the wiring pattern 322, and
in an orthogonal projection with respect to the main surface, the plug 110 is arranged outside the opening portion 100.
Regarding claim 2, Kobayashi in [0037]-[0136] and Figs. 1A-9B discloses the device according to claim 1, wherein the plug 110 is in contact with the pad 313 in the peripheral portion.
Regarding claim 3, Kobayashi in [0037]-[0136] and Figs. 1A-9B discloses the device according to claim 1, wherein the pad 313 (e.g. aluminum) and the wiring pattern 322 (e.g. copper) contain materials different from each other [0115].
Regarding claim 5, Kobayashi in [0037]-[0136] and Figs. 1A-9B discloses the device according to claim 1, wherein the pad 313 (e.g. aluminum) and the plug 110 (e.g. tungsten or copper) contain materials different from each other [0114].
Regarding claim 6, Kobayashi in [0037]-[0136] and Figs. 1A-9B discloses the device according to claim 1, wherein the plug 110 (e.g. tungsten) contains a refractory metal [0114].
Regarding claim 7, Kobayashi in [0037]-[0136] and Figs. 1A-9B discloses the device according to claim 1, wherein the interlayer insulating film is formed by a plurality of interlayer insulating layers stacked on each other, and among the plurality of interlayer insulating layers, interlayer insulating layers arranged between the pad and the wiring pattern include at least two interlayer insulating layers 124 [0119] and 106 [0079] containing materials different from each other.
Regarding claim 8, Kobayashi in [0037]-[0136] and Figs. 1A-9B discloses the device according to claim 7, wherein the plurality of interlayer insulating layers include an interlayer insulating layer having a lower dielectric constant than silicon oxide [0113],[0119] (e.g. organic resin films).
Regarding claim 12, Kobayashi in [0037]-[0136] and Figs. 1A-9B discloses the device according to claim 1, wherein a plurality of wiring layers including a wiring layer where the wiring pattern is arranged are arranged in the interlayer insulating film, and the wiring pattern is arranged in the wiring layer closest to the pad among the plurality of wiring layers.
Regarding claim 14, Kobayashi in [0037]-[0136] and Figs. 1A-9B discloses the device according to claim 1, wherein the insulating film is formed by a plurality of insulating layers stacked on each other, and the plurality of insulating layers include insulating layers containing materials different from each other.
Regarding claim 25, Kobayashi in [0037]-[0136] and Figs. 1A-9B discloses method of manufacturing a semiconductor device comprising:
a substrate 101 [0086] 404 [0119];
a pad 313 [0044] Fig. 9A used to connect an external terminal;
an interlayer insulating film 104-106 [0079], 124-127 [0119], which is arranged between a main surface of the substrate 101, 404 and the pad 313 and where a wiring pattern 322 is arranged; and
an insulating film 104 [0113] Figs. 4 and 9A arranged so as to cover a peripheral portion of the pad 313, wherein
an opening portion 100 [0044] configured to connect the pad 313 to the external terminal is provided in the insulating film 104,
the pad 313 and the wiring pattern 322 are electrically connected via a plug 110, Fig. 4 [0079] and in contact with both the pad 313 and the wiring pattern 322, and
in an orthogonal projection with respect to the main surface, the plug 110 is arranged outside the opening portion 100.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kobayashi US 2013/0105667.
Regarding claim 4, Kobayashi in [0037]-[0136] and Figs. 1A-9B discloses the device according to claim 1, but does not expressly disclose wherein a thickness of the pad is smaller than a thickness of the wiring pattern.
Notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization. Applicant has not disclosed that the relative dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, Jn re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). See also MPEP 2144.04(1V)(B).
Regarding claim 13, Kobayashi in [0037]-[0136] and Figs. 1A-9B discloses the device according to claim 1, wherein a plurality of wiring layers including a wiring layer where the wiring pattern is arranged in the interlayer insulating film, the wiring pattern is set as a first wiring pattern, and the plug is set as a first plug, the plurality of wiring layers include a first wiring layer where the first wiring pattern is arranged, and a second wiring layer which is arranged between the first wiring layer and the main surface and where a second wiring pattern is arranged, the first wiring pattern and the second wiring pattern are electrically connected via a second plug in contact with both the first wiring pattern and the second wiring pattern but does not expressly disclose the first plug is thinner than the second plug.
Notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization. Applicant has not disclosed that the relative dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, Jn re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). See also MPEP 2144.04(1V)(B).
Claim(s) 9 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kobayashi US 2013/0105667 as applied to claim 1 above, and further in view of Ohchi US 2019/0319221.
Regarding claim 9, Kobayashi in [0037]-[0136] and Figs. 1A-9B discloses the device according to claim 1 but does not disclose wherein the pad is electrically connected to the external terminal via a conductive film arranged in the opening portion.
Ohchi in Fig. 7 and [0064]-[0129] teach a pad 103 [0064] is electrically connected to an external terminal 900 via a conductive film 120 arranged in the opening portion [0064].
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Ohchi in the device of Kobayashi for the purpose of electrically connecting the circuit substrate and the OELD panel.
Regarding claim 11, Kobayashi in view of Ohchi teach the device according to claim 9. Ohchi in Figs. 1-6 teach wherein in the orthogonal projection with respect to the main surface, the conductive film 120 includes a portion in contact with an insulating film 320 outside the opening portion.
Claim(s) 15-23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kobayashi US 2013/0105667 as applied to claims 1 and 14 above, and further in view of Nakamura et al. US 2014/0117334.
Regarding claim 15, Kobayashi in [0037]-[0136] and Figs. 1A-9B discloses the device according to claim 1 but does not expressly disclose the device of claim 1, further comprising a plurality of pixels each including a light emitting layer arranged on the main surface.
Nakamura et al. in Figs. 1-11B [0067]-[0143] teach an semiconductor device including a connection terminal and an organic EL device 200. The organic EL device 200 including a plurality of pixels 18R, 18G, 18B with light emitting layer 32 [0070] arranged on a main surface.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have an OLED such as Nakamura et al. in the device of Kobayashi for the purpose of forming a top emission type device.
Regarding claim 16, Kobayashi in [0037]-[0136] and Figs. 1A-9B discloses the device according to claim 1 but does not expressly disclose the device of claim 1, further comprising a plurality of pixels each including a light emitting layer arranged on the main surface, wherein each of the plurality of pixels is covered with at least one insulating layer of the plurality of insulating layers.
Nakamura et al. in Figs. 1-11B [0067]-[0143] teach an semiconductor device including a connection terminal and an organic EL device 200. The organic EL device 200 including a plurality of pixels 18R, 18G, 18B with light emitting layer 32 [0070] on a main surface of the substrate 11 [0089] covered with at least one insulating layer 26 [0094] of a plurality of insulating layers.
Regarding claim 17, Kobayashi in view of Nakamura et al. teach the device according to claim 16. Nakamura et al. in Fig. 11B teach wherein each of the plurality of pixels 18R, 18G, 18B is covered with an insulating layer 26 farthest from the main surface among the plurality of insulating layers.
Regarding claim 18, Kobayashi in view of Nakamura et al. teach the device according to claim 16. Nakamura et al. in Fig. 11B teach wherein each of the plurality of pixels 18R, 18G, 18B includes a reflection layer 25 [0091] arranged between the light emitting layer 32 and the main surface, the plurality of insulating layers include an optical adjustment layer 31 [0070] arranged between the reflection layer 25 and the light emitting layer 32 in each of the plurality of pixels 18R, 18G, 18B, and the plurality of pixels include a first pixel 18R and a second pixel 18B different from each other but do not expressly teach in a thickness of the optical adjustment layer.
Notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization. Applicant has not disclosed that the relative dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, Jn re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). See also MPEP 2144.04(1V)(B).
Regarding claim 19, Kobayashi in view of Nakamura et al. teach the device according to claim 16. Nakamura et al. in Fig. 11B teach wherein the reflection layer 25 [0091] is a conductive pattern arranged in the same wiring layer 103 [0109] as the pad 101.
Regarding claim 20, Kobayashi in view of Nakamura et al. teach the device according to claim 16. Nakamura et al. in Fig. 11B teach display device comprising the semiconductor device according to claim 15, and an active element 21 and 23 [0070]-[0074] connected to the semiconductor device Fig. 1.
Regarding claim 21, Kobayashi in view of Nakamura et al. teach the device according to claim 16. Kobayashi in [0082]-[0083] and Nakamura et al. in Figs. 1-11B [0067]-[0143] teach a photoelectric conversion device comprising an optical unit including a plurality of lenses, an image sensor configured to receive light having passed through the optical unit, and a display unit configured to display an image, wherein the display unit displays an image captured by the image sensor, and includes the semiconductor device according to claim 15.
Regarding claim 22, Kobayashi in view of Nakamura et al. teach the device according to claim 16. Nakamura et al. in Fig. 18 teach an electronic apparatus comprising a housing provided with a display unit, and a communication unit provided in the housing and configured to perform external communication, wherein the display unit includes the semiconductor device according to claim 15.
Regarding claim 23, Kobayashi in view of Nakamura et al. teach the device according to claim 16. Nakamura et al. in Fig. 11B teach an illumination device comprising a light source, and at least one of a light diffusing unit and an optical film, wherein the light source includes the semiconductor device according to claim 15.
Claim(s) 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kobayashi US 2013/0105667 in view of Nakamura et al. US 2014/0117334 as applied to claim 15 above, and further in view of Kim et al. US 2022/0306012.
Regarding claim 24, Kobayashi in view of Nakamura et al. teach the semiconductor device according to claim 15 including a display device but do not expressly teach a moving body comprising a main body, and a lighting appliance provided in the main body.
Kim et al. teach a vehicle including a display panel. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to try a vehicle using the display device of Kobayashi and Nakamura et al., as the court has held that choosing from a finite number of identified, predictable solutions, with a reasonable expectation of success is prima facie obvious. KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Allowable Subject Matter
Claim 10 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art neither anticipates nor renders obvious, in the context of the claims, wherein in the orthogonal projection with respect to the main surface, the external terminal includes a portion overlapping the plug.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SONYA D MCCALL-SHEPARD whose telephone number is (571)272-9801. The examiner can normally be reached M-F: 8:30 AM-5:00 PM.
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/Sonya McCall-Shepard/Primary Examiner, Art Unit 2898
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