Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Status
This instant application No. 18/613497 has claims 1-17 pending. The effective filing date of this application is 01/19/2024.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 3, 5, 8, 10 and 12 rejected under 35 U.S.C. 103 as being unpatentable over Sarkar et al (2023/0359466) hereinafter Sarkar in view of Liang et al (2018/0232169) hereinafter Liang.
Regarding claim 1, Sarkar teaches A method for booting a storage device comprising:
receiving first identity information as part of a procedure for establishing a transport connection between the storage device and a host device, the first identity information corresponding to an association of the storage device with the host device (Sarkar: [0028]: “The normal bootup process may include a verification of information retrieved from the memory device 140 during the normal bootup process. In other words, during the normal bootup process, the controller 130 may verify or measure the information against expected values”; [0034]: “The normal bootup process may involve verifying or measuring the information against expected values (e.g., previously stored reference measurements)”);
determining whether the first identity information matches second identity information stored in a memory of the storage device (Sarkar: [0016]: “When the information corresponds to the expected values (e.g., matches or is substantially similar to, within a tolerance threshold), the bootup process may continue”); and
Sarkar does not explicitly teach based on the first identity information matching the second identify information, loading, from a configuration file related to the second identity information stored in the memory of the storage device, configuration data corresponding to one or more configuration operations related to a boot sequence, wherein the boot sequence comprises a plurality of configuration operations for booting the storage device.
However, Liang teaches based on the first identity information matching the second identify information (Liang: [0013]: “The boot data can include, for example, memory pointers (referencing, e.g., memory addresses), memory mappings, data values, and/or other suitable information for readying device operation”; [0026]: “whether the boot data stored in the first region of the memory media 104 is valid”), loading, from a configuration file related to the second identity information stored in the memory of the storage device, configuration data corresponding to one or more configuration operations related to a boot sequence, wherein the boot sequence comprises a plurality of configuration operations for booting the storage device (Liang: [0025]: “the routine 340 can be carried out by the controller 106 (FIG. 1) upon startup of the SSD 102 (FIG. 1), such as to enable a boot up sequence (e.g., a quick boot) using the boot data stored in the memory media 104 (FIG. 1). The routine 340 begins by determining the location of a first region of the memory media 104 that stores the boot data (block 341)”).
Disclosures by Sarkar and Liang are analogous because they are in the same field of endeavor of memory access and control.
It would have been obvious to an ordinary person skilled in the art before the earliest effective filing date of the claimed invention to incorporate verifying the information against expect values during a bootup process of a memory device taught by Sarkar to include determining boot data in a region of a memory device to perform a boot up sequence upon startup of the memory device disclosed by Liang. The motivation for determining boot data to perform a boot up sequence by paragraph [0025] of Liang is for enabling a quick boot using boot data after checking for errors.
Regarding claim 8, these claims limitations are significantly similar to those of claim 1, and, therefore, are rejected on the same grounds.
Regarding claim 3, Sarkar combined further teaches The method as claimed in claim 2, wherein the one or more configuration operations comprise host based configuration operations related to memory allocation, wherein the host based configuration operations comprise one or more of:
configuring an Admin Queue by setting Admin Queue Attributes (AQA), Admin Submission Queue Base Address (ASQ), and Admin Completion Queue Base Address (ACQ) to appropriate values; determining supported Input-Output (I/O) Command Sets by checking a state of Controller capabilities-Command set supported (CAP.CSS) field and initializing Controller Configuration-Command set supported (CC.CSS) field;
configuring settings of a storage device controller comprising selecting arbitration mechanism and initializing a memory page size;
enabling the storage device controller (Sarkar: [0064]: “when the measurements of the boot region correspond to the reference measurements, the controller may allow a bootup (e.g., by sending bootup information to the host device). As shown by reference number 512, when the measurements of the boot region do not correspond to the reference measurements, the controller may perform an error handling and/or stop the bootup of the storage system”);
determining a number of I/O Submission Queues and I/O Completion Queues supported using a Set Features command and configuring one or more Transport specific interrupt registers comprising Message-Signaled Interrupts (MSI) registers and/or Extended Message-Signaled Interrupts (MSI-X) registers;
allocating an appropriate number of I/O Completion Queues based on a number required for system configuration and a number supported by the storage device controller; and
allocating an appropriate number of I/O Submission Queues based on a number required for the system configuration and a number supported by the storage device controller.
Regarding claim 10, these claims limitations are significantly similar to those of claim 3, and, therefore, are rejected on the same grounds.
Regarding claim 5, Liang combined further teaches The method as claimed in claim 1, further comprising:
determining whether the loading of the configuration data corresponding to the one or more configuration operations is successful (Liang: [0026]: “The routine 340 next determines whether the boot data stored in the first region of the memory media 104 is valid”);
based on determining that the loading of the configuration data from the configuration file is successful, setting a success flag in a status register of the storage device (Liang: [0026]: “In particular, the routine 340 reads out at least a portion of the boot data and checks for bit errors. Typically, NAND memory pages include a relatively small number of memory cells dedicated exclusively to error code correction. These memory cells store information that the controller 106 can use to resolve bit errors during read out operations using, e.g., BCH codes, low-density parity-check (LDPC) codes, or other suitable error code correction algorithms. If the data read out passes error code correction, the routine 340 proceeds to initialize the SSD 102 based on the boot data”); and
based on determining that the loading of the configuration data from the configuration file is unsuccessful, setting an error flag in a status register of the storage device (Liang: [0026]: “Otherwise, the routine 340 flags the boot data as invalid”), wherein the error flag notifies the host device to execute each of the plurality of configuration operations of the boot sequence for booting the storage device (Liang: [0025]: “In one embodiment, the routine 340 can be carried out by the controller 106 (FIG. 1) upon startup of the SSD 102 (FIG. 1), such as to enable a boot up sequence (e.g., a quick boot) using the boot data stored in the memory media 104 (FIG. 1). The routine 340 begins by determining the location of a first region of the memory media 104 that stores the boot data”).
Disclosures by Sarkar and Liang are analogous because they are in the same field of endeavor of memory access and control.
It would have been obvious to an ordinary person skilled in the art before the earliest effective filing date of the claimed invention to incorporate verifying the information against expect values during a bootup process of a memory device taught by Sarkar to include setting a flag for the boot data disclosed by Liang. The motivation for setting a flag for the boot data by paragraph [0026] of Liang is for enabling a quick boot using boot data based on the flag.
Regarding claim 12, these claims limitations are significantly similar to those of claim 5, and, therefore, are rejected on the same grounds.
Regarding claim 14, these claims limitations are significantly similar to those of claim 7, and, therefore, are rejected on the same grounds.
Claims 2, 4, 6, 9, 11 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Sarkar et al (2023/0359466) hereinafter Sarkar in view of Liang et al (2018/0232169) hereinafter Liang as applied to claims 1 and 8 respectively above, and further in view of Fai et al (2013/0007347) hereinafter Fai.
Regarding claim 2, the combination of Sarkar and Liang do not teach exactly limitations of claim 2.
However, Fai teaches The method as claimed in claim 1, wherein establishing the transport connection between the storage device and the host device comprises:
determining whether the storage device is paired for a first time with the host device (Fai: [0003]: “Memory devices have been configured to boot from information that is stored locally on the devices. For example, a memory device that includes a memory controller (with one or more processors/microprocessors) can boot using firmware that is stored in NVM of the memory device”);
based on determining that the storage device is paired for the first time with the host device, receiving the second identity information and saving execution results of the one or more configuration operations related to the boot sequence into the configuration file (Fai: [0024]: “The host device 102 can provide the firmware 116-120 to the NVM package 104 from the volatile memory. In other implementations, the firmware 116-120 can be stored in NVM of the host device 102 and read out of NVM of the host device 102 as needed to boot the NVM package 104. The firmware 116-120 can be executed by the NVM package 104 to perform boot operations (e.g., initialize memory dies, load instructions for operating the NVM package 104 into volatile memory) and/or post-boot operations (e.g., read/write/erase operations, debug operations)”); and
storing the configuration file and the second identity information into the memory of the storage device (Fai: [0024]: “The NVM package 104 includes memory 114 (volatile memory and/or NVM) that stores various types of firmware 116-120 that can be provided to the NVM package 104”).
Disclosures by Sarkar, Liang and Fai are analogous because they are in the same field of endeavor of memory access and control.
It would have been obvious to an ordinary person skilled in the art before the earliest effective filing date of the claimed invention to incorporate verifying the information against expect values during a bootup process of a memory device taught by Sarkar/Liang to include booting a memory device using boot information provided from a host disclosed by Fai. The motivation for booting a memory device using boot information provided from a host by paragraph [0010] of Fai is for increasing the speed with which a memory device boots.
Regarding claim 9, these claims limitations are significantly similar to those of claim 2, and, therefore, are rejected on the same grounds.
Regarding claim 4, Sarkar combined further teaches The method as claimed in claim 1, further comprising: based on determining that the first identity information does not match with the second identity information (Sarkar: [0016]: “When the information does not correspond to the expected values (e.g., does not match or is not substantially similar to, outside of a tolerance threshold), this may indicate that the information has been modified in relation to a baseline version of the information, and the bootup process may or may not continue”),
The combination of Sarkar and Liang do not teach setting an error flag in a status register of the storage device.
However, Fai teaches setting an error flag in a status register of the storage device, wherein the error flag notifies the host device to execute each of the plurality of configuration operations of the boot sequence for booting the storage device (Fai: [0012]: “Updates and changes to the manner in which a memory device operates can be easily made by updating/changing the boot information provided by a host device to a memory device. For example, if an error is encountered with a memory device, a host device can cause the memory device to reboot using debug firmware”; [0024]: “the firmware 116-120 can be stored in NVM of the host device 102 and read out of NVM of the host device 102 as needed to boot the NVM package 104. The firmware 116-120 can be executed by the NVM package 104 to perform boot operations (e.g., initialize memory dies, load instructions for operating the NVM package 104 into volatile memory) and/or post-boot operations (e.g., read/write/erase operations, debug operations)”).
Disclosures by Sarkar, Liang and Fai are analogous because they are in the same field of endeavor of memory access and control.
It would have been obvious to an ordinary person skilled in the art before the earliest effective filing date of the claimed invention to incorporate verifying the information against expect values during a bootup process of a memory device taught by Sarkar/Liang to include generating an error log disclosed by Fai. The motivation for generating an error log by paragraph [0012] of Fai is for identifying a source of an error.
Regarding claim 11, these claims limitations are significantly similar to those of claim 4, and, therefore, are rejected on the same grounds.
Regarding claim 6, the combination of Sarkar and Liang do not teach exactly limitations of claim 6.
However, Fai further teaches The method as claimed in claim 1, further comprising: setting one or more bits into a capability register of the storage device to indicate that the storage device is configured to load the configuration data from the configuration file (Fai: [0003]: “a "raw" memory device (a memory device that does not include a memory controller) can boot using trim values that are stored in NVM of the memory device”; [0039]: “The registers 174 can be loaded with trim values 176 received from the host device 152. Trim values 156 can also and/or alternatively be used by the NVM of the NVM package 154”).
Disclosures by Sarkar, Liang and Fai are analogous because they are in the same field of endeavor of memory access and control.
It would have been obvious to an ordinary person skilled in the art before the earliest effective filing date of the claimed invention to incorporate verifying the information against expect values during a bootup process of a memory device taught by Sarkar/Liang to include registers to store trim values that used to boot the memory device disclosed by Fai. The motivation for include registers to store trim values that used to boot the memory device by paragraph [0010] of Fai is for minimizing delay to bootup the memory device.
Regarding claim 13, these claims limitations are significantly similar to those of claim 6, and, therefore, are rejected on the same grounds.
Claims 7 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Sarkar et al (2023/0359466) hereinafter Sarkar in view of Liang et al (2018/0232169) hereinafter Liang as applied to claims 1 and 8 respectively above, and further in view of JIN et al (2018/0275891) hereinafter JIN.
Regarding claim 7, Sarkar and Liang do not teach the limitation of claim 7.
However, JIN teaches The method as claimed in claim 1, wherein the storage device comprise a Solid State Drive (SSD), and wherein the SSD is configured to use a Non-Volatile Memory Express (NVMe) interface for communicating with the host device (JIN: [0023]: “The NVMe SSD based all flash array systems can benefit various applications, such as high performance computing and real-time large data analysis, because of fast performance of the all flash array systems”).
Disclosures by Sarkar, Liang and JIN are analogous because they are in the same field of endeavor of memory access and control.
It would have been obvious to an ordinary person skilled in the art before the earliest effective filing date of the claimed invention to incorporate verifying the information against expect values during a bootup process of a memory device taught by Sarkar/Liang to include a SSD using NVMe protocol disclosed by JIN. The motivation for include a SSD using NVMe protocol by paragraph [0023] of JIN is for high performance of the memory system.
Claims 15 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Sarkar et al (2023/0359466) hereinafter Sarkar in view of Nautiyal et al (2020/0104204) hereinafter Nautiyal.
Regarding claim 15, Sarkar teaches A method for booting a storage device comprising:
establishing a transport connection between the storage device and a host device (Sarkar: [0022]: “The host device 110 may communicate with the storage system 120 (e.g., the controller 130 of the storage system 120) via a host interface 150. The controller 130 and the memory device 140 may communicate via an input/output (I/O) interface 160”);
reading a capability register of the storage device to determine whether the storage device supports fast booting (Sarkar: [0032]: “the storage system may support both a fast boot process”; [0042]: “The controller may update or set the fast boot flag stored in the memory device to a second value indicating that the fast boot process is enabled, such as a value of “1” or “ENABLED.”; [0076]: “a controller of the storage system may retrieve fast boot information from a protected region of the memory device. The fast boot information may indicate a fast boot flag”);
based on determining that the storage device supports the fast booting, generating first identity information corresponding to an association of the storage device with the host device and communicating the first identity information to the storage device (Sarkar: [0036] “The fast boot flag may be associated with fast boot information stored in the memory device”; [0050]: “The controller may periodically compare the information stored in the memory device to the baseline version of the information, which may enable the controller to detect whether any changes have been made to the information”); and
Sarkar does not explicitly teach upon expiry of a timer, reading a status register of the storage device to determine whether the storage device has loaded configuration data from a configuration file related to the first identity information, the configuration data corresponding to one or more configuration operations related to a boot sequence, wherein the boot sequence comprises a plurality of configuration operations for booting the storage device.
However, Nautiyal teaches upon expiry of a timer (Nautiyal: [0015]: “The controller includes a programmable timer and a programmable timer register. The programmable timer register stores a timer value that is loaded by the safety core. The programmable timer runs periodically based on the timer value and the controller generates a timer interrupt signal when the programmable timer times out”), reading a status register of the storage device to determine whether the storage device has loaded configuration data from a configuration file related to the first identity information, the configuration data corresponding to one or more configuration operations related to a boot sequence, wherein the boot sequence comprises a plurality of configuration operations for booting the storage device (Nautiyal: [0046]: “The safety core 104 loads the configuration data from the main memory to its local memory and performs consistency checks on the configuration data. Based on the consistency checks, the safety core 104 generates a status indicator indicating the current status of the configuration data. The safety core 104 transmits a first transaction signal TS1 to the fault detection circuit 106 by way of the system bus 202 for accessing the first status register 216a to write the status indicator. Since the first transaction signal TS1 is transmitted by the safety core 104, it has the domain identifier ‘ID3’. The access control module 206 thus grants the safety core 104 a read-write access to the first status register 216a based on a match between the domain identifier ‘ID3’ of the first transaction signal TS1 and the domain identifier ‘ID3’ stored in the identification register 210. The safety core 104 writes the status indicator to the first status register 216a. Based on the status indicator, the first and second flag bits of the first status register 216a are modified. In one embodiment, if no fault is detected during the consistency checks of the configuration data, the first flag bit is reset and the second flag bit is set to indicate that the fault detection program 112 is running and ready to process the first and second progress data PD1 and PD2. The safety core 104 further loads the programmable timer register 222 with the timer value and the programmable timer 220 starts running based on the timer value”).
Disclosures by Sarkar and Nautiyal are analogous because they are in the same field of endeavor of memory access and control.
It would have been obvious to an ordinary person skilled in the art before the earliest effective filing date of the claimed invention to incorporate verifying the information against expect values during a bootup process of a memory device taught by Sarkar to include a status register disclosed by Nautiyal. The motivation for include the status register by paragraph [0034] of Nautiyal is for verifying the configuration data is stored in order to continue processing.
Regarding claim 17, Sarkar combined further teaches The method as claimed in claim 15, further comprising:
performing normal booting of the storage device by executing each of the plurality of configuration operations of the boot sequence for booting the storage device (Sarkar: Fig.5 to Fig. 9: booting processes) based on one of:
determining that the storage device does not support the fast booting (Sarkar: [0019]: “the controller may keep the initial factory configuration (e.g., keep the normal bootup process) and not enable the fast bootup process”);
determining that an error flag is set in the status register of the storage device; and
determining that the loading of the configuration data corresponding to the one or more configuration operations is unsuccessful.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Sarkar et al (2023/0359466) hereinafter Sarkar in view of Nautiyal et al (2020/0104204) hereinafter Nautiyal, as applied to claim 15 above, and further in view of Fai et al (2013/0007347) hereinafter Fai.
Regarding claim 16, the combination of Sarkar and Nautiyal do not explicitly teach exactly the current limitations of claim 16.
However, Fai teaches The method of claim 15, further comprising:
determining whether the host device is paired for a first time with the storage device (Fai: [0003]: “Memory devices have been configured to boot from information that is stored locally on the devices. For example, a memory device that includes a memory controller (with one or more processors/microprocessors) can boot using firmware that is stored in NVM of the memory device”); and
based on determining that the host device is paired for the first time with the storage device:
generating second identity information corresponding to an initial association of the storage device with the host device and communicating the second identity information to the storage device (Fai: [0024]: “The host device 102 can provide the firmware 116-120 to the NVM package 104 from the volatile memory. In other implementations, the firmware 116-120 can be stored in NVM of the host device 102 and read out of NVM of the host device 102 as needed to boot the NVM package 104”; [0006]: “ wherein transmission of the firmware to the memory device causes the memory device to boot using the firmware, wherein the memory device boots separately from the host device”); and
executing each of the plurality of configuration operations of the boot sequence for booting the storage device and instructing the storage device to save execution results of the one or more configuration operations related to the boot sequence into the configuration file (Fai: [0024]: “The host device 102 can provide the firmware 116-120 to the NVM package 104 from the volatile memory. In other implementations, the firmware 116-120 can be stored in NVM of the host device 102 and read out of NVM of the host device 102 as needed to boot the NVM package 104. The firmware 116-120 can be executed by the NVM package 104 to perform boot operations (e.g., initialize memory dies, load instructions for operating the NVM package 104 into volatile memory) and/or post-boot operations (e.g., read/write/erase operations, debug operations)”.
Disclosures by Sarkar, Nautiyal and Fai are analogous because they are in the same field of endeavor of memory access and control.
It would have been obvious to an ordinary person skilled in the art before the earliest effective filing date of the claimed invention to incorporate verifying the information against expect values during a bootup process of a memory device taught by Sarkar/ Nautiyal to include booting a memory device using boot information provided from a host disclosed by Fai. The motivation for booting a memory device using boot information provided from a host by paragraph [0010] of Fai is for increasing the speed with which a memory device boots.
RELEVANT ART CITED BY THE EXAMINER
The following prior art made of record and not relied upon is cited to establish the level
of skill in the applicant’s art and those arts considered reasonably pertinent to applicant’s
disclosure. See MPEP 707.05(c).
The prior art made of record and not relied upon is considered pertinent to applicant’s
disclosure. These references include:
Hsin (2012/0284497), which teaches a booting method of a main chip includes the following steps. The main chip searches a current block of a NAND Flash for reading a boot table from a current page of the current block and verifying a boot header of the boot table. When the boot header passes the verification, the main chip checks whether ID of the boot table and ID of the NAND Flash are the same. When the IDs of the boot table and the NAND Flash are the same, the main chip reads a next page of the current block and checks whether data stored in the current page and in the next page is the same. When the data stored in the current page and in the next page is the same, the main chip reads configuration information of the boot table to initialize the NAND Flash and boots; and
Porzio (2023/0259291) teaches techniques for identifying boot information stored at the memory array of the memory system and transferring the boot information to one or more locations of the memory array with a higher reliability. Based on or in response to transferring the boot information to the higher reliability locations of the memory array, the boot information may be accessed with reduced latency and reduced errors. The memory system may identify the boot information stored at the memory array based on or in response to a command received from the host system. During boot time, one or more boot operations may be associated with a time window or a timer for performing the respective boot operation.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAN V DOAN whose telephone number is (571)270-7250. The examiner can normally be reached Monday, Wednesday and Thursday from 10:45 AM to 4:45PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan Savla can be reached at 571-272-1077. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/HAN V DOAN/Examiner, Art Unit 2137
/Arpan P. Savla/Supervisory Patent Examiner, Art Unit 2137