DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Newly submitted claims 13-14 and 27 are directed to an invention that is independent or distinct from the invention originally claimed for the following reasons:
These claims contain “a second reset VCI.” This is the embodiment of applicant’s Fig. 6. But all of the original claims were directed to the embodiment Fig. 5.
Each of these claims recited “wherein a first plate of the reference capacitor is connected to a gate line for said pixels.” This language was in all the originally filed independent claims: claims 1, 13, and 17. The first plate of the reference capacitor is connected to the gate line in the embodiment of Fig. 5 but not in the embodiment of Fig. 6.
This language has now been eliminated from claims 13-14. This in combination with the second reset VCI of the claim make it clearly directed to the embodiment of Fig. 6, which was not originally claimed.1
Note that newly filed claim 27 adds backs the language directed to the gate line, making it unclear which embodiment this claim is directed to, but because it is dependent on claim 13 it will be assumed to be directed to Fig. 6 and also withdrawn.
Since applicant has received an action on the merits for the originally presented invention, this invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, claims 13-14 and 27 are withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03.
To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the restriction requirement. Otherwise, the election shall be treated as a final election without traverse. Traversal must be timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are subsequently added, applicant must indicate which of the subsequently added claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 17-18 and 26 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US 2018/0239940).
Regarding claim 17:
Kim discloses:
A capacitive sensor comprising a plurality of pixels (paragraph 6), each pixel comprising:
a capacitive sensing electrode (Fig. 6: C2);
a reference capacitor (Fig. 6: C1);
a sense voltage-controlled impedance, VCI (Fig. 6: T1); and
a select VCI (Fig. 6: T2);
wherein a first plate of the reference capacitor is connected to a gate line for said pixel (as seen in Fig. 6: it is connected to gate line SSi), and wherein a second plate of the reference capacitor is connected to each of a control terminal of the sense VCI (this is the gate of T1) and the capacitive sensing electrode (this is C2); and
wherein the select VCI is configured to selectively connect the sense VCI to a reference signal supply to selectively permit the sense VCI to output, on a read-out line of the pixel (Fig. 6: Oj) a readout signal indicative of a proximity to the capacitive sensing electrode of a conductive object (paragraph 124),
wherein the readout signal of the sense VCI is controlled primarily by a voltage difference between the read-out line and the capacitive sensing electrode (at least true in the case where NMOS transistors are used as per paragraph 135).
Regarding claim 18:
Kim discloses:
wherein the sensor is configured to activate a pixel by operating the select VCI of that pixel to connect the sense VCI of that pixel to the reference signal supply to permit said sense VCI to output a readout signal (paragraph 124).
Regarding claim 26:
Kim discloses:
Wherein a source terminal of the sense VCI is connected to the read-out line of the pixel (Kim paragraph 134).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-6, 8-10, and 20-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2018/0239940) in view of Taghibakhsh (US 2014/0266262) and further in view of Cho et al. (US 2007/0200832).
Regarding claim 1:
Kim discloses:
A capacitive sensor comprising a plurality of pixels (paragraph 6), each pixel comprising:
a capacitive sensing electrode (Fig. 6: C2);
a reference capacitor (Fig. 6: C1);
a sense voltage-controlled impedance, VCI (Fig. 6: T1);
a select VCI (Fig. 6: T2); and
a reset VCI (Fig. 6: T3);
wherein a first plate of the reference capacitor is connected to a gate line for said pixel (as seen in Fig. 6: it is connected to gate line SSi), and wherein a second plate of the reference capacitor is connected to each of: a conduction path of the reset VCI (as seen in Fig. 6 – this is T3), a control terminal of the sense VCI (as seen in Fig. 6 – this is T1), and the capacitive sensing electrode (as seen in Fig. 6: this is C2).
wherein the select VCI is configured to selectively connect the sense VCI to a reference signal supply (Fig. 6: it connects it to reference voltage line Pj).
wherein the reset VCI is configured to selectively connect the control terminal of the sense VCI to a reset voltage provider (as seen in Fig. 6; paragraph 72).
Kim does not disclose:
(A) “wherein the reset voltage provider is different than the reference signal supply.”
(B) "wherein the reset voltage provider is configured to provide a controllable reset voltage"
Regarding (A):
Taghibakhsh discloses:
wherein the reset voltage provider is different to the reference signal supply (paragraph 47)
It would have been obvious to one of ordinary skill in the art at the time the application was filed to include in Kim the elements taught by Taghibakhsh.
The rationale is as follows:
Kim and Taghibakhsh are directed to the same field of art.
Taghibakhsh discloses the reset voltage can be independent, which might be useful in some circumstances (paragraph 47). This is a known improvement that one of ordinary skill in the art could have included with predictable results.
Regarding (B):
Cho discloses:
wherein the reset voltage provider is configured to provide a controllable reset voltage (paragraphs 63-64).
It would have been obvious to include in Kim in view of Kim '504 the elements taught by Cho.
The rationale is as follows:
Kim, Taghibakhsh, and Cho are directed to the same field of art.
Cho discloses adjusting the reset voltage allows the sensing units to be in an appropriate output range (paragraph 63). This is a known improvement that one of ordinary skill in the art could have included with predictable results.
Regarding claim 3:
Kim, etc., discloses:
wherein the select VCI is configured to selectively connect the sense VCI to the reference signal supply to selectively permit the sense VCI to output a readout signal indicative of a proximity to the capacitive sensing electrode of a conductive object (e.g., Kim paragraph 17).
Regarding claim 4:
Kim, etc., discloses:
wherein a control terminal of the select VCI is connected to the gate line for said pixel (as seen in Kim Fig. 6: the gate of T2 is connected to the gate line).
Regarding claim 5:
Kim, etc., discloses:
wherein the sensor is configured to activate a pixel by operating the select VCI of that pixel to connect the sense VCI of that pixel to the reference signal supply to permit said sense VCI to output a readout signal (Kim paragraph 124).
Regarding claim 6:
Kim, etc., discloses:
wherein the select VCI is arranged to inhibit a sense VCI outputting a readout signal when said pixel is not activated (follows from Kim paragraph 124).
Regarding claim 8:
Kim, etc., discloses:
wherein the pixel is arranged so that an impedance of the sense VCI is controlled based on a capacitance from the capacitive sensing electrode, and wherein the select VCI is configured to selectively connect the sense VCI to a reference signal supply to permit the sense VCI to output a readout signal indicative of said capacitance (follows from Kim paragraphs 140-142)
Regarding claim 9:
Kim, etc., discloses:
wherein the sensor is configured to reset the reference capacitor prior to a subsequent activation of the pixel (paragraph 128: “initialized”).
Regarding claim 10:
Kim, etc., discloses:
wherein the sensor is configured to activate a sensor pixel by applying a gate drive signal to the gate line for that pixel (Kim paragraph 124).
Regarding claims 20:
All elements positively recited have already been identified with respect to earlier rejections. No further elaboration is necessary.
Claim 21:
Kim, etc., discloses:
wherein the sense VCI is configured to output, on a read-out line of the pixel, a readout signal indicative of a proximity to the capacitive sensing electrode of a conductive object (this is just the finger as per, e.g., paragraph 53), and wherein the readout signal of the sense VCI is controlled primarily by a voltage difference between the read-out line and the capacitive sensing electrode (as discussed earlier, true at the very least in the case of NMOS transistors).
Regarding claim 22:
Kim, etc., discloses:
further comprising a controller that is connected to the reset voltage provider and is configured to adjust and fix the reset voltage (Cho paragraph 63: “voltage adjusting unit”).
Regarding claim 23:
Kim, etc., discloses:
a dielectric shield overlying the plurality of pixels (Kim paragraph 43: “insulating material”), wherein the reset voltage is selected based on the thickness of a dielectric shield and/or a dielectric constant of the shield (while not explicitly discussed, since Cho sets the reset voltage with a test, it will take into account the properties of the sensor protective layer).
Regarding claim 24:
Kim, etc., discloses:
wherein the reset voltage is selected to tune the sensitivity of the pixel (Cho paragraph 63: setting it to an appropriate output range is tuning the sensitivity).
Claim(s) 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Taghibakhsh and further in view of Cho, and further in view of Yang et al. (US 2017/0162121).
Regarding claim 25:
Kim, etc., discloses a sensor as discussed above.
Kim, etc., does not disclose:
“wherein the reset voltage is selected so that, during sensing, the sense VCI is in a voltage range where an output current of the sense VCI varies linearly with a voltage at the control terminal of the sense VCI.”
Yang discloses:
the sense VCI is in a voltage range where an output current of the sense VCI varies linearly with a voltage at the control terminal of the sense VC (paragraph 84).
It would have been obvious to one of ordinary skill in the art at the time the application was filed to include in Kim, etc., wherein the reset voltage is selected so that, during sensing, the sense VCI is in a voltage range where an output current of the sense VCI varies linearly with a voltage at the control terminal of the sense VCI, as suggested by Yang.
The rationale is as follows:
Kim, Taghibakhsh, Cho, and Yang are directed to the same field of art.
Cho already suggests setting the reset voltage to bias the output to an appropriate range, but does not discuss what an appropriate range would be. Yang suggests it should be a range where the sense VCI varies linearly with a voltage. This is a known improvement one of ordinary skill in the art could have included with predictable results.
Response to Arguments
Applicant's arguments filed 30 April 2026 have been fully considered but they are not persuasive.
Applicant first argues their amendment to claim 13 and its dependent claims has overcome the 112 rejections. Probably it would, but this is now irrelevant as these claims are now directed to an embodiment of the invention that was never before claimed. As such they have been withdrawn and are no longer being considered.
Applicant next (starting page 9) argues with the rejection of claim 17. This argument is based on arguments submitted in a declaration filed 30 April 2026, which applicant calls the “Derckx declaration.” Note that there was already a Derckx declaration submitted 17 October 2025, so from here on the Examiner will refer to these as the April 2026 declaration and the October 2025 declaration if necessary to distinguish them.
The April 2026 declaration argues that an NMOS version of Kim’s Fig. 6 would not function correctly. But Kim explicitly states that they could be NMOS transistors (paragraph 135), so the presumption is that it would function. Furthermore, if they were NMOS transistors, the circuit shown in Fig. 6 of Kim and applicant’s Fig. 5 would be identical save for the source of the reset voltage. These are the same circuit. Every transistor and every component, including the read-out line, is connected in exactly the same way.
It might be reasonable argue that Kim’s would not work if there were any difference between the circuits. But hey are the same. It is very difficult for the Examiner to conclude that this circuit doesn’t meet applicant’s language when it appears to be the same one applicant themselves discloses. If there is some difference, perhaps applicant should explain what they believe it to be.
Perhaps applicant is basing this argument on the voltage levels shown in Fig. 7, which are opposite theirs (e.g., Fig. 4). But certainly it is within the level of ordinary skill to understand that if you swap the transistor type you need to adjust the high and low levels of the signals.
Since the prior art appears to show exactly the same circuit that applicant does, it is reasonable to conclude that it must perform the claimed function. How could it not? If it doesn’t, how does applicant’s circuit meet this language?
Applicant’s next argument (really starting page 11) is directed to the new language of the claim which recites “wherein the reset voltage provider is configured to provide a controllable reset voltage.”
The first argument essentially is that the voltage Kim ‘504 is different than a reset voltage. To satisfy applicant’s concerns, Taghibakhsh has been relied upon for an independent reset voltage instead, and Cho for the new language about it being controllable. Therefore these arguments have been addressed by the new grounds of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER RAY LAMB whose telephone number is (571)272-5264. The examiner can normally be reached 8:30-5:00 PM.
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/CHRISTOPHER R LAMB/ Primary Examiner, Art Unit 2622
1 Note the “second reset VCI” language was added in the amendment filed 17 October 2025. But the claims were not withdrawn at this time because they still contained the language directed to the first plate of the reference capacitor connected to the gate line, making it unclear what embodiment was being claimed. Due to amendment it is now clear applicant is attempting to claim a different embodiment that was not originally presented.
Prosecution Insights